Skip to content

X
x393
Commit 8ffbbc62 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

added save/load state with pickle

parent 82800325
Show whitespace changes
Inline Side-by-side
Showing with 88 additions and 16 deletions
py393/args
View file @ 8ffbbc62
......@@ -2,6 +2,7 @@
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-p NEWPAR='h3ff
-c write_mem 0x377 25
-c read_mem 0x3ff
......
py393/hargs
View file @ 8ffbbc62
......@@ -2,5 +2,5 @@
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p NEWPAR='h3ff
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-i
\ No newline at end of file
py393/hargs-auto
View file @ 8ffbbc62
......@@ -2,6 +2,7 @@
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c measure_all "ICWRPOASZ" 1 2 2 3
-c set_phase_delays 15 'A' 'A' 1 None 0
-c save
py393/vrlg.py
View file @ 8ffbbc62
......@@ -463,7 +463,7 @@ STATUS_SEQ_SHFT__RAW = str
DLY_DM_ODELAY__TYPE = str
MCONTR_PHY_0BIT_DCI_RST__RAW = str
REFCLK_FREQUENCY__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
MCONTR_RD_MASK__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
TILE_VSTEP = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
......@@ -475,6 +475,7 @@ WRITE_BLOCK_OFFSET = int
COLADDR_NUMBER__TYPE = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
TEST01_SUSPEND__TYPE = str
PICKLE = str
NUM_CYCLES_15__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
......@@ -487,6 +488,7 @@ SCANLINE_EXTRA_PAGES = int
READ_PATTERN_OFFSET__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
TILE_HEIGHT__RAW = str
PICKLE__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
DIVCLK_DIVIDE = int
......@@ -505,7 +507,7 @@ TILED_EXTRA_PAGES = int
MCNTRL_PS_EN_RST__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
CLK_PHASE__RAW = str
MCONTR_RD_MASK__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
MCONTR_PHY_16BIT_ADDR__TYPE = str
TILED_STARTY = int
TILED_STARTX = int
......@@ -690,6 +692,7 @@ CLK_DIV_PHASE__RAW = str
LD_DLY_LANE1_IDELAY = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
PICKLE__RAW = str
NUM_CYCLES_02__RAW = str
TEST01_NEXT_PAGE__RAW = str
DQSTRI_LAST__RAW = str
......
py393/x393_mcntrl_adjust.py
View file @ 8ffbbc62
......@@ -29,6 +29,7 @@ __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import sys
import pickle
#import x393_mem
#x393_pio_sequences
#from import_verilog_parameters import VerilogParameters
......@@ -2973,6 +2974,11 @@ class X393McntrlAdjust(object):
'keep_all':False,
'set_table':True,
'quiet':quiet+1}},
{'key':'S',
'func':self.save_mcntrl,
'comment':'Save current state as Python pickle',
'params':{'path': None, # use path defined by the parameter 'PICKLE'
'quiet':quiet+1}},
{'key':'Z',
'func':self.show_all_vs_phase,
'comment':'Printing results table (delays and errors vs. phase)- all, including invalid phases',
......@@ -3970,3 +3976,40 @@ class X393McntrlAdjust(object):
keep_all=keep_all,
set_table=False,
quiet=2)
def save_mcntrl(self,
path=None,
quiet=1):
"""
Save memory controller delays measuremnt/adjustment state to file
@param path location to save state or None to use path defined by parameter PICKLE
@return None, raises exception if path is not provided and PICKLE is not defined
"""
if path is None:
try:
path=vrlg.PICKLE
except:
raise Exception ("path is not provided and Verilog parameter PICKLE is not defined")
pickle.dump(self.adjustment_state, open(path, "wb" ))
if quiet <2:
print ("mcntrl state (self.adjustment_state) is saved to %s"%(path))
def load_mcntrl(self,
path=None,
quiet=1):
"""
Load memory controller delays measuremnt/adjustment state from file
@param path location to load state from or None to use path defined by parameter PICKLE
@return None, raises exception if path is not provided and PICKLE is not defined
"""
if path is None:
try:
path=vrlg.PICKLE
except:
raise Exception ("path is not provided and Verilog parameter PICKLE is not defined")
self.adjustment_state=pickle.load(open(path, "rb" ))
if quiet <2:
print ("mcntrl state (self.adjustment_state) is loaded from %s"%(path))
if quiet<1:
print ("self.adjustment_state=",self.adjustment_state)
\ No newline at end of file
py393/x393_mcntrl_buffers.py
View file @ 8ffbbc62
......@@ -39,6 +39,8 @@ import x393_axi_control_status
#from verilog_utils import hx, concat, bits, getParWidth
#from verilog_utils import concat, getParWidth
#from x393_axi_control_status import concat, bits
from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32
import vrlg
class X393McntrlBuffers(object):
DRY_MODE= True # True
......@@ -167,19 +169,41 @@ class X393McntrlBuffers(object):
show_rslt=True):
"""
Fill buffer the incremental data (each next register is written with previous register data + 1
<start_word_address> full register address in AXI space (in 32-bit words, not bytes)
<num_read> number of 32-bit words to read
<show_rslt> print buffer data read
@param start_word_address full register address in AXI space (in 32-bit words, not bytes)
@param num_read number of 32-bit words to read
@param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words)
"""
if (self.verbose>1) or show_rslt:
if (self.verbose>1) or (show_rslt==1):
print("**** read_block_buf, start_word_address=0x%x, num_read=0x%x "%(start_word_address,num_read))
result=[]
for i in range(num_read): #for (i = 0; i < num_read; i = i + 16) begin
d=self.x393_mem.axi_read_addr_w(start_word_address+i)
if (self.verbose>2) or show_rslt:
if (self.verbose>2) or (show_rslt==1):
print(" read_block_buf 0x%x:0x%x"%(start_word_address+i,d))
result.append(d)
if show_rslt==16:
rslt16=convert_w32_to_mem16(result)
sum_read16=0
for d in rslt16:
sum_read16+=d
print("read16 (0x%x):"%(sum_read16),end="")
for i in range(len(rslt16)):
if (i & 0x1f) == 0:
print("\n%03x:"%i,end=" ")
print("%04x"%rslt16[i],end=" ")
print("\n")
elif show_rslt==32:
sum_rd_buf=0
for d in result:
sum_rd_buf+=d
print("read buffer: (0x%x):"%(sum_rd_buf),end="")
for i in range(len(result)):
if (i & 0xf) == 0:
print("\n%03x:"%i,end=" ")
print("%08x"%result[i],end=" ")
print("\n")
return result
def read_block_buf_chn(self, # S uppressThisWarning VEditor : may be unused
......@@ -189,10 +213,10 @@ class X393McntrlBuffers(object):
show_rslt=True):
"""
Fill buffer the incremental data (each next register is written with previous register data + 1
<chn> 4-bit buffer channel (0..4) to read from
<page> 2-bit buffer page to read from
<num_read> number of 32-bit words to read
<show_rslt> print buffer data read
@param chn 4-bit buffer channel (0..4) to read from
@param page 2-bit buffer page to read from
@param num_read number of 32-bit words to read
@param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words)
"""
start_addr=-1
if chn==0: start_addr=vrlg.MCONTR_BUF0_RD_ADDR + (page << 8)
......
py393/x393_pio_sequences.py
View file @ 8ffbbc62
......@@ -958,10 +958,10 @@ class X393PIOSequences(object):
wait_complete=1): # Wait for operation to complete
"""
Read pattern
<num> number of 32-bit words to read
<show_rslt> print read data
<wait_complete> wait read pattern operation to complete (0 - may initiate multiple PS PIO operations)
returns list of the read data
@param num number of 32-bit words to read
@param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words)
@param wait_complete wait read pattern operation to complete (0 - may initiate multiple PS PIO operations)
@return list of the read data
"""
self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment