diff --git a/py393/args b/py393/args index efc07ed64214735bbda3950558c785d27546dfef..3d0f7dd5db547980c7bc3af10dcfddc68738fb8b 100644 --- a/py393/args +++ b/py393/args @@ -2,6 +2,7 @@ -f ../system_defines.vh -f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh -l ../includes/x393_cur_params_target_gen.vh +-p PICKLE="../includes/x393_mcntrl.pickle" -p NEWPAR='h3ff -c write_mem 0x377 25 -c read_mem 0x3ff diff --git a/py393/hargs b/py393/hargs index 848171c01839aa6c04d987a72e5392a702d5ea7f..7aad1fb412b6d9efc988a19d096113813c5e95c1 100644 --- a/py393/hargs +++ b/py393/hargs @@ -2,5 +2,5 @@ -f /usr/local/verilog/system_defines.vh -f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh -l /usr/local/verilog/x393_cur_params_target.vh --p NEWPAR='h3ff +-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle -i \ No newline at end of file diff --git a/py393/hargs-auto b/py393/hargs-auto index f5004e892d065c1e981178a6c39227758781dd1b..5235b99222b0691755b8faea318859f6a17edd95 100644 --- a/py393/hargs-auto +++ b/py393/hargs-auto @@ -2,6 +2,7 @@ -f /usr/local/verilog/system_defines.vh -f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh -l /usr/local/verilog/x393_cur_params_target.vh +-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle -c measure_all "ICWRPOASZ" 1 2 2 3 -c set_phase_delays 15 'A' 'A' 1 None 0 -c save diff --git a/py393/vrlg.py b/py393/vrlg.py index 745fbe422e8c852669dadd6ae865f67a29caa7b1..dda1f4544f1e13b83b498111ed96cbc308471fa6 100644 --- a/py393/vrlg.py +++ b/py393/vrlg.py @@ -463,7 +463,7 @@ STATUS_SEQ_SHFT__RAW = str DLY_DM_ODELAY__TYPE = str MCONTR_PHY_0BIT_DCI_RST__RAW = str REFCLK_FREQUENCY__RAW = str -MCONTR_PHY_0BIT_DLY_RST = int +MCONTR_RD_MASK__RAW = str MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str TILE_VSTEP = int DFLT_DQS_TRI_OFF_PATTERN__TYPE = str @@ -475,6 +475,7 @@ WRITE_BLOCK_OFFSET = int COLADDR_NUMBER__TYPE = str MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int TEST01_SUSPEND__TYPE = str +PICKLE = str NUM_CYCLES_15__RAW = str MCONTR_PHY_0BIT_ADDR_MASK = int MCNTRL_TILED_TILE_WHS__TYPE = str @@ -487,6 +488,7 @@ SCANLINE_EXTRA_PAGES = int READ_PATTERN_OFFSET__RAW = str MCNTRL_SCANLINE_CHN1_ADDR__RAW = str TILE_HEIGHT__RAW = str +PICKLE__TYPE = str MCONTR_PHY_0BIT_CKE_EN__TYPE = str MCNTRL_TILED_MODE__TYPE = str DIVCLK_DIVIDE = int @@ -505,7 +507,7 @@ TILED_EXTRA_PAGES = int MCNTRL_PS_EN_RST__RAW = str MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str CLK_PHASE__RAW = str -MCONTR_RD_MASK__RAW = str +MCONTR_PHY_0BIT_DLY_RST = int MCONTR_PHY_16BIT_ADDR__TYPE = str TILED_STARTY = int TILED_STARTX = int @@ -690,6 +692,7 @@ CLK_DIV_PHASE__RAW = str LD_DLY_LANE1_IDELAY = int MCONTR_PHY_16BIT_PATTERNS__TYPE = str MCONTR_PHY_0BIT_CKE_EN__RAW = str +PICKLE__RAW = str NUM_CYCLES_02__RAW = str TEST01_NEXT_PAGE__RAW = str DQSTRI_LAST__RAW = str diff --git a/py393/x393_mcntrl_adjust.py b/py393/x393_mcntrl_adjust.py index e41cbddaedcab4b3d312d9e450479be37228a6ed..14ec89217876fe8970bd43e79ccd5e61bc4021d4 100644 --- a/py393/x393_mcntrl_adjust.py +++ b/py393/x393_mcntrl_adjust.py @@ -29,6 +29,7 @@ __maintainer__ = "Andrey Filippov" __email__ = "andrey@elphel.com" __status__ = "Development" import sys +import pickle #import x393_mem #x393_pio_sequences #from import_verilog_parameters import VerilogParameters @@ -2973,6 +2974,11 @@ class X393McntrlAdjust(object): 'keep_all':False, 'set_table':True, 'quiet':quiet+1}}, + {'key':'S', + 'func':self.save_mcntrl, + 'comment':'Save current state as Python pickle', + 'params':{'path': None, # use path defined by the parameter 'PICKLE' + 'quiet':quiet+1}}, {'key':'Z', 'func':self.show_all_vs_phase, 'comment':'Printing results table (delays and errors vs. phase)- all, including invalid phases', @@ -3970,3 +3976,40 @@ class X393McntrlAdjust(object): keep_all=keep_all, set_table=False, quiet=2) + def save_mcntrl(self, + path=None, + quiet=1): + """ + Save memory controller delays measuremnt/adjustment state to file + @param path location to save state or None to use path defined by parameter PICKLE + @return None, raises exception if path is not provided and PICKLE is not defined + """ + if path is None: + try: + path=vrlg.PICKLE + except: + raise Exception ("path is not provided and Verilog parameter PICKLE is not defined") + pickle.dump(self.adjustment_state, open(path, "wb" )) + if quiet <2: + print ("mcntrl state (self.adjustment_state) is saved to %s"%(path)) + + def load_mcntrl(self, + path=None, + quiet=1): + """ + Load memory controller delays measuremnt/adjustment state from file + @param path location to load state from or None to use path defined by parameter PICKLE + @return None, raises exception if path is not provided and PICKLE is not defined + """ + if path is None: + try: + path=vrlg.PICKLE + except: + raise Exception ("path is not provided and Verilog parameter PICKLE is not defined") + self.adjustment_state=pickle.load(open(path, "rb" )) + if quiet <2: + print ("mcntrl state (self.adjustment_state) is loaded from %s"%(path)) + if quiet<1: + print ("self.adjustment_state=",self.adjustment_state) + + \ No newline at end of file diff --git a/py393/x393_mcntrl_buffers.py b/py393/x393_mcntrl_buffers.py index 6d59cdeb3551c9ffb6e01b6306a8bd4c3ebd2df4..50d4feb766c8ae7a3a084e9898e012d1a45a531f 100644 --- a/py393/x393_mcntrl_buffers.py +++ b/py393/x393_mcntrl_buffers.py @@ -39,6 +39,8 @@ import x393_axi_control_status #from verilog_utils import hx, concat, bits, getParWidth #from verilog_utils import concat, getParWidth #from x393_axi_control_status import concat, bits +from verilog_utils import convert_w32_to_mem16 #,convert_mem16_to_w32 + import vrlg class X393McntrlBuffers(object): DRY_MODE= True # True @@ -167,19 +169,41 @@ class X393McntrlBuffers(object): show_rslt=True): """ Fill buffer the incremental data (each next register is written with previous register data + 1 - full register address in AXI space (in 32-bit words, not bytes) - number of 32-bit words to read - print buffer data read + @param start_word_address full register address in AXI space (in 32-bit words, not bytes) + @param num_read number of 32-bit words to read + @param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words) """ - if (self.verbose>1) or show_rslt: + if (self.verbose>1) or (show_rslt==1): print("**** read_block_buf, start_word_address=0x%x, num_read=0x%x "%(start_word_address,num_read)) result=[] for i in range(num_read): #for (i = 0; i < num_read; i = i + 16) begin d=self.x393_mem.axi_read_addr_w(start_word_address+i) - if (self.verbose>2) or show_rslt: + if (self.verbose>2) or (show_rslt==1): print(" read_block_buf 0x%x:0x%x"%(start_word_address+i,d)) result.append(d) + if show_rslt==16: + rslt16=convert_w32_to_mem16(result) + sum_read16=0 + for d in rslt16: + sum_read16+=d + print("read16 (0x%x):"%(sum_read16),end="") + for i in range(len(rslt16)): + if (i & 0x1f) == 0: + print("\n%03x:"%i,end=" ") + print("%04x"%rslt16[i],end=" ") + print("\n") + elif show_rslt==32: + sum_rd_buf=0 + for d in result: + sum_rd_buf+=d + print("read buffer: (0x%x):"%(sum_rd_buf),end="") + for i in range(len(result)): + if (i & 0xf) == 0: + print("\n%03x:"%i,end=" ") + print("%08x"%result[i],end=" ") + print("\n") + return result def read_block_buf_chn(self, # S uppressThisWarning VEditor : may be unused @@ -189,10 +213,10 @@ class X393McntrlBuffers(object): show_rslt=True): """ Fill buffer the incremental data (each next register is written with previous register data + 1 - 4-bit buffer channel (0..4) to read from - 2-bit buffer page to read from - number of 32-bit words to read - print buffer data read + @param chn 4-bit buffer channel (0..4) to read from + @param page 2-bit buffer page to read from + @param num_read number of 32-bit words to read + @param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words) """ start_addr=-1 if chn==0: start_addr=vrlg.MCONTR_BUF0_RD_ADDR + (page << 8) diff --git a/py393/x393_pio_sequences.py b/py393/x393_pio_sequences.py index 3969a8a93590fb0f6ae9a974a53434ec888ee912..8f7c7fe1f48410f075751ff74f692aef7b60bd6e 100644 --- a/py393/x393_pio_sequences.py +++ b/py393/x393_pio_sequences.py @@ -958,10 +958,10 @@ class X393PIOSequences(object): wait_complete=1): # Wait for operation to complete """ Read pattern - number of 32-bit words to read - print read data - wait read pattern operation to complete (0 - may initiate multiple PS PIO operations) - returns list of the read data + @param num number of 32-bit words to read + @param show_rslt print buffer data read 1 - column, 16 - as 16-bit (memory words), 32 - as 32-bit (data words) + @param wait_complete wait read pattern operation to complete (0 - may initiate multiple PS PIO operations) + @return list of the read data """ self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)