made the whole program to run automatically from the command file (82800325) · Commits · Elphel / x393

py393/x393_mcntrl_adjust.py

+21 −5

Original line number	Diff line number	Diff line
		@@ -2838,7 +2838,7 @@ class X393McntrlAdjust(object):
		return cmd_odelay

		def measure_all(self,
		tasks="CWRPOAZ",
		tasks="ICWRPOASZ",
		prim_steps=1,
		primary_set_in=2,
		primary_set_out=2,
		@@ -2869,9 +2869,14 @@ class X393McntrlAdjust(object):
		safe_phase=0.25 # 0: strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
		commonFine=True, # use same values for fine delay for address/bank lines
		addr_odly_max_err= 0.125 # 1/8 period
		task_data=[
		{'key':'I',
		'func':self.x393_pio_sequences.task_set_up,
		'comment':'Initial setup - memory controller, sequnces',
		'params':{'quiet':quiet+1}},


		task_data=[{'key':'C',
		{'key':'C',
		'func':self.adjust_cmda_odelay,
		'comment':'Measuring CMDA output delay for each clock phase',
		'params':{'start_phase':0,
		@@ -2957,6 +2962,17 @@ class X393McntrlAdjust(object):
		'max_err':addr_odly_max_err,
		'quiet':quiet+1}},

		{'key':'S',
		'func':self.get_delays_vs_phase,
		'comment':'Setting calculated delays to global parameters to be used when setting phase',
		'params':{'filter_dqo': 2,
		'filter_dqi': 2,
		'filter_dqso':2,
		'filter_dqsi':2,
		'filter_cmda':2,
		'keep_all':False,
		'set_table':True,
		'quiet':quiet+1}},
		{'key':'Z',
		'func':self.show_all_vs_phase,
		'comment':'Printing results table (delays and errors vs. phase)- all, including invalid phases',

py393/x393_mcntrl_tests.py

+4 −31

Original line number	Diff line number	Diff line
		@@ -105,6 +105,7 @@ class X393McntrlTests(object):
		((0,1)[write_mem],1), # write_mem,
		((0,1)[enable], 1), #enable,
		((1,0)[chn_reset],1)) # ~chn_reset};
		'''
		def task_set_up(self,
		set_per_pin_delays=0):
		"""
		@@ -121,7 +122,7 @@ class X393McntrlTests(object):
		write buffer latency
		<set_per_pin_delays> - 1 - set individual (per-pin) I/O delays, 0 - use common for the whole class
		Returns 1 if phase was set, 0 if it failed
		"""

		#reset memory controller
		self.x393_axi_tasks.enable_memcntrl(0)
		#enable memory controller
		@@ -133,7 +134,7 @@ class X393McntrlTests(object):
		# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
		self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns()
		# prepare all sequences
		self.set_all_sequences()
		self.x393_pio_sequences.set_all_sequences()
		# prepare write buffer
		self.x393_mcntrl_buffers.write_block_buf_chn(0,0,256); # fill block memory (channel, page, number)
		# set all delays
		@@ -159,36 +160,8 @@ class X393McntrlTests(object):
		self.x393_mcntrl_timing.axi_set_wbuf_delay(vrlg.WBUF_DLY_DFLT)
		self.x393_axi_tasks.read_all_status()
		return 1
		'''

		def set_all_sequences(self):
		"""
		Set all sequences: MRS, REFRESH, WRITE LEVELLING, READ PATTERN, WRITE BLOCK, READ BLOCK
		"""
		if self.verbose>0: print("SET MRS")
		self.x393_pio_sequences.set_mrs(1) # reset DLL
		if self.verbose>0: print("SET REFRESH")
		self.x393_pio_sequences.set_refresh(
		vrlg.T_RFC, # input [ 9:0] t_rfc; # =50 for tCK=2.5ns
		vrlg.T_REFI) #input [ 7:0] t_refi; # 48/97 for normal, 16 - for simulation
		if self.verbose>0: print("SET WRITE LEVELING")
		self.x393_pio_sequences.set_write_lev(16) # write leveling, 16 times (full buffer - 128)
		if self.verbose>0: print("SET READ PATTERNt")
		self.x393_pio_sequences.set_read_pattern(8) # 8x2*64 bits, 32x32 bits to read
		if self.verbose>0: print("SET WRITE BLOCK")
		self.x393_pio_sequences.set_write_block(
		5, # 3'h5, # bank
		0x1234, # 15'h1234, # row address
		0x100 # 10'h100 # column address
		)

		if self.verbose>0: print("SET READ BLOCK");
		self.x393_pio_sequences.set_read_block (
		5, # 3'h5, # bank
		0x1234, # 15'h1234, # row address

		0x100 # 10'h100 # column address
		)
		self.x393_axi_tasks.set_sequences_set(1) # Mark sequences as being set
		def init_ddr3(self,
		refresh=1,
		wait_complete=True):

py393/x393_mcntrl_timing.py

+8 −8

Original line number	Diff line number	Diff line
		@@ -164,18 +164,18 @@ class X393McntrlTiming(object):
		# self.x393_axi_tasks.write_contol_register(vrlg.LD_DLY_LANE1_IDELAY + 8, vrlg.DLY_LANE1_DQS_WLV_IDELAY)
		self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0)

		def axi_set_delays(self): # set all individual delays
		def axi_set_delays(self,quiet=1): # set all individual delays
		"""
		Set all DDR3 I/O delays to individual parameter-defined values (using default values,
		current ones are supposed to be synchronized)
		"""
		self.axi_set_dq_idelay()
		self.axi_set_dqs_idelay()
		self.axi_set_dq_odelay()
		self.axi_set_dqs_odelay()
		self.axi_set_dm_odelay()
		self.axi_set_cmda_odelay()
		self.axi_set_phase()
		self.axi_set_dq_idelay(quiet=quiet)
		self.axi_set_dqs_idelay(quiet=quiet)
		self.axi_set_dq_odelay(quiet=quiet)
		self.axi_set_dqs_odelay(quiet=quiet)
		self.axi_set_dm_odelay(quiet=quiet)
		self.axi_set_cmda_odelay(quiet=quiet)
		self.axi_set_phase(quiet=quiet)

		def axi_set_dq_idelay(self, # sets same delay to all dq idelay
		delay=None, # input [7:0] delay;

py393/x393_pio_sequences.py

+90 −0

Original line number	Diff line number	Diff line
		@@ -32,6 +32,7 @@ __status__ = "Development"
		#import x393_mem
		#x393_pio_sequences
		#from import_verilog_parameters import VerilogParameters
		from x393_mcntrl_timing import X393McntrlTiming
		from x393_mem import X393Mem
		#from x393_axi_control_status import X393AxiControlStatus
		import x393_axi_control_status
		@@ -48,6 +49,7 @@ class X393PIOSequences(object):
		# vpars=None
		x393_mem=None
		x393_axi_tasks=None #x393X393AxiControlStatus
		x393_mcntrl_timing=None
		target_phase=0 # TODO: set!
		def __init__(self, debug_mode=1,dry_mode=True):
		self.DEBUG_MODE=debug_mode
		@@ -56,6 +58,7 @@ class X393PIOSequences(object):
		# self.x393_axi_tasks=X393AxiControlStatus(debug_mode,dry_mode)
		self.x393_axi_tasks=x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
		self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
		self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
		# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
		'''
		Maybe import parameters into the module, not class namespace to use directly, w/o self. ?
		@@ -911,6 +914,44 @@ class X393PIOSequences(object):
		self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
		cmd_addr += 1

		def set_all_sequences(self, quiet=1):
		"""
		Set all sequences: MRS, REFRESH, WRITE LEVELLING, READ PATTERN, WRITE BLOCK, READ BLOCK
		"""
		if quiet < 3 :
		print("SET MRS")
		self.set_mrs(1) # reset DLL
		if quiet < 3 :
		print("SET REFRESH")
		self.set_refresh(
		vrlg.T_RFC, # input [ 9:0] t_rfc; # =50 for tCK=2.5ns
		vrlg.T_REFI) #input [ 7:0] t_refi; # 48/97 for normal, 16 - for simulation
		if quiet < 3:
		print("SET WRITE LEVELING")
		self.set_write_lev(16) # write leveling, 16 times (full buffer - 128)
		if quiet < 3:
		print("SET READ PATTERNt")
		self.set_read_pattern(8) # 8x2*64 bits, 32x32 bits to read
		if quiet < 3:
		print("SET WRITE BLOCK")
		self.set_write_block(
		5, # 3'h5, # bank
		0x1234, # 15'h1234, # row address
		0x100 # 10'h100 # column address
		)

		if quiet < 3:
		print("SET READ BLOCK");
		self.set_read_block (
		5, # 3'h5, # bank
		0x1234, # 15'h1234, # row address

		0x100 # 10'h100 # column address
		)
		self.x393_axi_tasks.set_sequences_set(1) # Mark sequences as being set



		def read_pattern(self,
		num,
		show_rslt,
		@@ -1115,3 +1156,52 @@ class X393PIOSequences(object):
		wait_complete ); # wait_complete; # Do not request a newe transaction from the scheduler until previous memory transaction is finished
		# Wait PS PIO sequence DOEN
		self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE, 1 , 2.0); # wait FIFO not half full, sync sequences, timeout 2 sec



		def task_set_up(self,
		quiet = 1):
		"""
		Initial setup of the memory controller, including:
		disable (and reset) memory controller
		enable memory controller
		setup status generation in all modules
		tristate patterns
		DQS/DQM patterns
		all sequences
		channel 0 buffer data
		I/O delays
		clock phase
		write buffer latency
		<set_per_pin_delays> - 1 - set individual (per-pin) I/O delays, 0 - use common for the whole class
		Returns 1 if phase was set, 0 if it failed
		"""
		#reset memory controller
		self.x393_axi_tasks.enable_memcntrl(0)
		#enable memory controller
		self.x393_axi_tasks.enable_memcntrl(1)
		#program status for all used modules to refresh at any bit change
		self.x393_axi_tasks.program_status_all(3, 0)
		# set dq /dqs tristate on/off patterns
		self.x393_mcntrl_timing.axi_set_tristate_patterns()
		# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
		self.x393_mcntrl_timing.axi_set_dqs_dqm_patterns()
		# prepare all sequences
		self.set_all_sequences(quiet)
		# prepare write buffer
		self.x393_mcntrl_buffers.write_block_buf_chn(0,0,256,quiet); # fill block memory (channel, page, number)
		# set all delays
		# Make it an only option TODO: do the same for the simulation!!
		self.x393_mcntrl_timing.axi_set_delays() # set all individual delays, aslo runs axi_set_phase()
		# set clock phase relative to DDR clk
		#phase already set in axi_set_delays
		# print("Debugging: sleeping for 1 second")
		# sleep(1)
		# phaseOK=self.x393_mcntrl_timing.axi_set_phase(vrlg.DLY_PHASE,wait_phase_en=True); # wait for phase set
		# if not phaseOK:
		# print("Failed to set clock phase")
		# return 0
		# read and print status (optional)
		self.x393_mcntrl_timing.axi_set_wbuf_delay(vrlg.WBUF_DLY_DFLT)
		self.x393_axi_tasks.read_all_status()
		return 1

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