Commit 8ffbbc62 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

added save/load state with pickle

parent 82800325

py393/args

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
-f ../system_defines.vh

-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh

-l ../includes/x393_cur_params_target_gen.vh

-p PICKLE="../includes/x393_mcntrl.pickle"

-p NEWPAR='h3ff

-c write_mem 0x377 25

-c read_mem 0x3ff

py393/hargs

+1 −1
Original line number Diff line number Diff line
@@ -2,5 +2,5 @@ 
-f /usr/local/verilog/system_defines.vh

-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh

-l /usr/local/verilog/x393_cur_params_target.vh

-p NEWPAR='h3ff

-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle

-i
 
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py393/hargs-auto

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
-f /usr/local/verilog/system_defines.vh

-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh

-l /usr/local/verilog/x393_cur_params_target.vh

-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle

-c measure_all "ICWRPOASZ" 1 2 2 3

-c set_phase_delays 15 'A' 'A' 1 None 0

-c save

py393/vrlg.py

+5 −2
Original line number Diff line number Diff line
@@ -463,7 +463,7 @@ STATUS_SEQ_SHFT__RAW = str 
DLY_DM_ODELAY__TYPE = str

MCONTR_PHY_0BIT_DCI_RST__RAW = str

REFCLK_FREQUENCY__RAW = str

MCONTR_PHY_0BIT_DLY_RST = int

MCONTR_RD_MASK__RAW = str

MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str

TILE_VSTEP = int

DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
@@ -475,6 +475,7 @@ WRITE_BLOCK_OFFSET = int 
COLADDR_NUMBER__TYPE = str

MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int

TEST01_SUSPEND__TYPE = str

PICKLE = str

NUM_CYCLES_15__RAW = str

MCONTR_PHY_0BIT_ADDR_MASK = int

MCNTRL_TILED_TILE_WHS__TYPE = str
@@ -487,6 +488,7 @@ SCANLINE_EXTRA_PAGES = int 
READ_PATTERN_OFFSET__RAW = str

MCNTRL_SCANLINE_CHN1_ADDR__RAW = str

TILE_HEIGHT__RAW = str

PICKLE__TYPE = str

MCONTR_PHY_0BIT_CKE_EN__TYPE = str

MCNTRL_TILED_MODE__TYPE = str

DIVCLK_DIVIDE = int
@@ -505,7 +507,7 @@ TILED_EXTRA_PAGES = int 
MCNTRL_PS_EN_RST__RAW = str

MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str

CLK_PHASE__RAW = str

MCONTR_RD_MASK__RAW = str

MCONTR_PHY_0BIT_DLY_RST = int

MCONTR_PHY_16BIT_ADDR__TYPE = str

TILED_STARTY = int

TILED_STARTX = int
@@ -690,6 +692,7 @@ CLK_DIV_PHASE__RAW = str 
LD_DLY_LANE1_IDELAY = int

MCONTR_PHY_16BIT_PATTERNS__TYPE = str

MCONTR_PHY_0BIT_CKE_EN__RAW = str

PICKLE__RAW = str

NUM_CYCLES_02__RAW = str

TEST01_NEXT_PAGE__RAW = str

DQSTRI_LAST__RAW = str

py393/x393_mcntrl_adjust.py

+43 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ __maintainer__ = "Andrey Filippov" 
__email__ = "andrey@elphel.com"

__status__ = "Development"

import sys

import pickle

#import x393_mem

#x393_pio_sequences

#from import_verilog_parameters import VerilogParameters
@@ -2973,6 +2974,11 @@ class X393McntrlAdjust(object): 
                              'keep_all':False,

                              'set_table':True,

                              'quiet':quiet+1}},

                    {'key':'S',

                    'func':self.save_mcntrl,

                    'comment':'Save current state as Python pickle',

                    'params':{'path': None, # use path defined by the parameter 'PICKLE'

                              'quiet':quiet+1}},

                    {'key':'Z',

                    'func':self.show_all_vs_phase,

                    'comment':'Printing results table (delays and errors vs. phase)- all, including invalid phases',
@@ -3970,3 +3976,40 @@ class X393McntrlAdjust(object): 
                            keep_all=keep_all,

                            set_table=False,

                            quiet=2)    

    def save_mcntrl(self,

                    path=None,

                    quiet=1):

        """

        Save memory controller delays measuremnt/adjustment state to file

        @param path location to save state or None to use path defined by parameter PICKLE

        @return None, raises exception if path is not provided and PICKLE is not defined

        """

        if path is None:

            try:

                path=vrlg.PICKLE

            except:

                raise Exception ("path is not provided and Verilog parameter PICKLE is not defined")

        pickle.dump(self.adjustment_state, open(path, "wb" ))

        if quiet <2:

            print ("mcntrl state (self.adjustment_state) is saved to %s"%(path))

        

    def load_mcntrl(self,

                    path=None,

                    quiet=1):

        """

        Load memory controller delays measuremnt/adjustment state from file

        @param path location to load state from or None to use path defined by parameter PICKLE

        @return None, raises exception if path is not provided and PICKLE is not defined

        """

        if path is None:

            try:

                path=vrlg.PICKLE

            except:

                raise Exception ("path is not provided and Verilog parameter PICKLE is not defined")

        self.adjustment_state=pickle.load(open(path, "rb" ))

        if quiet <2:

            print ("mcntrl state (self.adjustment_state) is loaded from %s"%(path))

            if quiet<1:

                print ("self.adjustment_state=",self.adjustment_state)

            

            
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