adding rigger out from the sensors running i free mode

8f05c2c2 · Andrey Filippov · ae33ff53 · 8f05c2c2 · 8f05c2c2 · 8f05c2c2
Commit 8f05c2c2 authored May 04, 2019 by Andrey Filippov
11 changed files
--- a/cocotb/x393_cocotb_lwir_04.sav
+++ b/cocotb/x393_cocotb_lwir_04.sav
 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Fri May  3 04:06:38 2019
+[*] Fri May  3 15:28:46 2019
 [*]
 [dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190502213839545.fst"
 [dumpfile_mtime] "Fri May  3 04:06:09 2019"
@@ -3061,16 +3061,44 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
 @28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_mclk
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_spi_seq_pclk
-@29
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_timeout_cntr[1:0]
-@28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_seq
-@200
-
 @1000200
 -reset_seq
 @800200
 -sens_channel0
+-timestamping
+@22
+x393_dut.x393_i.timing393_i.frame_sync[3:0]
+@28
+x393_dut.x393_i.timing393_i.frsync_chn0
+x393_dut.x393_i.timing393_i.frsync_chn1
+x393_dut.x393_i.timing393_i.frsync_chn2
+x393_dut.x393_i.timing393_i.frsync_chn3
+@22
+x393_dut.x393_i.timing393_i.trig[3:0]
+@28
+x393_dut.x393_i.timing393_i.trig_chn0
+x393_dut.x393_i.timing393_i.trig_chn1
+x393_dut.x393_i.timing393_i.trig_chn2
+x393_dut.x393_i.timing393_i.trig_chn3
+x393_dut.x393_i.timing393_i.triggered_mode
+@22
+x393_dut.x393_i.timing393_i.ts_data_chn0[7:0]
+x393_dut.x393_i.timing393_i.ts_data_chn1[7:0]
+x393_dut.x393_i.timing393_i.ts_data_chn2[7:0]
+x393_dut.x393_i.timing393_i.ts_data_chn3[7:0]
+x393_dut.x393_i.timing393_i.ts_stb[3:0]
+@28
+x393_dut.x393_i.timing393_i.ts_stb_chn0
+x393_dut.x393_i.timing393_i.ts_stb_chn1
+x393_dut.x393_i.timing393_i.ts_stb_chn2
+x393_dut.x393_i.timing393_i.ts_stb_chn3
+@201
+-
+@1000200
+-timestamping
+@800200
 -lepto3_0
 @28
 x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.prst

--- a/fpga_version.vh
+++ b/fpga_version.vh
@@ -35,7 +35,8 @@
 * contains all the components and scripts required to completely simulate it
 * with at least one of the Free Software programs.
 */
-        parameter FPGA_VERSION =          32'h03930136;      // Fiixing spi_seq 
+        parameter FPGA_VERSION =          32'h03930137;       // longer reset, sync output 
+//        parameter FPGA_VERSION =          32'h03930136;      // Fiixing spi_seq 
 //        parameter FPGA_VERSION =          32'h03930135;      // Adding multi-cam reset 
 //        parameter FPGA_VERSION =          32'h0393014;      // Adding multi-cam reset - buggy 
 //        parameter FPGA_VERSION =          32'h03930133;      // Works with linux kernel rocko commit of 05/01/2019 bd61276e05f7343415929112ae368230a9c472f0

--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -594,7 +594,7 @@
        parameter VOSPI_MRST_AFTER_MS =      5, // Wait after master reset and generate SOF pulse to advance sequencer  
        parameter VOSPI_SPI_TIMEOUT_MS =     3, // Wait to tymeout SPI when needed to re-sync
    `else
-        parameter VOSPI_MRST_MS =            5, // master reset duration in ms
+        parameter VOSPI_MRST_MS =          200, // master reset duration in ms (so even all channels would overlap)
        parameter VOSPI_MRST_AFTER_MS =   2000, // Wait after master reset and generate SOF pulse to advance sequencer  
        parameter VOSPI_SPI_TIMEOUT_MS =   185, // Wait to tymeout SPI when needed to re-sync
    `endif  

--- a/sensor/sens_lepton3.v
+++ b/sensor/sens_lepton3.v
@@ -89,7 +89,7 @@ module  sens_lepton3 #(
    parameter VOSPI_SOF_TO_HACT =    100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
    parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
    parameter VOSPI_MCLK_HALFDIV =     4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
-    parameter VOSPI_MRST_MS =          5, // master reset duration in ms
+    parameter VOSPI_MRST_MS =        200, // master reset duration in ms (so even all channels would overlap)
    parameter VOSPI_MRST_AFTER_MS = 2000,  // Wait after master reset and generate SOF pulse to advance sequencer  
    parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync
 )(

--- a/sensor/sensor_channel.v
+++ b/sensor/sensor_channel.v
@@ -276,7 +276,7 @@ module  sensor_channel#(
    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
    parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF
    parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 
-    parameter VOSPI_MRST_MS =            5, // master reset duration in ms
+    parameter VOSPI_MRST_MS =          200, // master reset duration in ms (so even all channels would overlap)
    parameter VOSPI_MRST_AFTER_MS =   2000,  // Wait after master reset and generate SOF pulse to advance sequencer  
    parameter VOSPI_SPI_TIMEOUT_MS =   185 // Wait to tymeout SPI when needed to re-sync
 `else
@@ -1061,7 +1061,7 @@ module  sensor_channel#(
            .VOSPI_SOF_TO_HACT      (VOSPI_SOF_TO_HACT), //      100,
            .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), //   2,
            .VOSPI_MCLK_HALFDIV     (VOSPI_MCLK_HALFDIV), //       4
-            .VOSPI_MRST_MS          (VOSPI_MRST_MS), //            5
+            .VOSPI_MRST_MS          (VOSPI_MRST_MS), //          200, // master reset duration in ms (so even all channels would overlap)
            .VOSPI_MRST_AFTER_MS    (VOSPI_MRST_AFTER_MS), //   2000
            .VOSPI_SPI_TIMEOUT_MS   (VOSPI_SPI_TIMEOUT_MS) //    185
    ) sens_lepton3_i (

--- a/sensor/sensors393.v
+++ b/sensor/sensors393.v
@@ -272,7 +272,7 @@ module  sensors393 #(
    parameter VOSPI_SOF_TO_HACT =      100, //  10,  // clock cycles from SOF to HACT (limited to 8 bits)
    parameter VOSPI_HACT_TO_HACT_EOF =   2,  // minimal clock cycles from HACT to HACT or to EOF
    parameter VOSPI_MCLK_HALFDIV =       4,  // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock 
-    parameter VOSPI_MRST_MS =            5, // master reset duration in ms
+    parameter VOSPI_MRST_MS =          200, // master reset duration in ms (so even all channels would overlap)
    parameter VOSPI_MRST_AFTER_MS =   2000,  // Wait after master reset and generate SOF pulse to advance sequencer
    parameter VOSPI_SPI_TIMEOUT_MS =   185, // Wait to tymeout SPI when needed to re-sync
 `else
@@ -764,7 +764,7 @@ module  sensors393 #(
                .VOSPI_SOF_TO_HACT             (VOSPI_SOF_TO_HACT), //      100,
                .VOSPI_HACT_TO_HACT_EOF        (VOSPI_HACT_TO_HACT_EOF), //   2,
                .VOSPI_MCLK_HALFDIV            (VOSPI_MCLK_HALFDIV), //       4
-                .VOSPI_MRST_MS                 (VOSPI_MRST_MS), //            5
+                .VOSPI_MRST_MS                 (VOSPI_MRST_MS), //          200, // master reset duration in ms (so even all channels would overlap)
                .VOSPI_MRST_AFTER_MS           (VOSPI_MRST_AFTER_MS), //   2000
                .VOSPI_SPI_TIMEOUT_MS          (VOSPI_SPI_TIMEOUT_MS) //    185
 `else

--- a/timing/camsync393.v
+++ b/timing/camsync393.v
--- a/x393.v
+++ b/x393.v
@@ -1883,7 +1883,7 @@ assign axi_grst = axi_rst_pre;
        .VOSPI_SOF_TO_HACT          (VOSPI_SOF_TO_HACT), //      100,
        .VOSPI_HACT_TO_HACT_EOF     (VOSPI_HACT_TO_HACT_EOF), //   2,
        .VOSPI_MCLK_HALFDIV         (VOSPI_MCLK_HALFDIV), //       4
-        .VOSPI_MRST_MS              (VOSPI_MRST_MS), //            5
+        .VOSPI_MRST_MS              (VOSPI_MRST_MS), //          200, // master reset duration in ms (so even all channels would overlap)
        .VOSPI_MRST_AFTER_MS        (VOSPI_MRST_AFTER_MS), //    2000
        .VOSPI_SPI_TIMEOUT_MS       (VOSPI_SPI_TIMEOUT_MS), //    185

--- a/x393_vospi.bit
+++ b/x393_vospi.bit
--- a/x393_vospi.timing_summary_impl
+++ b/x393_vospi.timing_summary_impl
--- a/x393_vospi_utilization.report
+++ b/x393_vospi_utilization.report
 Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
-| Date         : Thu May  2 22:27:59 2019
+| Date         : Fri May  3 14:00:41 2019
 | Host         : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
 | Command      : report_utilization -file vivado_build/x393_vospi_utilization.report
 | Design       : x393
@@ -31,13 +31,13 @@ Table of Contents
 +----------------------------+-------+-------+-----------+-------+
 |          Site Type         |  Used | Fixed | Available | Util% |
 +----------------------------+-------+-------+-----------+-------+
-| Slice LUTs                 | 42274 |     0 |     78600 | 53.78 |
+| Slice LUTs                 | 42462 |     0 |     78600 | 54.02 |
-|   LUT as Logic             | 38918 |     0 |     78600 | 49.51 |
+|   LUT as Logic             | 39108 |     0 |     78600 | 49.76 |
-|   LUT as Memory            |  3356 |     0 |     26600 | 12.62 |
+|   LUT as Memory            |  3354 |     0 |     26600 | 12.61 |
 |     LUT as Distributed RAM |  2802 |     0 |           |       |
-|     LUT as Shift Register  |   554 |     0 |           |       |
+|     LUT as Shift Register  |   552 |     0 |           |       |
-| Slice Registers            | 54220 |     0 |    157200 | 34.49 |
+| Slice Registers            | 54238 |     0 |    157200 | 34.50 |
-|   Register as Flip Flop    | 54220 |     0 |    157200 | 34.49 |
+|   Register as Flip Flop    | 54238 |     0 |    157200 | 34.50 |
 |   Register as Latch        |     0 |     0 |    157200 |  0.00 |
 | F7 Muxes                   |    34 |     0 |     39300 |  0.09 |
 | F8 Muxes                   |     0 |     0 |     19650 |  0.00 |
@@ -58,8 +58,8 @@ Table of Contents
 | 0     |          Yes |           - |            - |
 | 8     |          Yes |           - |          Set |
 | 680   |          Yes |           - |        Reset |
-| 1084  |          Yes |         Set |            - |
+| 1108  |          Yes |         Set |            - |
-| 52448 |          Yes |       Reset |            - |
+| 52442 |          Yes |       Reset |            - |
 +-------+--------------+-------------+--------------+
@@ -69,27 +69,27 @@ Table of Contents
 +-------------------------------------------+-------+-------+-----------+-------+
 |                 Site Type                 |  Used | Fixed | Available | Util% |
 +-------------------------------------------+-------+-------+-----------+-------+
-| Slice                                     | 16898 |     0 |     19650 | 85.99 |
+| Slice                                     | 16910 |     0 |     19650 | 86.06 |
-|   SLICEL                                  | 11122 |     0 |           |       |
+|   SLICEL                                  | 11158 |     0 |           |       |
-|   SLICEM                                  |  5776 |     0 |           |       |
+|   SLICEM                                  |  5752 |     0 |           |       |
-| LUT as Logic                              | 38918 |     0 |     78600 | 49.51 |
+| LUT as Logic                              | 39108 |     0 |     78600 | 49.76 |
-|   using O5 output only                    |     1 |       |           |       |
+|   using O5 output only                    |     6 |       |           |       |
-|   using O6 output only                    | 30285 |       |           |       |
+|   using O6 output only                    | 30466 |       |           |       |
-|   using O5 and O6                         |  8632 |       |           |       |
+|   using O5 and O6                         |  8636 |       |           |       |
-| LUT as Memory                             |  3356 |     0 |     26600 | 12.62 |
+| LUT as Memory                             |  3354 |     0 |     26600 | 12.61 |
 |   LUT as Distributed RAM                  |  2802 |     0 |           |       |
 |     using O5 output only                  |     2 |       |           |       |
 |     using O6 output only                  |    84 |       |           |       |
 |     using O5 and O6                       |  2716 |       |           |       |
-|   LUT as Shift Register                   |   554 |     0 |           |       |
+|   LUT as Shift Register                   |   552 |     0 |           |       |
-|     using O5 output only                  |   285 |       |           |       |
+|     using O5 output only                  |   272 |       |           |       |
-|     using O6 output only                  |   219 |       |           |       |
+|     using O6 output only                  |   228 |       |           |       |
-|     using O5 and O6                       |    50 |       |           |       |
+|     using O5 and O6                       |    52 |       |           |       |
-| LUT Flip Flop Pairs                       | 24502 |     0 |     78600 | 31.17 |
+| LUT Flip Flop Pairs                       | 24526 |     0 |     78600 | 31.20 |
-|   fully used LUT-FF pairs                 |  4550 |       |           |       |
+|   fully used LUT-FF pairs                 |  4532 |       |           |       |
-|   LUT-FF pairs with one unused LUT output | 17779 |       |           |       |
+|   LUT-FF pairs with one unused LUT output | 17794 |       |           |       |
-|   LUT-FF pairs with one unused Flip Flop  | 17787 |       |           |       |
+|   LUT-FF pairs with one unused Flip Flop  | 17697 |       |           |       |
-| Unique Control Sets                       |  4739 |       |           |       |
+| Unique Control Sets                       |  4907 |       |           |       |
 +-------------------------------------------+-------+-------+-----------+-------+
 * Note: Review the Control Sets Report for more information regarding control sets.
@@ -196,17 +196,17 @@ Table of Contents
 +------------------------+-------+----------------------+
 |        Ref Name        |  Used |  Functional Category |
 +------------------------+-------+----------------------+
-| FDRE                   | 52448 |         Flop & Latch |
+| FDRE                   | 52442 |         Flop & Latch |
-| LUT3                   | 11328 |                  LUT |
+| LUT3                   | 11375 |                  LUT |
-| LUT6                   | 10336 |                  LUT |
+| LUT6                   | 10433 |                  LUT |
-| LUT2                   |  8397 |                  LUT |
+| LUT2                   |  8421 |                  LUT |
-| LUT4                   |  7992 |                  LUT |
+| LUT4                   |  8002 |                  LUT |
-| LUT5                   |  7901 |                  LUT |
+| LUT5                   |  7906 |                  LUT |
 | RAMD32                 |  4126 |   Distributed Memory |
 | CARRY4                 |  2733 |           CarryLogic |
-| LUT1                   |  1596 |                  LUT |
+| LUT1                   |  1607 |                  LUT |
 | RAMS32                 |  1392 |   Distributed Memory |
-| FDSE                   |  1084 |         Flop & Latch |
+| FDSE                   |  1108 |         Flop & Latch |
 | FDCE                   |   680 |         Flop & Latch |
 | SRL16E                 |   496 |   Distributed Memory |
 | SRLC32E                |   108 |   Distributed Memory |