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x393
Commit 88808cb3 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
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from /tmp back to / - because overlayfs

parent 4e2a8fce
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Showing with 5 additions and 4 deletions
py393/imgsrv.py
View file @ 88808cb3
...@@ -39,7 +39,8 @@ import shutil ...@@ -39,7 +39,8 @@ import shutil
import sys import sys
import subprocess import subprocess
path="/tmp/img.jpeg" path="/www/pages/img.jpeg"
#path="/tmp/img.jpeg"
PORT=8888 PORT=8888
def communicate(port,snd_str): def communicate(port,snd_str):
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM) sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
...@@ -67,7 +68,7 @@ acquisition_parameters={ ...@@ -67,7 +68,7 @@ acquisition_parameters={
"black": None, "black": None,
"colorsat_blue":None, "colorsat_blue":None,
"colorsat_red": None, "colorsat_red": None,
"server_root": "/tmp/", "server_root": "/www/pages/",
"gain_r": None, "gain_r": None,
"gain_gr": None, "gain_gr": None,
"gain_gb": None, "gain_gb": None,
......
py393/x393_utils.py
View file @ 88808cb3
...@@ -39,8 +39,8 @@ from time import sleep ...@@ -39,8 +39,8 @@ from time import sleep
import vrlg # global parameters import vrlg # global parameters
import x393_axi_control_status import x393_axi_control_status
import shutil import shutil
#DEFAULT_BITFILE="/usr/local/verilog/x393.bit" DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
DEFAULT_BITFILE="/tmp/x393.bit" #DEFAULT_BITFILE="/tmp/x393.bit"
FPGA_RST_CTRL = 0xf8000240 FPGA_RST_CTRL = 0xf8000240
FPGA0_THR_CTRL = 0xf8000178 FPGA0_THR_CTRL = 0xf8000178
FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all FPGA_LVL_SHFTR = 0xf8000900 # 0xf: all enabled, 0x0 - disable all
......
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