Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
88808cb3
Commit
88808cb3
authored
Jul 20, 2016
by
Oleg Dzhimiev
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
from /tmp back to / - because overlayfs
parent
4e2a8fce
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
5 additions
and
4 deletions
+5
-4
imgsrv.py
py393/imgsrv.py
+3
-2
x393_utils.py
py393/x393_utils.py
+2
-2
No files found.
py393/imgsrv.py
View file @
88808cb3
...
...
@@ -39,7 +39,8 @@ import shutil
import
sys
import
subprocess
path
=
"/tmp/img.jpeg"
path
=
"/www/pages/img.jpeg"
#path="/tmp/img.jpeg"
PORT
=
8888
def
communicate
(
port
,
snd_str
):
sock
=
socket
.
socket
(
socket
.
AF_INET
,
socket
.
SOCK_STREAM
)
...
...
@@ -67,7 +68,7 @@ acquisition_parameters={
"black"
:
None
,
"colorsat_blue"
:
None
,
"colorsat_red"
:
None
,
"server_root"
:
"/
tmp
/"
,
"server_root"
:
"/
www/pages
/"
,
"gain_r"
:
None
,
"gain_gr"
:
None
,
"gain_gb"
:
None
,
...
...
py393/x393_utils.py
View file @
88808cb3
...
...
@@ -39,8 +39,8 @@ from time import sleep
import
vrlg
# global parameters
import
x393_axi_control_status
import
shutil
#
DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
DEFAULT_BITFILE
=
"/tmp/x393.bit"
DEFAULT_BITFILE
=
"/usr/local/verilog/x393.bit"
#
DEFAULT_BITFILE="/tmp/x393.bit"
FPGA_RST_CTRL
=
0xf8000240
FPGA0_THR_CTRL
=
0xf8000178
FPGA_LVL_SHFTR
=
0xf8000900
# 0xf: all enabled, 0x0 - disable all
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment