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Commit 8314065a authored by Andrey Filippov's avatar Andrey Filippov
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generated bitstream for parallel interface sensors

parent 538d91a0
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Showing with 4 additions and 3 deletions
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 8314065a
...@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true ...@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_hispi VivadoBitstream_124_rawfile=x393_parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@-> com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
fpga_version.vh
View file @ 8314065a
...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
// parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
// parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works // parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works
// parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT) // parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT)
// parameter FPGA_VERSION = 32'h03930095; // parallel -0.068/-0.342/5 82.38% // parameter FPGA_VERSION = 32'h03930095; // parallel -0.068/-0.342/5 82.38%
......
system_defines.vh
View file @ 8314065a
...@@ -59,7 +59,7 @@ ...@@ -59,7 +59,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/ // `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
......
x393_parallel.bit
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