Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
8314065a
Commit
8314065a
authored
Jun 18, 2016
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
generated bitstream for parallel interface sensors
parent
538d91a0
Changes
4
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
4 additions
and
3 deletions
+4
-3
com.elphel.vdt.VivadoBitstream.prefs
.settings/com.elphel.vdt.VivadoBitstream.prefs
+1
-1
fpga_version.vh
fpga_version.vh
+2
-1
system_defines.vh
system_defines.vh
+1
-1
x393_parallel.bit
x393_parallel.bit
+0
-0
No files found.
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @
8314065a
...
...
@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_
hispi
VivadoBitstream_124_rawfile=x393_
parallel
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1
fpga_version.vh
View file @
8314065a
...
...
@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely
parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
// parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
// parameter FPGA_VERSION = 32'h03930097; // serial, trying dct_chen - works
// parameter FPGA_VERSION = 32'h03930096; // serial, next (before changing DCT)
// parameter FPGA_VERSION = 32'h03930095; // parallel -0.068/-0.342/5 82.38%
...
...
system_defines.vh
View file @
8314065a
...
...
@@ -59,7 +59,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
//
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
...
...
x393_parallel.bit
View file @
8314065a
No preview for this file type
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment