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Commit 77c76c3b authored by Andrey Filippov's avatar Andrey Filippov
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hardware debugging/bug fixing

parent 72068ae7
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.project
View file @ 77c76c3b
...@@ -62,42 +62,42 @@ ...@@ -62,42 +62,42 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150826175759893.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
...@@ -107,32 +107,32 @@ ...@@ -107,32 +107,32 @@
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150826180314606.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150826175759893.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150831151630695.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150826180314606.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-place.dcp</name> <name>vivado_state/x393-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150826180314606.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150826180314606.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150826175759893.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
fpga_version.vh
View file @ 77c76c3b
parameter FPGA_VERSION = 32'h03930001; parameter FPGA_VERSION = 32'h03930003;
py393/dbg/x393_mcntrl.pickle
View file @ 77c76c3b
This diff is collapsed.
py393/x393_axi_control_status.py
View file @ 77c76c3b
...@@ -124,7 +124,7 @@ class X393AxiControlStatus(object): ...@@ -124,7 +124,7 @@ class X393AxiControlStatus(object):
return refresh_en return refresh_en
def get_enabled_channels(self,quiet=1): def get_enabled_channels(self,quiet=1):
# global enabled_channels # global enabled_channels
enabled_channels = self.read_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN) enabled_channels = self.read_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
if quiet<2 : if quiet<2 :
print ("ENABLED_CHANNELS = 0x%x"%enabled_channels) print ("ENABLED_CHANNELS = 0x%x"%enabled_channels)
return enabled_channels return enabled_channels
...@@ -135,7 +135,7 @@ class X393AxiControlStatus(object): ...@@ -135,7 +135,7 @@ class X393AxiControlStatus(object):
if quiet<2 : if quiet<2 :
print ("CHANNEL PRIORITIES:",end=" ") print ("CHANNEL PRIORITIES:",end=" ")
for chn in range (16): for chn in range (16):
v = self.read_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn) v = self.read_control_register(vrlg.MCONTR_ARBIT_ADDR + chn)
print ("%d"%v,end=" ") print ("%d"%v,end=" ")
channel_priority.append(v) channel_priority.append(v)
""" """
...@@ -160,7 +160,7 @@ class X393AxiControlStatus(object): ...@@ -160,7 +160,7 @@ class X393AxiControlStatus(object):
'sequences_set': self.get_sequences_set(quiet) 'sequences_set': self.get_sequences_set(quiet)
} }
def write_contol_register(self, reg_addr, data): def write_control_register(self, reg_addr, data):
""" """
Write 32-bit word to the control register Write 32-bit word to the control register
@param addr - register address relative to the control register address space @param addr - register address relative to the control register address space
...@@ -168,7 +168,7 @@ class X393AxiControlStatus(object): ...@@ -168,7 +168,7 @@ class X393AxiControlStatus(object):
""" """
self.x393_mem.axi_write_single_w(vrlg.CONTROL_ADDR+reg_addr, data) self.x393_mem.axi_write_single_w(vrlg.CONTROL_ADDR+reg_addr, data)
def read_contol_register(self, reg_addr=None, quiet=1): def read_control_register(self, reg_addr=None, quiet=1):
""" """
Read 32-bit word from the control register (written by the software or the command sequencer) Read 32-bit word from the control register (written by the software or the command sequencer)
@param addr - register address relative to the control register address space @param addr - register address relative to the control register address space
...@@ -240,7 +240,7 @@ class X393AxiControlStatus(object): ...@@ -240,7 +240,7 @@ class X393AxiControlStatus(object):
data=self.read_status(status_address) data=self.read_status(status_address)
if wait_seq: if wait_seq:
seq_num = ((data >> vrlg.STATUS_SEQ_SHFT) ^ 0x20) & 0x30 seq_num = ((data >> vrlg.STATUS_SEQ_SHFT) ^ 0x20) & 0x30
self.write_contol_register(status_control_address, ((status_mode & 3) <<6) | (seq_num & 0x3f)) self.write_control_register(status_control_address, ((status_mode & 3) <<6) | (seq_num & 0x3f))
data=self.read_status(status_address) data=self.read_status(status_address)
while (((data >> vrlg.STATUS_SEQ_SHFT) ^ seq_num) & 0x30) !=0: while (((data >> vrlg.STATUS_SEQ_SHFT) ^ seq_num) & 0x30) !=0:
data=self.read_status(status_address) data=self.read_status(status_address)
...@@ -281,7 +281,14 @@ class X393AxiControlStatus(object): ...@@ -281,7 +281,14 @@ class X393AxiControlStatus(object):
print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8))) print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8)))
print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8))) print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))
print ("MEMBRIDGE_STATUS_REG: %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8))) print ("MEMBRIDGE_STATUS_REG: %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8)))
items_per_line = 8
for i in range (256):
if not i % items_per_line:
print ("\n0x%02x: "%(i), end = "")
d=hx(self.read_status(i),8)
print ("%s "%(d), end = "")
print ()
def program_status(self, def program_status(self,
base_addr, # input [29:0] base_addr; base_addr, # input [29:0] base_addr;
reg_addr, # input [7:0] reg_addr; reg_addr, # input [7:0] reg_addr;
...@@ -298,7 +305,7 @@ class X393AxiControlStatus(object): ...@@ -298,7 +305,7 @@ class X393AxiControlStatus(object):
4: auto, inc sequence number 4: auto, inc sequence number
<seq_number> - 6-bit sequence number of the status message to be sent <seq_number> - 6-bit sequence number of the status message to be sent
""" """
self.write_contol_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f)) self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f))
def program_status_all( self, def program_status_all( self,
...@@ -337,7 +344,7 @@ class X393AxiControlStatus(object): ...@@ -337,7 +344,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en] en=(0,1)[en]
if self.verbose>0: if self.verbose>0:
print ("ENABLE CMDA %s"%str(en)) print ("ENABLE CMDA %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0); self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0);
cmda_en=en cmda_en=en
def enable_cke(self, def enable_cke(self,
...@@ -350,7 +357,7 @@ class X393AxiControlStatus(object): ...@@ -350,7 +357,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en] en=(0,1)[en]
if self.verbose>0: if self.verbose>0:
print ("ENABLE CKE %s"%str(en)) print ("ENABLE CKE %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0); self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0);
cke_en=en cke_en=en
def activate_sdrst(self, def activate_sdrst(self,
...@@ -363,7 +370,7 @@ class X393AxiControlStatus(object): ...@@ -363,7 +370,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en] en=(0,1)[en]
if self.verbose>0: if self.verbose>0:
print ("ACTIVATE SDRST %s"%str(en)) print ("ACTIVATE SDRST %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0); self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
sdrst_on=en sdrst_on=en
def enable_refresh(self, def enable_refresh(self,
...@@ -376,7 +383,7 @@ class X393AxiControlStatus(object): ...@@ -376,7 +383,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en] en=(0,1)[en]
if self.verbose>0: if self.verbose>0:
print ("ENABLE REFRESH %s"%str(en)) print ("ENABLE REFRESH %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0); self.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
refresh_en=en refresh_en=en
def enable_memcntrl(self, def enable_memcntrl(self,
...@@ -389,7 +396,7 @@ class X393AxiControlStatus(object): ...@@ -389,7 +396,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en] en=(0,1)[en]
if self.verbose > 0: if self.verbose > 0:
print ("ENABLE MEMCTRL %s"%str(en)) print ("ENABLE MEMCTRL %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0); self.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
mcntrl_en=en mcntrl_en=en
def enable_memcntrl_channels(self, def enable_memcntrl_channels(self,
chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable; chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable;
...@@ -399,7 +406,7 @@ class X393AxiControlStatus(object): ...@@ -399,7 +406,7 @@ class X393AxiControlStatus(object):
""" """
# global enabled_channels # global enabled_channels
enabled_channels = chnen # currently enabled memory channels enabled_channels = chnen # currently enabled memory channels
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen}); self.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
if self.verbose > 0: if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen)) print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))
...@@ -413,12 +420,12 @@ class X393AxiControlStatus(object): ...@@ -413,12 +420,12 @@ class X393AxiControlStatus(object):
""" """
# global enabled_channels # global enabled_channels
# Adding readback register # Adding readback register
enabled_channels = self.read_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN) enabled_channels = self.read_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
if en: if en:
enabled_channels |= 1<<chn; enabled_channels |= 1<<chn;
else: else:
enabled_channels &= ~(1<<chn); enabled_channels &= ~(1<<chn);
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS}); self.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose > 0: if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels) print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)
...@@ -431,7 +438,7 @@ class X393AxiControlStatus(object): ...@@ -431,7 +438,7 @@ class X393AxiControlStatus(object):
<priority> - 16-bit priority value (higher value means more important) <priority> - 16-bit priority value (higher value means more important)
""" """
# global channel_priority # global channel_priority
self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority}); self.write_control_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
if self.verbose > 0: if self.verbose > 0:
print ("SET CHANNEL %d priority=0x%x"%(chn,priority)) print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
# channel_priority[chn]=priority # channel_priority[chn]=priority
......
py393/x393_camsync.py
View file @ 77c76c3b
...@@ -93,7 +93,7 @@ class X393Camsync(object): ...@@ -93,7 +93,7 @@ class X393Camsync(object):
data |= (4 | (master_chn & 3)) << (vrlg.CAMSYNC_MASTER_BIT - 2) data |= (4 | (master_chn & 3)) << (vrlg.CAMSYNC_MASTER_BIT - 2)
if not chn_en is None: if not chn_en is None:
data |= (0x10 | (chn_en & 0xf)) << (vrlg.CAMSYNC_CHN_EN_BIT - 4) data |= (0x10 | (chn_en & 0xf)) << (vrlg.CAMSYNC_CHN_EN_BIT - 4)
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_MODE, data); self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_MODE, data);
def set_camsync_inout(self, def set_camsync_inout(self,
is_out, is_out,
...@@ -111,7 +111,7 @@ class X393Camsync(object): ...@@ -111,7 +111,7 @@ class X393Camsync(object):
db=(2,3)[active_positive] db=(2,3)[active_positive]
data &= ~(3 << (2 * bit_number)) data &= ~(3 << (2 * bit_number))
data |= (db << (2 * bit_number)) data |= (db << (2 * bit_number))
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR +
(vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], data) (vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], data)
def reset_camsync_inout(self, def reset_camsync_inout(self,
...@@ -120,7 +120,7 @@ class X393Camsync(object): ...@@ -120,7 +120,7 @@ class X393Camsync(object):
Reset camsync inputs or outputs to inactive/don't care state Reset camsync inputs or outputs to inactive/don't care state
@param is_out - True for outputs, False for inputs @param is_out - True for outputs, False for inputs
""" """
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR +
(vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], 0) (vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], 0)
def set_camsync_period(self, def set_camsync_period(self,
...@@ -129,7 +129,7 @@ class X393Camsync(object): ...@@ -129,7 +129,7 @@ class X393Camsync(object):
Set camsync period Set camsync period
@param period - period value in 10 ns steps - max 42.95 sec @param period - period value in 10 ns steps - max 42.95 sec
""" """
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, period) self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, period)
def set_camsync_delay(self, def set_camsync_delay(self,
sub_chn, sub_chn,
...@@ -139,7 +139,7 @@ class X393Camsync(object): ...@@ -139,7 +139,7 @@ class X393Camsync(object):
@param sub_chn - sensor channel (0..3) @param sub_chn - sensor channel (0..3)
@param delay - delay value in 10 ns steps - max 42.95 sec @param delay - delay value in 10 ns steps - max 42.95 sec
""" """
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, delay) self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, delay)
def camsync_setup(self, def camsync_setup(self,
sensor_mask = None, sensor_mask = None,
......
py393/x393_cmprs.py
View file @ 77c76c3b
...@@ -182,7 +182,7 @@ class X393Cmprs(object): ...@@ -182,7 +182,7 @@ class X393Cmprs(object):
data = self.func_compressor_format (num_macro_cols_m1 = num_macro_cols_m1, data = self.func_compressor_format (num_macro_cols_m1 = num_macro_cols_m1,
num_macro_rows_m1 = num_macro_rows_m1, num_macro_rows_m1 = num_macro_rows_m1,
left_margin = left_margin) left_margin = left_margin)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_FORMAT, self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_FORMAT,
data) data)
def compressor_color_saturation (self, def compressor_color_saturation (self,
...@@ -196,7 +196,7 @@ class X393Cmprs(object): ...@@ -196,7 +196,7 @@ class X393Cmprs(object):
""" """
data = self.func_compressor_color_saturation (colorsat_blue = colorsat_blue, data = self.func_compressor_color_saturation (colorsat_blue = colorsat_blue,
colorsat_red = colorsat_red) colorsat_red = colorsat_red)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_COLOR_SATURATION, self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_COLOR_SATURATION,
data) data)
def compressor_coring (self, def compressor_coring (self,
...@@ -207,7 +207,7 @@ class X393Cmprs(object): ...@@ -207,7 +207,7 @@ class X393Cmprs(object):
@param coring - coring value @param coring - coring value
""" """
data = coring & ((1 << vrlg.CMPRS_CORING_BITS) - 1) data = coring & ((1 << vrlg.CMPRS_CORING_BITS) - 1)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CORING_MODE, self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CORING_MODE,
data) data)
def compressor_control (self, def compressor_control (self,
...@@ -251,7 +251,7 @@ class X393Cmprs(object): ...@@ -251,7 +251,7 @@ class X393Cmprs(object):
multi_frame = multi_frame, multi_frame = multi_frame,
bayer = bayer, bayer = bayer,
focus_mode = focus_mode) focus_mode = focus_mode)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG, self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG,
data) data)
def setup_compressor_memory (self, def setup_compressor_memory (self,
num_sensor, num_sensor,
...@@ -297,31 +297,31 @@ class X393Cmprs(object): ...@@ -297,31 +297,31 @@ class X393Cmprs(object):
write_mem = False, write_mem = False,
enable = True, enable = True,
chn_reset = False) chn_reset = False)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_STARTADDR, base_addr + vrlg.MCNTRL_TILED_STARTADDR,
frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE, base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE,
frame_sa_inc) frame_sa_inc)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_LAST, base_addr + vrlg.MCNTRL_TILED_FRAME_LAST,
last_frame_num) last_frame_num)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH, base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
frame_full_width) frame_full_width)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_WH, base_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16)); ((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0, base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16)); ((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY, base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
0) 0)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_TILE_WHS, base_addr + vrlg.MCNTRL_TILED_TILE_WHS,
((tile_vstep & 0xff) <<16) | ((tile_height & 0xff) <<8) | (tile_width & 0xff)) #//(tile_height<<8)+(tile_vstep<<16)); ((tile_vstep & 0xff) <<16) | ((tile_height & 0xff) <<8) | (tile_width & 0xff)) #//(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_MODE, base_addr + vrlg.MCNTRL_TILED_MODE,
mode); mode);
def compressor_run(self, # may use compressor_control with the same arguments def compressor_run(self, # may use compressor_control with the same arguments
......
py393/x393_cmprs_afi.py
View file @ 77c76c3b
...@@ -91,7 +91,7 @@ class X393CmprsAfi(object): ...@@ -91,7 +91,7 @@ class X393CmprsAfi(object):
@param port_afi - number of AFI port (0 - afi 1, 1 - afi2) @param port_afi - number of AFI port (0 - afi 1, 1 - afi2)
@param rst_chn - bit mask of channels to reset (persistent, needs release) @param rst_chn - bit mask of channels to reset (persistent, needs release)
""" """
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_RST, vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_RST,
rst_chn) rst_chn)
def afi_mux_enable_chn (self, def afi_mux_enable_chn (self,
...@@ -104,7 +104,7 @@ class X393CmprsAfi(object): ...@@ -104,7 +104,7 @@ class X393CmprsAfi(object):
@param en_chn - number of afi input channel to enable/disable (0..3) @param en_chn - number of afi input channel to enable/disable (0..3)
@param en - number enable (True) or disable (False) selected AFI input @param en - number enable (True) or disable (False) selected AFI input
""" """
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN, vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN,
(2,3)[en] << (2 * en_chn)) (2,3)[en] << (2 * en_chn))
...@@ -117,7 +117,7 @@ class X393CmprsAfi(object): ...@@ -117,7 +117,7 @@ class X393CmprsAfi(object):
@param en_chn - number of afi input channel to enable/disable (0..3) @param en_chn - number of afi input channel to enable/disable (0..3)
@param en - number enable (True) or disable (False) selected AFI input @param en - number enable (True) or disable (False) selected AFI input
""" """
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN, vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN,
(2,3)[en] << (2 * 4)) (2,3)[en] << (2 * 4))
...@@ -135,7 +135,7 @@ class X393CmprsAfi(object): ...@@ -135,7 +135,7 @@ class X393CmprsAfi(object):
mode == 2 - show current pointer, internal mode == 2 - show current pointer, internal
mode == 3 - show current pointer, confirmed written to the system memory mode == 3 - show current pointer, confirmed written to the system memory
""" """
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_MODE, vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_MODE,
(4 + (mode & 3)) << (4 * chn)) (4 + (mode & 3)) << (4 * chn))
...@@ -152,10 +152,10 @@ class X393CmprsAfi(object): ...@@ -152,10 +152,10 @@ class X393CmprsAfi(object):
@param length - channel buffer length in 32-byte chunks @param length - channel buffer length in 32-byte chunks
""" """
reg_addr = vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_SA_LEN + chn reg_addr = vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_SA_LEN + chn
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
reg_addr, reg_addr,
sa) sa)
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
reg_addr + 4, reg_addr + 4,
length) length)
......
py393/x393_frame_sequencer.py
View file @ 77c76c3b
...@@ -77,7 +77,7 @@ class X393FrameSequencer(object): ...@@ -77,7 +77,7 @@ class X393FrameSequencer(object):
data |= 1 << (vrlg.CMDFRAMESEQ_RUN_BIT -1) data |= 1 << (vrlg.CMDFRAMESEQ_RUN_BIT -1)
if start or stop: if start or stop:
data |= 1 << vrlg.CMDFRAMESEQ_RUN_BIT data |= 1 << vrlg.CMDFRAMESEQ_RUN_BIT
self.x393_axi_tasks.write_contol_register( self.x393_axi_tasks.write_control_register(
vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + vrlg.CMDFRAMESEQ_CTRL, vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + vrlg.CMDFRAMESEQ_CTRL,
data) data)
...@@ -100,6 +100,6 @@ class X393FrameSequencer(object): ...@@ -100,6 +100,6 @@ class X393FrameSequencer(object):
if relative and (frame_addr == 0xf): if relative and (frame_addr == 0xf):
raise Exception ("task write_cmd_frame_sequencer(): relative address 0xf is invalid, it is reserved for module control") raise Exception ("task write_cmd_frame_sequencer(): relative address 0xf is invalid, it is reserved for module control")
reg_addr = vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + (vrlg.CMDFRAMESEQ_ABS,vrlg.CMDFRAMESEQ_REL)[relative] + frame_addr reg_addr = vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + (vrlg.CMDFRAMESEQ_ABS,vrlg.CMDFRAMESEQ_REL)[relative] + frame_addr
self.x393_axi_tasks.write_contol_register( reg_addr, addr) # two writes to the same location - first is the register address self.x393_axi_tasks.write_control_register( reg_addr, addr) # two writes to the same location - first is the register address
self.x393_axi_tasks.write_contol_register( reg_addr, data) # second is data to write to that register self.x393_axi_tasks.write_control_register( reg_addr, data) # second is data to write to that register
py393/x393_gpio.py
View file @ 77c76c3b
...@@ -37,7 +37,7 @@ import x393_axi_control_status ...@@ -37,7 +37,7 @@ import x393_axi_control_status
import x393_utils import x393_utils
#import time import time
import vrlg import vrlg
class X393GPIO(object): class X393GPIO(object):
DRY_MODE= True # True DRY_MODE= True # True
...@@ -95,7 +95,7 @@ class X393GPIO(object): ...@@ -95,7 +95,7 @@ class X393GPIO(object):
data |= (2,3)[port_a] << 4 data |= (2,3)[port_a] << 4
if not port_c is None: if not port_c is None:
data |= (2,3)[port_a] << 6 data |= (2,3)[port_a] << 6
self.x393_axi_tasks.write_contol_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN) self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN)
def set_gpio_pins(self, def set_gpio_pins(self,
ext0 = None, ext0 = None,
...@@ -133,5 +133,5 @@ class X393GPIO(object): ...@@ -133,5 +133,5 @@ class X393GPIO(object):
data |= 3 << (2*i) data |= 3 << (2*i)
else: else:
raise Exception ("Expecting one of 'L', 'H', 'I', got "+str(e)+" for ext"+str(i)) raise Exception ("Expecting one of 'L', 'H', 'I', got "+str(e)+" for ext"+str(i))
self.x393_axi_tasks.write_contol_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data) self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data)
py393/x393_mcntrl_membridge.py
View file @ 77c76c3b
...@@ -36,7 +36,7 @@ import x393_axi_control_status ...@@ -36,7 +36,7 @@ import x393_axi_control_status
import x393_pio_sequences import x393_pio_sequences
import x393_mcntrl_timing import x393_mcntrl_timing
import x393_mcntrl_buffers import x393_mcntrl_buffers
import verilog_utils #import verilog_utils
import x393_mcntrl import x393_mcntrl
MEM_PATH='/sys/devices/elphel393-mem.2/' MEM_PATH='/sys/devices/elphel393-mem.2/'
BUFFER_ASSRESS_NAME='buffer_address' BUFFER_ASSRESS_NAME='buffer_address'
...@@ -118,7 +118,7 @@ class X393McntrlMembridge(object): ...@@ -118,7 +118,7 @@ class X393McntrlMembridge(object):
with open(MEM_PATH+BUFFER_PAGES_NAME) as sysfile: with open(MEM_PATH+BUFFER_PAGES_NAME) as sysfile:
BUFFER_LEN=PAGE_SIZE*int(sysfile.read(),0) BUFFER_LEN=PAGE_SIZE*int(sysfile.read(),0)
except: except:
print("Failed to get resderved physical memory range") print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS=',BUFFER_ADDRESS) print('BUFFER_ADDRESS=',BUFFER_ADDRESS)
print('BUFFER_LEN=',BUFFER_LEN) print('BUFFER_LEN=',BUFFER_LEN)
return return
...@@ -206,12 +206,12 @@ class X393McntrlMembridge(object): ...@@ -206,12 +206,12 @@ class X393McntrlMembridge(object):
if quiet <2: if quiet <2:
print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet)) print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64, len64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64, len64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache);
def membridge_start(self, def membridge_start(self,
cont=False, cont=False,
...@@ -221,8 +221,8 @@ class X393McntrlMembridge(object): ...@@ -221,8 +221,8 @@ class X393McntrlMembridge(object):
@param cont - continue with the current system memory pointer, False - start with lo_addr64+start64 @param cont - continue with the current system memory pointer, False - start with lo_addr64+start64
@quiet reduce output (>=1 - silent) @quiet reduce output (>=1 - silent)
''' '''
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0x3,0x7)[cont]); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0x3,0x7)[cont]);
# write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {29'b0,continue,2'b11}); # write_control_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {29'b0,continue,2'b11});
def membridge_en(self, def membridge_en(self,
en=True, en=True,
...@@ -232,8 +232,8 @@ class X393McntrlMembridge(object): ...@@ -232,8 +232,8 @@ class X393McntrlMembridge(object):
@param en True - enable, False - disable AXI transfers (reset "Done" if AFI is idle @param en True - enable, False - disable AXI transfers (reset "Done" if AFI is idle
@quiet reduce output (>=1 - silent) @quiet reduce output (>=1 - silent)
''' '''
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0,1)[en]); self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0,1)[en]);
# write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {31'b0,en}); # write_control_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {31'b0,en});
def membridge_rw (self, def membridge_rw (self,
write_ddr3, # input write_ddr3; write_ddr3, # input write_ddr3;
...@@ -317,17 +317,17 @@ class X393McntrlMembridge(object): ...@@ -317,17 +317,17 @@ class X393McntrlMembridge(object):
enable = True, enable = True,
chn_reset = False) chn_reset = False)
# self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64); # self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
# self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address # self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width); self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16)); self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left) # WINDOW_X0+ (WINDOW_Y0<<16)); self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left) # WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode) self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
self.x393_axi_tasks.configure_channel_priority(1,0); # lowest priority channel 1 self.x393_axi_tasks.configure_channel_priority(1,0); # lowest priority channel 1
self.x393_axi_tasks.enable_memcntrl_en_dis(1,1); self.x393_axi_tasks.enable_memcntrl_en_dis(1,1);
# write_contol_register(test_mode_address, TEST01_START_FRAME); # write_control_register(test_mode_address, TEST01_START_FRAME);
self.afi_setup(0) self.afi_setup(0)
self.membridge_setup( self.membridge_setup(
(window_width << 1)*window_height, # ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], #len64, (window_width << 1)*window_height, # ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], #len64,
......
py393/x393_mcntrl_tests.py
View file @ 77c76c3b
This diff is collapsed.
py393/x393_mcntrl_timing.py
View file @ 77c76c3b
...@@ -90,8 +90,8 @@ class X393McntrlTiming(object): ...@@ -90,8 +90,8 @@ class X393McntrlTiming(object):
vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1) vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1)
if quiet<2: if quiet<2:
print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE)) print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
self.x393_axi_tasks.write_contol_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0)
# self.target_phase = phase # self.target_phase = phase
if wait_phase_en: if wait_phase_en:
return self.wait_phase(True, wait_seq) return self.wait_phase(True, wait_seq)
...@@ -160,9 +160,9 @@ class X393McntrlTiming(object): ...@@ -160,9 +160,9 @@ class X393McntrlTiming(object):
""" """
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 8, 1, vrlg.DLY_LANE0_DQS_WLV_IDELAY, "DLY_LANE0_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 8, 1, vrlg.DLY_LANE0_DQS_WLV_IDELAY, "DLY_LANE0_IDELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 8, 1, vrlg.DLY_LANE1_DQS_WLV_IDELAY, "DLY_LANE1_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 8, 1, vrlg.DLY_LANE1_DQS_WLV_IDELAY, "DLY_LANE1_IDELAY")
# self.x393_axi_tasks.write_contol_register(vrlg.LD_DLY_LANE0_IDELAY + 8, vrlg.DLY_LANE0_DQS_WLV_IDELAY) # self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_LANE0_IDELAY + 8, vrlg.DLY_LANE0_DQS_WLV_IDELAY)
# self.x393_axi_tasks.write_contol_register(vrlg.LD_DLY_LANE1_IDELAY + 8, vrlg.DLY_LANE1_DQS_WLV_IDELAY) # self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_LANE1_IDELAY + 8, vrlg.DLY_LANE1_DQS_WLV_IDELAY)
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0)
def axi_set_delays(self,quiet=1): # set all individual delays def axi_set_delays(self,quiet=1): # set all individual delays
""" """
...@@ -206,7 +206,7 @@ class X393McntrlTiming(object): ...@@ -206,7 +206,7 @@ class X393McntrlTiming(object):
print("SET DQ IDELAY="+hexMultiple(delay)) # hexMultiple print("SET DQ IDELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 0, 8, delay[0], "DLY_LANE0_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 0, 8, delay[0], "DLY_LANE0_IDELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 0, 8, delay[1], "DLY_LANE1_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 0, 8, delay[1], "DLY_LANE1_IDELAY")
self.x393_axi_tasks.write_contol_register (vrlg.DLY_SET,0);# // set all delays self.x393_axi_tasks.write_control_register (vrlg.DLY_SET,0);# // set all delays
def axi_set_dq_odelay(self, def axi_set_dq_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -236,7 +236,7 @@ class X393McntrlTiming(object): ...@@ -236,7 +236,7 @@ class X393McntrlTiming(object):
print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY"); self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY"); self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0); # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0); # set all delays
def axi_set_dqs_idelay(self, def axi_set_dqs_idelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -255,7 +255,7 @@ class X393McntrlTiming(object): ...@@ -255,7 +255,7 @@ class X393McntrlTiming(object):
print("SET DQS IDELAY="+hexMultiple(delay)) # hexMultiple print("SET DQS IDELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 8, 1, delay[0], "DLY_LANE0_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 8, 1, delay[0], "DLY_LANE0_IDELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 8, 1, delay[1], "DLY_LANE1_IDELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 8, 1, delay[1], "DLY_LANE1_IDELAY")
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0); # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0); # set all delays
def axi_set_dqs_odelay(self, def axi_set_dqs_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -275,7 +275,7 @@ class X393McntrlTiming(object): ...@@ -275,7 +275,7 @@ class X393McntrlTiming(object):
print("SET DQS ODELAY="+hexMultiple(delay)) # hexMultiple print("SET DQS ODELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 8, 1, delay[0], "DLY_LANE0_ODELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 8, 1, delay[0], "DLY_LANE0_ODELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 8, 1, delay[1], "DLY_LANE1_ODELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 8, 1, delay[1], "DLY_LANE1_ODELAY")
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0); # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0); # set all delays
def axi_set_dm_odelay (self, def axi_set_dm_odelay (self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -294,7 +294,7 @@ class X393McntrlTiming(object): ...@@ -294,7 +294,7 @@ class X393McntrlTiming(object):
print("SET DQM IDELAY="+hexMultiple(delay)) # hexMultiple print("SET DQM IDELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 9, 1, delay[0], "DLY_LANE0_ODELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 9, 1, delay[0], "DLY_LANE0_ODELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 9, 1, delay[1], "DLY_LANE1_ODELAY") self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 9, 1, delay[1], "DLY_LANE1_ODELAY")
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_cmda_odelay(self, def axi_set_cmda_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -324,7 +324,7 @@ class X393McntrlTiming(object): ...@@ -324,7 +324,7 @@ class X393McntrlTiming(object):
if quiet < 2: if quiet < 2:
print("SET COMMAND and ADDRESS ODELAY"+hexMultiple(delay)) print("SET COMMAND and ADDRESS ODELAY"+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 32, delay, "DLY_CMDA"); self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 32, delay, "DLY_CMDA");
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_address_odelay(self, def axi_set_address_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -354,7 +354,7 @@ class X393McntrlTiming(object): ...@@ -354,7 +354,7 @@ class X393McntrlTiming(object):
if quiet < 2: if quiet < 2:
print("SET ADDRESS ODELAY="+hexMultiple(delay)) print("SET ADDRESS ODELAY="+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 0, delay, "DLY_CMDA") self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 0, delay, "DLY_CMDA")
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_bank_odelay(self, def axi_set_bank_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -386,7 +386,7 @@ class X393McntrlTiming(object): ...@@ -386,7 +386,7 @@ class X393McntrlTiming(object):
if quiet < 2: if quiet < 2:
print("SET BANK ODELAY="+hexMultiple(delay)) print("SET BANK ODELAY="+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, bank_offset, 0,delay, "DLY_CMDA") # length will be determined by len(delay) self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, bank_offset, 0,delay, "DLY_CMDA") # length will be determined by len(delay)
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_cmd_odelay(self, def axi_set_cmd_odelay(self,
delay=None, # input [7:0] delay; delay=None, # input [7:0] delay;
...@@ -417,7 +417,7 @@ class X393McntrlTiming(object): ...@@ -417,7 +417,7 @@ class X393McntrlTiming(object):
if quiet < 2: if quiet < 2:
print("SET COMMAND ODELAY="+hexMultiple(delay)) print("SET COMMAND ODELAY="+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, command_offset, 0,delay, "DLY_CMDA") # length will be determined by len(delay) self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, command_offset, 0,delay, "DLY_CMDA") # length will be determined by len(delay)
self.x393_axi_tasks.write_contol_register(vrlg.DLY_SET,0) # set all delays self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_multiple_delays(self, def axi_set_multiple_delays(self,
...@@ -443,7 +443,7 @@ class X393McntrlTiming(object): ...@@ -443,7 +443,7 @@ class X393McntrlTiming(object):
delay= delay + [None]*(number-len(delay)) # delay= delay + [None]*(number-len(delay)) #
for i, d in enumerate(delay): for i, d in enumerate(delay):
if not d is None: if not d is None:
self.x393_axi_tasks.write_contol_register(reg_addr + (offset + i), d) self.x393_axi_tasks.write_control_register(reg_addr + (offset + i), d)
if vname: if vname:
vrlg.set_name_field(vname, offset + i, d) vrlg.set_name_field(vname, offset + i, d)
...@@ -469,7 +469,7 @@ class X393McntrlTiming(object): ...@@ -469,7 +469,7 @@ class X393McntrlTiming(object):
vrlg.DFLT_WBUF_DELAY=delay vrlg.DFLT_WBUF_DELAY=delay
if self.DEBUG_MODE > 1: if self.DEBUG_MODE > 1:
print("SET WBUF DELAY=0x%x"%delay) print("SET WBUF DELAY=0x%x"%delay)
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_PHY_16BIT_ADDR+vrlg.MCONTR_PHY_16BIT_WBUF_DELAY, delay & 0xf) # {28'h0, delay}); self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_16BIT_ADDR+vrlg.MCONTR_PHY_16BIT_WBUF_DELAY, delay & 0xf) # {28'h0, delay});
#set dq /dqs tristate on/off patterns #set dq /dqs tristate on/off patterns
def axi_set_tristate_patterns(self, def axi_set_tristate_patterns(self,
...@@ -529,7 +529,7 @@ class X393McntrlTiming(object): ...@@ -529,7 +529,7 @@ class X393McntrlTiming(object):
if self.DEBUG_MODE > 1: if self.DEBUG_MODE > 1:
print("SET TRISTATE PATTERNS, combined delays=%s"%str(delays)) print("SET TRISTATE PATTERNS, combined delays=%s"%str(delays))
print("SET TRISTATE PATTERNS, combined delays=0x%x"%delays) print("SET TRISTATE PATTERNS, combined delays=0x%x"%delays)
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_PHY_16BIT_ADDR +vrlg.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST}); self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_16BIT_ADDR +vrlg.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
def axi_set_dqs_dqm_patterns(self, def axi_set_dqs_dqm_patterns(self,
dqs_patt=None, dqs_patt=None,
...@@ -550,7 +550,7 @@ class X393McntrlTiming(object): ...@@ -550,7 +550,7 @@ class X393McntrlTiming(object):
if quiet < 2 : if quiet < 2 :
print("axi_set_dqs_dqm_patterns(): SET DQS+DQM PATTERNS, patt= 0x%08x (TODO:reduce quiet threshold)"%patt) print("axi_set_dqs_dqm_patterns(): SET DQS+DQM PATTERNS, patt= 0x%08x (TODO:reduce quiet threshold)"%patt)
# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.) # set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_PHY_16BIT_ADDR + vrlg.MCONTR_PHY_16BIT_PATTERNS, patt) # 32'h0055); self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_16BIT_ADDR + vrlg.MCONTR_PHY_16BIT_PATTERNS, patt) # 32'h0055);
def get_dqs_dqm_patterns(self): def get_dqs_dqm_patterns(self):
#print ('vrlg.dqs_dqm_patt=',vrlg.dqs_dqm_patt) #print ('vrlg.dqs_dqm_patt=',vrlg.dqs_dqm_patt)
......
py393/x393_mem.py
View file @ 77c76c3b
...@@ -215,7 +215,7 @@ class X393Mem(object): ...@@ -215,7 +215,7 @@ class X393Mem(object):
<data> - 32-bit data to write <data> - 32-bit data to write
<verbose> print data being written (default: 0) <verbose> print data being written (default: 0)
""" """
if verbose: if verbose or self.DEBUG_MODE:
print("axi_write_single_w(0x%x,0x%08x)"%(addr,data)) print("axi_write_single_w(0x%x,0x%08x)"%(addr,data))
self.axi_write_single(addr<<2,data) self.axi_write_single(addr<<2,data)
......
py393/x393_pio_sequences.py
View file @ 77c76c3b
...@@ -80,7 +80,7 @@ class X393PIOSequences(object): ...@@ -80,7 +80,7 @@ class X393PIOSequences(object):
<chn> sub-channel to use: 0 - memory read, 1 - memory write <chn> sub-channel to use: 0 - memory read, 1 - memory write
<wait_complete> Do not request a new transaction from the scheduler until previous memory transaction is finished <wait_complete> Do not request a new transaction from the scheduler until previous memory transaction is finished
""" """
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_PS_ADDR + vrlg.MCNTRL_PS_CMD, self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_PS_ADDR + vrlg.MCNTRL_PS_CMD,
# {17'b0, # {17'b0,
((0,1)[wait_complete]<<14) | ((0,1)[wait_complete]<<14) |
((0,1)[chn]<<13) | ((0,1)[chn]<<13) |
...@@ -435,7 +435,7 @@ class X393PIOSequences(object): ...@@ -435,7 +435,7 @@ class X393PIOSequences(object):
<rst> 1 - reset active, 0 - reset off <rst> 1 - reset active, 0 - reset off
""" """
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_PS_ADDR + vrlg.MCNTRL_PS_EN_RST, self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_PS_ADDR + vrlg.MCNTRL_PS_EN_RST,
((0,1)[en]<<1) | #{30'b0,en, ((0,1)[en]<<1) | #{30'b0,en,
(1,0)[rst]) #~rst}); (1,0)[rst]) #~rst});
...@@ -817,12 +817,12 @@ class X393PIOSequences(object): ...@@ -817,12 +817,12 @@ class X393PIOSequences(object):
data=self.func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) data=self.func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# write_contol_register(DLY_SET,0); # write_control_register(DLY_SET,0);
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_ADDRESS, vrlg.REFRESH_OFFSET) self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_ADDRESS, vrlg.REFRESH_OFFSET)
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_PERIOD, t_refi) self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_PERIOD, t_refi)
# enable refresh - should it be done here? # enable refresh - should it be done here?
if en_refresh: if en_refresh:
self.x393_axi_tasks.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0) self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)
def set_mrs(self, # will also calibrate ZQ def set_mrs(self, # will also calibrate ZQ
......
py393/x393_rtc.py
View file @ 77c76c3b
...@@ -37,7 +37,7 @@ import x393_axi_control_status ...@@ -37,7 +37,7 @@ import x393_axi_control_status
import x393_utils import x393_utils
#import time import time
import vrlg import vrlg
class X393Rtc(object): class X393Rtc(object):
DRY_MODE= True # True DRY_MODE= True # True
...@@ -76,17 +76,23 @@ class X393Rtc(object): ...@@ -76,17 +76,23 @@ class X393Rtc(object):
mode, mode,
seq_num) seq_num)
def set_rtc(self, def set_rtc(self,
sec, sec = None,
usec, usec = 0,
corr): corr = 0):
""" """
Set RTC time and correction Set RTC time and correction
@param sec - number of seconds (usually epoch) @param sec - number of seconds (usually epoch)
@param usec - number of microseconds @param usec - number of microseconds
@parame corr signed 16-bit correction (full range is +/- 1/256 @parame corr signed 16-bit correction (full range is +/- 1/256
""" """
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_CORR, corr); #>>> time.time()
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_USEC, usec); #1440958713.117321
self.x393_axi_tasks.write_contol_register(vrlg.RTC_ADDR + vrlg.RTC_SET_SEC, sec); if sec is None:
t = time.time()
sec = int (t)
usec = int (1000 * (t - sec))
self.x393_axi_tasks.write_control_register(vrlg.RTC_ADDR + vrlg.RTC_SET_CORR, corr);
self.x393_axi_tasks.write_control_register(vrlg.RTC_ADDR + vrlg.RTC_SET_USEC, usec);
self.x393_axi_tasks.write_control_register(vrlg.RTC_ADDR + vrlg.RTC_SET_SEC, sec);
py393/x393_sens_cmprs.py
View file @ 77c76c3b
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py393/x393_sensor.py
View file @ 77c76c3b
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util_modules/status_generate.v
View file @ 77c76c3b
...@@ -218,7 +218,9 @@ module status_generate_extra #( ...@@ -218,7 +218,9 @@ module status_generate_extra #(
localparam ALIGNED_STATUS_WIDTH = ((NUM_BYTES - 2) << 3) + 2; // 2 ->2, localparam ALIGNED_STATUS_WIDTH = ((NUM_BYTES - 2) << 3) + 2; // 2 ->2,
// ugly solution to avoid warnings in unused "if" branch // ugly solution to avoid warnings in unused "if" branch
localparam ALIGNED_STATUS_BIT_2 = (ALIGNED_STATUS_WIDTH > 2) ? 2 : 0; localparam ALIGNED_STATUS_BIT_2 = (ALIGNED_STATUS_WIDTH > 2) ? 2 : 0;
localparam STATUS_MASK = (1 << (NUM_BYTES) -1) - 1; localparam STATUS_MASK = (1 << (NUM_BYTES) -1) - 1;
// localparam [EXTRA_WORDS:0] START1HOT = 1 << EXTRA_WORDS;
wire [1:0] mode_w; wire [1:0] mode_w;
reg [1:0] mode; reg [1:0] mode;
...@@ -255,11 +257,14 @@ module status_generate_extra #( ...@@ -255,11 +257,14 @@ module status_generate_extra #(
{{(26-ALIGNED_STATUS_WIDTH){1'b0}},aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}: {{(26-ALIGNED_STATUS_WIDTH){1'b0}},aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}:
{ aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}): { aligned_status[ALIGNED_STATUS_WIDTH-1:ALIGNED_STATUS_BIT_2],seq,aligned_status[1:0]}):
{24'b0,seq,aligned_status[1:0]}; {24'b0,seq,aligned_status[1:0]};
reg shift_data;
genvar i; genvar i;
generate generate
for (i = 0; i < (1<<EXTRA_WORDS_LN2); i=i+1) begin:gen_cyc1 for (i = 0; i < (1<<EXTRA_WORDS_LN2); i=i+1) begin:gen_cyc1
assign pre_mux[32 * i +: 32] = (i < EXTRA_WORDS)? //status[PAYLOAD_BITS + 32*i +:32] : // actually change order! assign pre_mux[32 * i +: 32] = (i < EXTRA_WORDS)? //status[PAYLOAD_BITS + 32*i +:32] : // actually change order!
{status[PAYLOAD_BITS + 32*i + 24 +:8],status[PAYLOAD_BITS + 32*i +:24] }: // {status[PAYLOAD_BITS + 32*i + 24 +:8],status[PAYLOAD_BITS + 32*i +:24] }:
{status[PAYLOAD_BITS + 32*i +:24],status[PAYLOAD_BITS + 32*i + 24 +:8]}:
(((i == EXTRA_WORDS) && (PAYLOAD_BITS > 0)) ? status32 : dont_care); (((i == EXTRA_WORDS) && (PAYLOAD_BITS > 0)) ? status32 : dont_care);
end end
endgenerate endgenerate
...@@ -308,16 +313,18 @@ module status_generate_extra #( ...@@ -308,16 +313,18 @@ module status_generate_extra #(
else if (srst) status_r <= 0; else if (srst) status_r <= 0;
else if (start_last) status_r <= status_r0; else if (start_last) status_r <= status_r0;
if (rst) next_addr <= first_addr; if (rst) next_addr <= first_addr;
else if (srst) next_addr <= first_addr; else if (srst) next_addr <= first_addr;
else if (!need_to_send || start_last) next_addr <= first_addr; else if (!need_to_send || start_last) next_addr <= first_addr;
else if (start && (msg1hot[EXTRA_WORDS -1:0])) next_addr <= STATUS_REG_ADDR; // else if (start && (msg1hot[EXTRA_WORDS -1:0])) next_addr <= STATUS_REG_ADDR;
else if (start) next_addr <= next_addr + 1; else if (start && (msg1hot[EXTRA_WORDS -1])) next_addr <= STATUS_REG_ADDR;
else if (start) next_addr <= next_addr + 1;
if (rst) next_mask <= first_mask; if (rst) next_mask <= first_mask;
else if (srst) next_mask <= first_mask; else if (srst) next_mask <= first_mask;
else if (!need_to_send || start_last) next_mask <= first_mask; else if (!need_to_send || start_last) next_mask <= first_mask;
else if (start && (msg1hot[EXTRA_WORDS -1 :0])) next_mask <= STATUS_MASK; // else if (start && (msg1hot[EXTRA_WORDS -1 :0])) next_mask <= STATUS_MASK;
else if (start && (msg1hot[EXTRA_WORDS -1])) next_mask <= STATUS_MASK;
if (rst) rq_r <= 0; if (rst) rq_r <= 0;
else if (srst) rq_r <= 0; else if (srst) rq_r <= 0;
...@@ -330,17 +337,24 @@ module status_generate_extra #( ...@@ -330,17 +337,24 @@ module status_generate_extra #(
else if (!need_to_send) msg_num <= 0; else if (!need_to_send) msg_num <= 0;
else if (start) msg_num <= msg_num + 1; else if (start) msg_num <= msg_num + 1;
if (rst) msg1hot <= 0; if (rst) msg1hot <= 1;
else if (srst) msg1hot <= 0; else if (srst) msg1hot <= 1;
else if (!need_to_send) msg1hot <= 0; else if (!need_to_send) msg1hot <= 1;
else if (start) msg1hot <= msg1hot >> 1; // else if (start) begin
// if (|msg1hot) msg1hot <= (msg1hot >> 1);
// else msg1hot <= 1 << (NUM_MSG-1);
// end
else if (start) if (|msg1hot) msg1hot <= msg1hot << 1;
if (rst) shift_data <= 0;
else if (srst || !rq) shift_data <= 0;
else if (start) shift_data <= 1;
end end
always @ (posedge clk) begin always @ (posedge clk) begin
if (!rq) data <= {next_addr, pre_mux[32 * msg_num +:32]}; // if (!rq) data <= {next_addr, pre_mux[32 * msg_num +:32]};
else if (start || start) data <= data >> 8; if (!rq) data <= {pre_mux[32 * msg_num +:32], next_addr};
else if (start || shift_data) data <= data >> 8;
end end
//http://www.edaboard.com/thread177879.html //http://www.edaboard.com/thread177879.html
function integer clogb2; function integer clogb2;
......
x393_testbench02.tf
View file @ 77c76c3b
...@@ -965,6 +965,9 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -965,6 +965,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
0); // input [1:0] sub_channel; 0); // input [1:0] sub_channel;
// just temporarily - enable channel immediately // just temporarily - enable channel immediately
// enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1); // enable_memcntrl_en_dis(4'hc + {2'b0,num_sensor}, 1);
program_status_rtc( // also takes snapshot
3, // input [1:0] mode;
0); //input [5:0] seq_num;
`endif `endif
...@@ -978,6 +981,9 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -978,6 +981,9 @@ assign #10 gpio_pins[9] = gpio_pins[8];
TEST_TITLE = "ALL_DONE"; TEST_TITLE = "ALL_DONE";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
#20000; #20000;
program_status_rtc( // also takes snapshot
3, // input [1:0] mode;
0); //input [5:0] seq_num;
TEST_TITLE = "WAITING 80usec more"; TEST_TITLE = "WAITING 80usec more";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
#80000; #80000;
...@@ -3021,17 +3027,43 @@ task set_sensor_io_ctl; ...@@ -3021,17 +3027,43 @@ task set_sensor_io_ctl;
reg [31:0] data; reg [31:0] data;
reg [29:0] reg_addr; reg [29:0] reg_addr;
begin begin
reg_addr = (SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC) + SENSIO_RADDR + SENSIO_CTRL;
if (clk_sel & 2) begin // reset MMCM before changing clock source
data = func_sensor_io_ctl (
0, // mrst,
0, // arst,
0, // aro,
3, // mmcm_rst,
0, // clk_sel,
0, // set_delays,
0, // set_quadrants,
0); // quadrants);
write_contol_register(reg_addr, data);
end
data = func_sensor_io_ctl ( data = func_sensor_io_ctl (
mrst, mrst,
arst, arst,
aro, aro,
mmcm_rst, 0, // mmcm_rst,
clk_sel, clk_sel,
set_delays, set_delays,
set_quadrants, set_quadrants,
quadrants); quadrants);
reg_addr = (SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC) + SENSIO_RADDR + SENSIO_CTRL;
write_contol_register(reg_addr, data); write_contol_register(reg_addr, data);
if ((clk_sel & 2) && !(mmcm_rst == 3)) begin // release reset MMCM after changing clock source (only if it was not requested on)
data = func_sensor_io_ctl (
0, // mrst,
0, // arst,
0, // aro,
2, // mmcm_rst,
0, // clk_sel,
0, // set_delays,
0, // set_quadrants,
0); // quadrants);
write_contol_register(reg_addr, data);
end
end end
endtask endtask
......
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