Commit 77c76c3b authored by Andrey Filippov's avatar Andrey Filippov

hardware debugging/bug fixing

parent 72068ae7
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150826175759893.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150831151630695.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150826180314606.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150831152219741.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150826175759893.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150831151630695.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150826180314606.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150831152219741.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150826180314606.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150831152219741.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150826180314606.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150831152219741.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150826175759893.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150831151630695.dcp</location>
</link>
</linkedResources>
</projectDescription>
parameter FPGA_VERSION = 32'h03930001;
parameter FPGA_VERSION = 32'h03930003;
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -124,7 +124,7 @@ class X393AxiControlStatus(object):
return refresh_en
def get_enabled_channels(self,quiet=1):
# global enabled_channels
enabled_channels = self.read_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
enabled_channels = self.read_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
if quiet<2 :
print ("ENABLED_CHANNELS = 0x%x"%enabled_channels)
return enabled_channels
......@@ -135,7 +135,7 @@ class X393AxiControlStatus(object):
if quiet<2 :
print ("CHANNEL PRIORITIES:",end=" ")
for chn in range (16):
v = self.read_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn)
v = self.read_control_register(vrlg.MCONTR_ARBIT_ADDR + chn)
print ("%d"%v,end=" ")
channel_priority.append(v)
"""
......@@ -160,7 +160,7 @@ class X393AxiControlStatus(object):
'sequences_set': self.get_sequences_set(quiet)
}
def write_contol_register(self, reg_addr, data):
def write_control_register(self, reg_addr, data):
"""
Write 32-bit word to the control register
@param addr - register address relative to the control register address space
......@@ -168,7 +168,7 @@ class X393AxiControlStatus(object):
"""
self.x393_mem.axi_write_single_w(vrlg.CONTROL_ADDR+reg_addr, data)
def read_contol_register(self, reg_addr=None, quiet=1):
def read_control_register(self, reg_addr=None, quiet=1):
"""
Read 32-bit word from the control register (written by the software or the command sequencer)
@param addr - register address relative to the control register address space
......@@ -240,7 +240,7 @@ class X393AxiControlStatus(object):
data=self.read_status(status_address)
if wait_seq:
seq_num = ((data >> vrlg.STATUS_SEQ_SHFT) ^ 0x20) & 0x30
self.write_contol_register(status_control_address, ((status_mode & 3) <<6) | (seq_num & 0x3f))
self.write_control_register(status_control_address, ((status_mode & 3) <<6) | (seq_num & 0x3f))
data=self.read_status(status_address)
while (((data >> vrlg.STATUS_SEQ_SHFT) ^ seq_num) & 0x30) !=0:
data=self.read_status(status_address)
......@@ -281,7 +281,14 @@ class X393AxiControlStatus(object):
print ("MCNTRL_TEST01_STATUS_REG_CHN3_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),8)))
print ("MCNTRL_TEST01_STATUS_REG_CHN4_ADDR: %s"%(hx(self.read_status(vrlg.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR),8)))
print ("MEMBRIDGE_STATUS_REG: %s"%(hx(self.read_status(vrlg.MEMBRIDGE_STATUS_REG),8)))
items_per_line = 8
for i in range (256):
if not i % items_per_line:
print ("\n0x%02x: "%(i), end = "")
d=hx(self.read_status(i),8)
print ("%s "%(d), end = "")
print ()
def program_status(self,
base_addr, # input [29:0] base_addr;
reg_addr, # input [7:0] reg_addr;
......@@ -298,7 +305,7 @@ class X393AxiControlStatus(object):
4: auto, inc sequence number
<seq_number> - 6-bit sequence number of the status message to be sent
"""
self.write_contol_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f))
self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f))
def program_status_all( self,
......@@ -337,7 +344,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en]
if self.verbose>0:
print ("ENABLE CMDA %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0);
self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0);
cmda_en=en
def enable_cke(self,
......@@ -350,7 +357,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en]
if self.verbose>0:
print ("ENABLE CKE %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0);
self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0);
cke_en=en
def activate_sdrst(self,
......@@ -363,7 +370,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en]
if self.verbose>0:
print ("ACTIVATE SDRST %s"%str(en))
self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
self.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
sdrst_on=en
def enable_refresh(self,
......@@ -376,7 +383,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en]
if self.verbose>0:
print ("ENABLE REFRESH %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
self.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
refresh_en=en
def enable_memcntrl(self,
......@@ -389,7 +396,7 @@ class X393AxiControlStatus(object):
en=(0,1)[en]
if self.verbose > 0:
print ("ENABLE MEMCTRL %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
self.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
mcntrl_en=en
def enable_memcntrl_channels(self,
chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable;
......@@ -399,7 +406,7 @@ class X393AxiControlStatus(object):
"""
# global enabled_channels
enabled_channels = chnen # currently enabled memory channels
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
self.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))
......@@ -413,12 +420,12 @@ class X393AxiControlStatus(object):
"""
# global enabled_channels
# Adding readback register
enabled_channels = self.read_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
enabled_channels = self.read_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN)
if en:
enabled_channels |= 1<<chn;
else:
enabled_channels &= ~(1<<chn);
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
self.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)
......@@ -431,7 +438,7 @@ class X393AxiControlStatus(object):
<priority> - 16-bit priority value (higher value means more important)
"""
# global channel_priority
self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
self.write_control_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
if self.verbose > 0:
print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
# channel_priority[chn]=priority
......
......@@ -93,7 +93,7 @@ class X393Camsync(object):
data |= (4 | (master_chn & 3)) << (vrlg.CAMSYNC_MASTER_BIT - 2)
if not chn_en is None:
data |= (0x10 | (chn_en & 0xf)) << (vrlg.CAMSYNC_CHN_EN_BIT - 4)
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_MODE, data);
self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_MODE, data);
def set_camsync_inout(self,
is_out,
......@@ -111,7 +111,7 @@ class X393Camsync(object):
db=(2,3)[active_positive]
data &= ~(3 << (2 * bit_number))
data |= (db << (2 * bit_number))
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR +
self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR +
(vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], data)
def reset_camsync_inout(self,
......@@ -120,7 +120,7 @@ class X393Camsync(object):
Reset camsync inputs or outputs to inactive/don't care state
@param is_out - True for outputs, False for inputs
"""
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR +
self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR +
(vrlg.CAMSYNC_TRIG_SRC,vrlg.CAMSYNC_TRIG_DST)[is_out], 0)
def set_camsync_period(self,
......@@ -129,7 +129,7 @@ class X393Camsync(object):
Set camsync period
@param period - period value in 10 ns steps - max 42.95 sec
"""
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, period)
self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, period)
def set_camsync_delay(self,
sub_chn,
......@@ -139,7 +139,7 @@ class X393Camsync(object):
@param sub_chn - sensor channel (0..3)
@param delay - delay value in 10 ns steps - max 42.95 sec
"""
self.x393_axi_tasks.write_contol_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, delay)
self.x393_axi_tasks.write_control_register(vrlg.CAMSYNC_ADDR + vrlg.CAMSYNC_TRIG_PERIOD, delay)
def camsync_setup(self,
sensor_mask = None,
......
......@@ -182,7 +182,7 @@ class X393Cmprs(object):
data = self.func_compressor_format (num_macro_cols_m1 = num_macro_cols_m1,
num_macro_rows_m1 = num_macro_rows_m1,
left_margin = left_margin)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_FORMAT,
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_FORMAT,
data)
def compressor_color_saturation (self,
......@@ -196,7 +196,7 @@ class X393Cmprs(object):
"""
data = self.func_compressor_color_saturation (colorsat_blue = colorsat_blue,
colorsat_red = colorsat_red)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_COLOR_SATURATION,
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_COLOR_SATURATION,
data)
def compressor_coring (self,
......@@ -207,7 +207,7 @@ class X393Cmprs(object):
@param coring - coring value
"""
data = coring & ((1 << vrlg.CMPRS_CORING_BITS) - 1)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CORING_MODE,
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CORING_MODE,
data)
def compressor_control (self,
......@@ -251,7 +251,7 @@ class X393Cmprs(object):
multi_frame = multi_frame,
bayer = bayer,
focus_mode = focus_mode)
self.x393_axi_tasks.write_contol_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG,
self.x393_axi_tasks.write_control_register(vrlg.CMPRS_GROUP_ADDR + chn * vrlg.CMPRS_BASE_INC + vrlg.CMPRS_CONTROL_REG,
data)
def setup_compressor_memory (self,
num_sensor,
......@@ -297,31 +297,31 @@ class X393Cmprs(object):
write_mem = False,
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_STARTADDR,
frame_sa) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_SIZE,
frame_sa_inc)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_LAST,
last_frame_num)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
frame_full_width)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
((window_height & 0xffff) << 16) | (window_width & 0xffff)) #/WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
((window_top & 0xffff) << 16) | (window_left & 0xffff)) #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
0)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_TILE_WHS,
((tile_vstep & 0xff) <<16) | ((tile_height & 0xff) <<8) | (tile_width & 0xff)) #//(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_MODE,
mode);
def compressor_run(self, # may use compressor_control with the same arguments
......
......@@ -91,7 +91,7 @@ class X393CmprsAfi(object):
@param port_afi - number of AFI port (0 - afi 1, 1 - afi2)
@param rst_chn - bit mask of channels to reset (persistent, needs release)
"""
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_RST,
rst_chn)
def afi_mux_enable_chn (self,
......@@ -104,7 +104,7 @@ class X393CmprsAfi(object):
@param en_chn - number of afi input channel to enable/disable (0..3)
@param en - number enable (True) or disable (False) selected AFI input
"""
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN,
(2,3)[en] << (2 * en_chn))
......@@ -117,7 +117,7 @@ class X393CmprsAfi(object):
@param en_chn - number of afi input channel to enable/disable (0..3)
@param en - number enable (True) or disable (False) selected AFI input
"""
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_EN,
(2,3)[en] << (2 * 4))
......@@ -135,7 +135,7 @@ class X393CmprsAfi(object):
mode == 2 - show current pointer, internal
mode == 3 - show current pointer, confirmed written to the system memory
"""
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_MODE,
(4 + (mode & 3)) << (4 * chn))
......@@ -152,10 +152,10 @@ class X393CmprsAfi(object):
@param length - channel buffer length in 32-byte chunks
"""
reg_addr = vrlg.CMPRS_GROUP_ADDR + (vrlg.CMPRS_AFIMUX_RADDR0,vrlg.CMPRS_AFIMUX_RADDR1)[port_afi] + vrlg.CMPRS_AFIMUX_SA_LEN + chn
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
reg_addr,
sa)
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
reg_addr + 4,
length)
......
......@@ -77,7 +77,7 @@ class X393FrameSequencer(object):
data |= 1 << (vrlg.CMDFRAMESEQ_RUN_BIT -1)
if start or stop:
data |= 1 << vrlg.CMDFRAMESEQ_RUN_BIT
self.x393_axi_tasks.write_contol_register(
self.x393_axi_tasks.write_control_register(
vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + vrlg.CMDFRAMESEQ_CTRL,
data)
......@@ -100,6 +100,6 @@ class X393FrameSequencer(object):
if relative and (frame_addr == 0xf):
raise Exception ("task write_cmd_frame_sequencer(): relative address 0xf is invalid, it is reserved for module control")
reg_addr = vrlg.CMDFRAMESEQ_ADDR_BASE + num_sensor * vrlg.CMDFRAMESEQ_ADDR_INC + (vrlg.CMDFRAMESEQ_ABS,vrlg.CMDFRAMESEQ_REL)[relative] + frame_addr
self.x393_axi_tasks.write_contol_register( reg_addr, addr) # two writes to the same location - first is the register address
self.x393_axi_tasks.write_contol_register( reg_addr, data) # second is data to write to that register
self.x393_axi_tasks.write_control_register( reg_addr, addr) # two writes to the same location - first is the register address
self.x393_axi_tasks.write_control_register( reg_addr, data) # second is data to write to that register
......@@ -37,7 +37,7 @@ import x393_axi_control_status
import x393_utils
#import time
import time
import vrlg
class X393GPIO(object):
DRY_MODE= True # True
......@@ -95,7 +95,7 @@ class X393GPIO(object):
data |= (2,3)[port_a] << 4
if not port_c is None:
data |= (2,3)[port_a] << 6
self.x393_axi_tasks.write_contol_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN)
self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data << vrlg.GPIO_PORTEN)
def set_gpio_pins(self,
ext0 = None,
......@@ -133,5 +133,5 @@ class X393GPIO(object):
data |= 3 << (2*i)
else:
raise Exception ("Expecting one of 'L', 'H', 'I', got "+str(e)+" for ext"+str(i))
self.x393_axi_tasks.write_contol_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data)
self.x393_axi_tasks.write_control_register(vrlg.GPIO_ADDR + vrlg.GPIO_SET_PINS, data)
......@@ -36,7 +36,7 @@ import x393_axi_control_status
import x393_pio_sequences
import x393_mcntrl_timing
import x393_mcntrl_buffers
import verilog_utils
#import verilog_utils
import x393_mcntrl
MEM_PATH='/sys/devices/elphel393-mem.2/'
BUFFER_ASSRESS_NAME='buffer_address'
......@@ -118,7 +118,7 @@ class X393McntrlMembridge(object):
with open(MEM_PATH+BUFFER_PAGES_NAME) as sysfile:
BUFFER_LEN=PAGE_SIZE*int(sysfile.read(),0)
except:
print("Failed to get resderved physical memory range")
print("Failed to get reserved physical memory range")
print('BUFFER_ADDRESS=',BUFFER_ADDRESS)
print('BUFFER_LEN=',BUFFER_LEN)
return
......@@ -206,12 +206,12 @@ class X393McntrlMembridge(object):
if quiet <2:
print("membridge_setup(0x%08x,0x%0xx,0x%08x,0x%0xx,0x%08x,%d)"%(len64, width64, start64, lo_addr64, size64, quiet))
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64, len64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LO_ADDR64, lo_addr64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_SIZE64, size64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64, len64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache);
def membridge_start(self,
cont=False,
......@@ -221,8 +221,8 @@ class X393McntrlMembridge(object):
@param cont - continue with the current system memory pointer, False - start with lo_addr64+start64
@quiet reduce output (>=1 - silent)
'''
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0x3,0x7)[cont]);
# write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {29'b0,continue,2'b11});
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0x3,0x7)[cont]);
# write_control_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {29'b0,continue,2'b11});
def membridge_en(self,
en=True,
......@@ -232,8 +232,8 @@ class X393McntrlMembridge(object):
@param en True - enable, False - disable AXI transfers (reset "Done" if AFI is idle
@quiet reduce output (>=1 - silent)
'''
self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0,1)[en]);
# write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {31'b0,en});
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_CTRL, (0,1)[en]);
# write_control_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {31'b0,en});
def membridge_rw (self,
write_ddr3, # input write_ddr3;
......@@ -317,17 +317,17 @@ class X393McntrlMembridge(object):
enable = True,
chn_reset = False)
# self.x393_axi_tasks.write_contol_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
# self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left) # WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_contol_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
# self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
# self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_STARTADDR, frame_start_addr) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, window_full_width);
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width) # WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left) # WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, 0)
self.x393_axi_tasks.write_control_register(vrlg.MCNTRL_SCANLINE_CHN1_ADDR + vrlg.MCNTRL_SCANLINE_MODE, mode)
self.x393_axi_tasks.configure_channel_priority(1,0); # lowest priority channel 1
self.x393_axi_tasks.enable_memcntrl_en_dis(1,1);
# write_contol_register(test_mode_address, TEST01_START_FRAME);
# write_control_register(test_mode_address, TEST01_START_FRAME);
self.afi_setup(0)
self.membridge_setup(
(window_width << 1)*window_height, # ((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], #len64,
......
......@@ -300,17 +300,17 @@ class X393McntrlTests(object):
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height<<16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top<<16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height<<16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top<<16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);
self.x393_axi_tasks.configure_channel_priority(channel,0); # lowest priority channel 3
# enable_memcntrl_channels(16'h000b); # channels 0,1,3 are enabled
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_START_FRAME);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME);
for ii in range(0,vrlg.TEST_INITIAL_BURST): # for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
# VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
if pages_per_row > 1:
......@@ -358,7 +358,7 @@ class X393McntrlTests(object):
xfer_size,
startx, # window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), # SCANLINE_CUR_X,
starty) # window_top + (ii / pages_per_row)); # SCANLINE_CUR_Y);
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
if wait_done:
self.x393_axi_tasks.wait_status_condition ( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......@@ -448,16 +448,16 @@ class X393McntrlTests(object):
chn_reset = False)
# program to the
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, vrlg.FRAME_START_ADDRESS); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_FRAME_FULL_WIDTH, vrlg.FRAME_FULL_WIDTH);
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_WH, (window_height << 16) | window_width); #WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_X0Y0, (window_top << 16) | window_left); #WINDOW_X0+ (WINDOW_Y0<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_WINDOW_STARTXY, vrlg.SCANLINE_STARTX+(vrlg.SCANLINE_STARTY<<16));
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_SCANLINE_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0); # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_START_FRAME);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME);
for ii in range(window_height * pages_per_row): # for (ii=0;ii<(window_height * pages_per_row);ii = ii+1) begin
if pages_per_row > 1:
if (ii % pages_per_row) < (pages_per_row-1):
......@@ -483,7 +483,7 @@ class X393McntrlTests(object):
xfer_size <<2,
# 1, # chn=0, page=3, number of 32-bit words=256, show_rslt
show_data))
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE)
return result
......@@ -563,28 +563,28 @@ class X393McntrlTests(object):
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
vrlg.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
concat(((window_height,16),
(window_width, 16)))[0]) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
concat(((window_top, 16),
(window_left, 16)))[0]) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
concat(((vrlg.TILED_STARTY, 16),
(vrlg.TILED_STARTX, 16)))[0]) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))[0]) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_START_FRAME);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME);
for ii in range(vrlg.TEST_INITIAL_BURST): # for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
print("########### test_tiled_write block %d: channel=%d"%( ii, channel))
......@@ -616,7 +616,7 @@ class X393McntrlTests(object):
tile_size,
startx, # window_left + ((ii % tiles_per_row) * tile_width),
starty) # window_top + (ii / tile_rows_per_window)); # SCANLINE_CUR_Y);\
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_NEXT_PAGE);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE);
if wait_done:
self.x393_axi_tasks.wait_status_condition( # may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, # MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......@@ -705,28 +705,28 @@ class X393McntrlTests(object):
enable = True,
chn_reset = False)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, 0); # reset channel, including page address
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_STARTADDR,
vrlg.FRAME_START_ADDRESS) # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_FRAME_FULL_WIDTH,
vrlg.FRAME_FULL_WIDTH)
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_WH,
concat(((window_height,16),
(window_width, 16)))[0]) # {window_height,window_width});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_X0Y0,
concat(((window_top, 16),
(window_left, 16)))[0]) # {window_top,window_left});
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_WINDOW_STARTXY,
concat(((vrlg.TILED_STARTY, 16),
(vrlg.TILED_STARTX, 16)))[0]) # TILED_STARTX+(TILED_STARTY<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_TILE_WHS,
concat(((tile_vstep, 8),
(tile_height, 8),
(tile_width, 8)))[0]) # {8'b0,tile_vstep,tile_height,tile_width});#tile_width+(tile_height<<8)+(tile_vstep<<16));
self.x393_axi_tasks.write_contol_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.write_control_register(start_addr + vrlg.MCNTRL_TILED_MODE, mode);# set mode register: {extra_pages[1:0],enable,!reset}
self.x393_axi_tasks.configure_channel_priority(channel,0) # lowest priority channel 3
self.x393_axi_tasks.enable_memcntrl_en_dis(channel,1);
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_START_FRAME);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_START_FRAME);
for ii in range(tiles_per_row * tile_rows_per_window): # (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
self.x393_axi_tasks.wait_status_condition (
status_address, # MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
......@@ -744,6 +744,6 @@ class X393McntrlTests(object):
tile_size <<2,
# 1, # chn=0, page=3, number of 32-bit words=256, show_rslt
show_data))
self.x393_axi_tasks.write_contol_register(test_mode_address, vrlg.TEST01_NEXT_PAGE);
self.x393_axi_tasks.write_control_register(test_mode_address, vrlg.TEST01_NEXT_PAGE);
# enable_memcntrl_en_dis(channel,0); # disable channel
return result
......@@ -90,8 +90,8 @@ class X393McntrlTiming(object):
vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1)
if quiet<2:
print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
self.x393_axi_tasks.write_contol_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
self.