simulating/bug fixing (75f18826) · Commits · Elphel / x393

.settings/com.elphel.vdt.FPGA_project.prefs

+2 −2

Original line number	Diff line number	Diff line
		FPGA_project_0_SimulationTopFile=x393_testbench02.tf
		FPGA_project_1_SimulationTopModule=x393_testbench02
		FPGA_project_0_SimulationTopFile=x393_testbench03.tf
		FPGA_project_1_SimulationTopModule=x393_testbench03
		FPGA_project_2_ImplementationTopFile=x393.v
		FPGA_project_4_part=xc7z030fbg484-1
		FPGA_project_5_part=xc7z030fbg484-1

includes/x393_parameters.vh

+46 −5

Original line number	Diff line number	Diff line
		@@ -429,11 +429,20 @@
		parameter SENS_CTRL_ARST = 2, // 3: 2
		parameter SENS_CTRL_ARO = 4, // 5: 4
		parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
		//`ifdef HISPI
		parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
		//`else
		parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
		//`endif
		parameter SENS_CTRL_LD_DLY = 10, // 10
		//`ifdef HISPI
		parameter SENS_CTRL_GP0= 12, // 13:12
		parameter SENS_CTRL_GP1= 14, // 15:14
		//`else
		parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
		parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
		parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
		//`endif
		parameter SENSIO_STATUS = 'h1,
		parameter SENSIO_JTAG = 'h2,
		// SENSIO_JTAG register bits
		@@ -442,7 +451,9 @@
		parameter SENS_JTAG_TCK = 4,
		parameter SENS_JTAG_TMS = 2,
		parameter SENS_JTAG_TDI = 0,
		//`ifndef HISPI
		parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
		//`endif
		parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
		// 4 of 8-bit delays per register
		// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
		@@ -466,10 +477,13 @@
		parameter SENSI2C_IOSTANDARD = "LVCMOS25",
		parameter SENSI2C_SLEW = "SLOW",

		//`ifndef HISPI
		//sensor_fifo parameters
		parameter SENSOR_DATA_WIDTH = 12,
		parameter SENSOR_FIFO_2DEPTH = 4,
		parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
		parameter SENSOR_FIFO_DELAY = 5, // 7,
		//`endif

		// other parameters for histogram_saxi module
		parameter HIST_SAXI_ADDR_MASK = 'h7f0,
		parameter HIST_SAXI_MODE_WIDTH = 8,
		@@ -505,15 +519,30 @@
		`endif
		parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",

		//`ifdef HISPI
		parameter PXD_CAPACITANCE = "DONT_CARE",
		parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
		parameter PXD_CLK_DIV_BITS = 4,
		//`endif

		parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
		parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

		// parameters for the sensor-synchronous clock PLL
		`ifdef HISPI
		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,
		`else
		parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,

		`endif
		// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
		// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",

		@@ -536,6 +565,18 @@
		parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
		parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns

		//`ifdef HISPI
		parameter HISPI_MSB_FIRST = 0,
		parameter HISPI_NUMLANES = 4,
		parameter HISPI_CAPACITANCE = "DONT_CARE",
		parameter HISPI_DIFF_TERM = "TRUE",
		parameter HISPI_DQS_BIAS = "TRUE",
		parameter HISPI_IBUF_DELAY_VALUE = "0",
		parameter HISPI_IBUF_LOW_PWR = "TRUE",
		parameter HISPI_IFD_DELAY_VALUE = "AUTO",
		parameter HISPI_IOSTANDARD = "DEFAULT",
		//`endif

		parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
		parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
		parameter CMPRS_BASE_INC = 'h10,

includes/x393_simulation_parameters.vh

+10 −0

Original line number	Diff line number	Diff line
		@@ -38,6 +38,15 @@
		// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
		// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
		// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
		`ifdef HISPI
		parameter SENSOR12BITS_NGPL = 2, // bpf to hact
		parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
		//parameter tMD = 14; //
		//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
		parameter SENSOR12BITS_TMD = 1.2, //
		parameter SENSOR12BITS_TDDO = 0.8, // some confusion here - let's assume that it is from DCLK to Data out
		parameter SENSOR12BITS_TDDO1 = 1.6, //
		`else
		parameter SENSOR12BITS_NGPL = 8, // bpf to hact
		parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
		//parameter tMD = 14; //
		@@ -45,6 +54,7 @@
		parameter SENSOR12BITS_TMD = 4, //
		parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
		parameter SENSOR12BITS_TDDO1 = 5, //
		`endif
		// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
		// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
		// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)

sensor/sens_10398.v

+41 −87

Original line number	Diff line number	Diff line
		@@ -56,10 +56,11 @@ module sens_10398 #(
		parameter real REFCLK_FREQUENCY = 200.0,
		parameter HIGH_PERFORMANCE_MODE = "FALSE",
		parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
		parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

		parameter CLKFBOUT_MULT_SENSOR = 4, // 220 MHz --> 880 MHz
		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,
		@@ -127,10 +128,11 @@ module sens_10398 #(

		input sns_flash_tdo, // sns_dp[4] TDO (differs from 10353)
		input sns_shutter_done,// sns_dn[4] DONE (differs from 10353)
		// output

		output [11:0] pxd,
		output vact,
		output hact
		output hact,
		output sof, // @pclk
		output eof // @pclk


		);
		@@ -145,18 +147,6 @@ module sens_10398 #(
		reg set_status_r;
		reg set_jtag_r;

		// reg [LINE_WIDTH_BITS-1:0] line_width_m1; // regenerated HACT duration;
		// reg [LINE_WIDTH_BITS-1:0] line_width_m1_ipclk; // regenerated HACT duration;

		// reg line_width_internal; // use regenetrated ( 0 - use HACT as is)
		// reg line_width_internal_ipclk;
		// reg [LINE_WIDTH_BITS-1:0] hact_cntr;

		// reg set_quad; // [1:0] - px, [3:2] - HACT, [5:4] - VACT,

		// wire [2:0] set_pxd_delay;
		// wire set_other_delay;

		wire ps_rdy;
		wire [7:0] ps_out;
		wire locked_pxd_mmcm;
		@@ -167,17 +157,11 @@ module sens_10398 #(
		reg iaro_soft = 0;
		wire iaro;
		reg iarst = 0;
		reg imrst = 0;
		reg imrst = 0; // active low
		reg rst_mmcm=1; // rst and command - en/dis
		// reg [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants=0; //90-degree shifts for data {1:0], hact [3:2] and vact [5:4]
		reg ld_idelay=0;
		// reg sel_ext_clk=0; // select clock source from the sensor (0 - use internal clock - to sensor)

		reg ignore_embed=0; // do not process sensor data marked as "embedded"



		// wire [17:0] status;
		wire [14:0] status;

		wire cmd_we;
		@@ -195,30 +179,10 @@ module sens_10398 #(
		reg xfpgatdi=0; // TDI to be sent to external FPGA

		reg [1:0] gp_r; // sensor GP0, GP1. For now just software control, later use for something else
		// wire hact_ext; // received hact signal
		// reg hact_ext_r; // received hact signal, delayed by 1 clock
		// reg hact_r; // received or regenerated hact

		// for debug/test alive
		/*
		reg vact_r;
		reg hact_r2;
		wire vact_a_mclk;
		wire hact_ext_a_mclk;
		wire hact_a_mclk;
		reg vact_alive;
		reg hact_ext_alive;
		reg hact_alive;
		reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
		*/
		reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
		// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
		// parameter PXD_CLK_DIV_BITS = 4,
		reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
		wire async_prst_with_sens_mrst = ~imrst \| rst_mmcm; // mclk domain


		// assign set_pxd_delay = set_idelay[2:0];
		// assign set_other_delay = set_idelay[3];
		// assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
		assign status = { locked_pxd_mmcm,
		clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
		ps_rdy, ps_out, xfpgatdo, senspgmin};
		@@ -273,15 +237,9 @@ module sens_10398 #(
		if (mrst) rst_mmcm <= 0;
		else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1]) rst_mmcm <= data_r[SENS_CTRL_RST_MMCM];

		// if (mrst) sel_ext_clk <= 0;
		// else if (set_ctrl_r && data_r[SENS_CTRL_EXT_CLK + 1]) sel_ext_clk <= data_r[SENS_CTRL_EXT_CLK];
		if (mrst) ignore_embed <= 0;
		else if (set_ctrl_r && data_r[SENS_CTRL_IGNORE_EMBED + 1]) ignore_embed <= data_r[SENS_CTRL_IGNORE_EMBED];


		// if (mrst) quadrants <= 0;
		// else if (set_ctrl_r && data_r[SENS_CTRL_QUADRANTS_EN]) quadrants <= data_r[SENS_CTRL_QUADRANTS +: SENS_CTRL_QUADRANTS_WIDTH];

		if (mrst) ld_idelay <= 0;
		else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];

		@@ -291,27 +249,22 @@ module sens_10398 #(
		if (mrst) gp_r[1] <= 0;
		else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 1]) gp_r[1] <= data_r[SENS_CTRL_GP1];




		// if (mrst) set_width_r <= 0;
		// else set_width_r <= {set_width_r[0],cmd_we && (cmd_a== SENSIO_WIDTH)};

		// if (mrst) line_width_m1 <= 0;
		// else if (set_width_r[1]) line_width_m1 <= data_r[LINE_WIDTH_BITS-1:0] -1;

		// if (mrst) line_width_internal <= 0;
		// else if (set_width_r[1]) line_width_internal <= ~ (\|data_r[LINE_WIDTH_BITS:0]); // line width is 0
		end

		// generate (slow) clock for the sensor - it will be multiplied by the sensor VCO
		always @(posedge pclk) begin
		if (prst \|\| (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0)) pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= (PXD_CLK_DIV / 2);
		else pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] <= pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] - 1;

		// treat MSB separately to make 50% duty cycle
		if (prst) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= 0;
		else if (pxd_clk_cntr[PXD_CLK_DIV_BITS-2:0] == 0) pxd_clk_cntr[PXD_CLK_DIV_BITS-1] <= ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1];

		// reg [ PXD_CLK_DIV_BITS-1:0] pxd_clk_cntr;
		end

		always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
		if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
		else if (prst) prst_with_sens_mrst <= 2'h3;
		else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;

		end
		cmd_deser #(
		@@ -353,8 +306,8 @@ module sens_10398 #(
		.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
		.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
		.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
		.SENS_BANDWIDTH (SENS_BANDWIDTH),
		.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
		.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
		.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
		.IPCLK_PHASE (IPCLK_PHASE),
		@@ -378,14 +331,15 @@ module sens_10398 #(
		.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
		) sens_hispi12l4_i (
		.pclk (pclk), // input
		.prst (prst), // input
		.prst (prst_with_sens_mrst[0]), //prst), // input
		.sns_dp (sns_dp[3:0]), // input[3:0]
		.sns_dn (sns_dn[3:0]), // input[3:0]
		.sns_clkp (sns_clkp), // input
		.sns_clkn (sns_clkn), // input
		.pxd_out (pxd), // output[11:0] reg
		.vact_out (vact), // output reg
		.hact_out (hact), // output
		.sof (sof), // output
		.eof (eof), // output reg
		.mclk (mclk), // input
		.mrst (mrst), // input
		.dly_data (data_r), // input[31:0]

sensor/sens_hispi12l4.v

+73 −31

Original line number	Diff line number	Diff line
		@@ -26,10 +26,11 @@ module sens_hispi12l4#(
		parameter real REFCLK_FREQUENCY = 200.0,
		parameter HIGH_PERFORMANCE_MODE = "FALSE",
		parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
		parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

		parameter CLKFBOUT_MULT_SENSOR = 4, // 220 MHz --> 880 MHz
		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
		parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
		parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
		parameter IPCLK_PHASE = 0.000,
		parameter IPCLK2X_PHASE = 0.000,
		@@ -51,19 +52,23 @@ module sens_hispi12l4#(
		parameter HISPI_IBUF_DELAY_VALUE = "0",
		parameter HISPI_IBUF_LOW_PWR = "TRUE",
		parameter HISPI_IFD_DELAY_VALUE = "AUTO",
		parameter HISPI_IOSTANDARD = "DEFAULT"
		parameter HISPI_IOSTANDARD = "DEFAULT",
		parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
		)(
		input pclk, // global clock input, pixel rate (220MHz for MT9F002)
		input prst,
		input prst, // reset @pclk (add sensor reset here)
		// I/O pads
		input [HISPI_NUMLANES-1:0] sns_dp,
		input [HISPI_NUMLANES-1:0] sns_dn,
		input sns_clkp,
		input sns_clkn,
		// output
		output reg [11:0] pxd_out,
		output reg vact_out,
		// output reg [11:0] pxd_out,
		output [11:0] pxd_out,
		// output reg vact_out,
		output hact_out,
		output sof, // @pclk
		output reg eof, // @pclk

		// delay control inputs
		input mclk,
		@@ -86,10 +91,15 @@ module sens_hispi12l4#(
		wire ipclk; // re-generated half HiSPi clock (165 MHz)
		wire ipclk2x;// re-generated HiSPi clock (330 MHz)
		wire [HISPI_NUMLANES * 4-1:0] sns_d;
		localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
		localparam FIFO_DEPTH = 4;
		reg [HISPI_KEEP_IRST-1:0] irst_r;
		wire irst = irst_r[0];

		sens_hispi_clock #(
		.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
		.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
		.SENS_BANDWIDTH (SENS_BANDWIDTH),
		.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
		.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
		.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
		.IPCLK_PHASE (IPCLK_PHASE),
		@@ -153,11 +163,6 @@ module sens_hispi12l4#(
		.dout (sns_d) // output[15:0]
		);

		localparam WAIT_ALL_LANES = 8; // number of output pixel cycles to wait after the earliest lane
		localparam FIFO_DEPTH = 4;

		reg [2:0] irst_r;
		wire irst = irst_r[2];


		wire [HISPI_NUMLANES * 12-1:0] hispi_aligned;
		@@ -188,12 +193,29 @@ module sens_hispi12l4#(
		wire hact_on;
		wire hact_off;
		reg ignore_embedded_ipclk;
		reg [1:0] vact_pclk;
		wire [11:0] pxd_out_pre = ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) \|
		({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) \|
		({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) \|
		({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]);



		assign hact_out = hact_r;
		assign sof = sof_pclk;

		// async reset
		always @ (posedge ipclk or posedge prst) begin
		if (prst) irst_r <= {HISPI_KEEP_IRST{1'b1}}; // HISPI_KEEP_IRST-1
		else irst_r <= irst_r >> 1;
		end



		always @(posedge ipclk) begin
		irst_r <= {irst_r[1:0], prst};
		// irst_r <= {irst_r[1:0], prst};

		if (irst \|\| (\|hispi_eof[i])) vact_ipclk <= 0; // extend output if hact active
		if (irst \|\| (\|hispi_eof)) vact_ipclk <= 0; // extend output if hact active
		else if (\|hispi_sof) vact_ipclk <= 1;

		ignore_embedded_ipclk <= ignore_embedded;
		@@ -212,25 +234,28 @@ module sens_hispi12l4#(

		rd_line_r <= rd_line;

		if (sol_pclk && !rd_line) good_lanes <= ~rd_run; // should be off before start
		if (sol_pclk && !rd_line) good_lanes <= ~rd_run_d; // should be off before start
		else if (sol_all_dly) good_lanes <= good_lanes & rd_run; // and now they should be on

		fifo_re_r <= fifo_re & rd_run; // when data out is ready, mask if not running

		// not using HISPI_NUMLANES here - fix? Will be 0 (not possible in hispi) when no data
		pxd_out <= ({12 {fifo_re_r[0]}} & fifo_out[0 * 12 +:12]) \|
		({12 {fifo_re_r[1]}} & fifo_out[1 * 12 +:12]) \|
		({12 {fifo_re_r[2]}} & fifo_out[2 * 12 +:12]) \|
		({12 {fifo_re_r[3]}} & fifo_out[3 * 12 +:12]);
		/* pxd_out <= ({12 {fifo_re_r[0] & rd_run[0]}} & fifo_out[0 * 12 +:12]) \|
		({12 {fifo_re_r[1] & rd_run[1]}} & fifo_out[1 * 12 +:12]) \|
		({12 {fifo_re_r[2] & rd_run[2]}} & fifo_out[2 * 12 +:12]) \|
		({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */

		if (prst) fifo_re <= 0;
		else if (sol_pclk \|\| (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
		else fifo_re <= fifo_re << 1;

		if (prst \|\| hact_off) hact_r <= 0;
		// if (prst \|\| (hact_off && (\|(good_lanes & ~rd_run)))) hact_r <= 0;
		if (prst \|\| (hact_off && (!rd_line \|\| (good_lanes[3] & ~rd_run[3])))) hact_r <= 0;
		else if (hact_on) hact_r <= 1;

		vact_out <= vact_pclk_strt [0] \|\| hact_r;
		vact_pclk <= {vact_pclk[0],vact_pclk_strt [0] \|\| hact_r};
		eof <= vact_pclk[1] && !vact_pclk[0];
		// vact_out <= vact_pclk_strt [0] \|\| hact_r;
		end

		dly_16 #(
		@@ -248,7 +273,10 @@ module sens_hispi12l4#(
		) dly_16_hact_on_i (
		.clk (pclk), // input
		.rst (1'b0), // input
		.dly (2), // input[3:0]
		// .dly (4'h2), // input[3:0]
		// .dly (4'h3), // input[3:0]
		// .dly (4'h1), // input[3:0]
		.dly (4'h2), // input[3:0]
		.din (sol_pclk), // input[0:0]
		.dout (hact_on) // output[0:0]
		);
		@@ -258,11 +286,25 @@ module sens_hispi12l4#(
		) dly_16_hact_off_i (
		.clk (pclk), // input
		.rst (1'b0), // input
		.dly (2), // input[3:0]
		// .dly (4'h2), // input[3:0]
		// .dly (4'h0), // input[3:0]
		// .dly (4'h1), // input[3:0]
		.dly (4'h2), // input[3:0]
		.din (fifo_re[HISPI_NUMLANES - 1]), // input[0:0]
		.dout (hact_off) // output[0:0]
		);

		dly_16 #(
		.WIDTH(12)
		) dly_16_pxd_out_i (
		.clk (pclk), // input
		.rst (1'b0), // input
		// .dly (4'h2), // input[3:0]
		// .dly (4'h0), // input[3:0]
		.dly (4'h1), // input[3:0]
		.din (pxd_out_pre), // input[0:0]
		.dout (pxd_out) // output[0:0]
		);

		generate
		genvar i;
		@@ -289,7 +331,7 @@ module sens_hispi12l4#(
		.ipclk (ipclk), // input
		.irst (irst), // input
		.we (hispi_dv[i]), // input
		.sol (hispi_sol[i] && (hispi_embed[i] \|\| !ignore_embedded_ipclk)), // input
		.sol (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
		.eol (hispi_eol[i]), // input
		.din (hispi_aligned[12*i +: 12]), // input[11:0]
		.pclk (pclk), // input

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