Testing hardware, added configurable lane mapping

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151110124146463.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151110124625814.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151111121710210.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

fpga_version.vh

@@ -31,7 +31,10 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  *******************************************************************************/
-    parameter FPGA_VERSION =          32'h0393006c; // will try debug for HiSPi.  xclk violated by -0.030, slices 15062 (76.65%)
+    parameter FPGA_VERSION =          32'h0393006e; // Trying lane switch again after bug fix, failing 1 in  ddr3_mclk -> ddr3_clk_div by  -0.023
+//    parameter FPGA_VERSION =          32'h0393006d; // -1 with lane switch - does not work
+//    parameter FPGA_VERSION =          32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
+//    parameter FPGA_VERSION =          32'h0393006c; // will try debug for HiSPi.  xclk violated by -0.030, slices 15062 (76.65%)
 //    parameter FPGA_VERSION =          32'h0393006b; // Correcting sensor external clock generation - was wrong division. xclk violated by 0.095 ns
 //    parameter FPGA_VERSION =          32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization x40..x60
 //    parameter FPGA_VERSION =          32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization

py393/x393_jpeg.py

@@ -819,24 +819,51 @@ class X393Jpeg(object):
 ff d9
 """        
 """
+#should be no MSB first (0x31c68400)
+
 cd /usr/local/verilog/; test_mcntrl.py @hargs
 measure_all "*DI"
 setup_all_sensors True None 0xf
+#compressor_control  all  None  None  None None None  3
+set_sensor_hispi_lanes 0 1 2 3 0
+compressor_control  all  None  None  None None None  2
+program_gamma all 0 0.57 0.04
 write_sensor_i2c  0 1 0 0x030600b4
 print_sensor_i2c 0 0x306 0xff 0x10 0
 print_sensor_i2c 0 0x303a 0xff 0x10 0
 print_sensor_i2c 0 0x301a 0xff 0x10 0
 print_sensor_i2c 0 0x31c6 0xff 0x10 0
-write_sensor_i2c  0 1 0 0x31c68402
-print_sensor_i2c 0 0x31c6 0xff 0x10 0
-write_sensor_i2c  0 1 0 0x301a001c
+write_sensor_i2c  0 1 0 0x31c68400
 print_sensor_i2c 0 0x31c6 0xff 0x10 0
+print_sensor_i2c 0 0x306e 0xff 0x10 0
+write_sensor_i2c  0 1 0 0x306e9280
+
 #test pattern - 100% color bars
-write_sensor_i2c  0 1 0 0x30700003
-#test pattern - fadiong color bars
+write_sensor_i2c  0 1 0 0x30700002
+#test pattern - fading color bars
 write_sensor_i2c  0 1 0 0x30700003
 print_sensor_i2c 0 0x3070 0xff 0x10 0
 
+#Exposure 0x800 lines
+write_sensor_i2c  0 1 0 0x30120800
+
+#default gain = 0xa, set red and blue (outdoors)
+write_sensor_i2c  0 1 0 0x3028000a
+write_sensor_i2c  0 1 0 0x302c000d
+write_sensor_i2c  0 1 0 0x302e0010
+
+#default gain = 0xa, set red and blue (indoors)
+write_sensor_i2c  0 1 0 0x3028000a
+write_sensor_i2c  0 1 0 0x302c000b
+write_sensor_i2c  0 1 0 0x302e0010
+
+write_sensor_i2c  0 1 0 0x301a001c
+print_sensor_i2c 0 0x31c6 0xff 0x10 0
+
+
+compressor_control 0 2
+jpeg_write  "img.jpeg" 0
+
 
 
 
@@ -1046,6 +1073,12 @@ root@elphel393:/sys/devices/amba.0/f8007100.ps7-xadc# cat /sys/devices/amba.0/f8
 
 write_sensor_i2c  0 1 0 0xff200000
 print_sensor_i2c 0 
+#set JP46
+compressor_control  all  None  None  None  2
+#JP4
+compressor_control  all  None  None  None  5
+#JPEG
+compressor_control  all  None  None  None  0
 
 
 

py393/x393_sens_cmprs.py

@@ -75,7 +75,8 @@ SENSOR_INTERFACES={SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0,   "iface"
                    SENSOR_INTERFACE_HISPI:    {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}}
 
 SENSOR_DEFAULTS= {SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100},
-                   SENSOR_INTERFACE_HISPI:   {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
+#                   SENSOR_INTERFACE_HISPI:   {"width":4608, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
+                   SENSOR_INTERFACE_HISPI:   {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100}}
 
 class X393SensCmprs(object):
     DRY_MODE =           True # True

py393/x393_sensor.py

@@ -635,14 +635,14 @@ class X393Sensor(object):
                     quadrants =  quadrants)
         reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
         self.x393_axi_tasks.write_control_register(reg_addr, data)
-
-    def set_sensor_io_dly (self,
-                           num_sensor,
-                           mmcm_phase,
-                           iclk_dly,
-                           vact_dly,
-                           hact_dly,
-                           pxd_dly):
+# TODO: Make one for HiSPi (it is different)
+    def set_sensor_io_dly_parallel (self,
+                                    num_sensor,
+                                    mmcm_phase,
+                                    iclk_dly,
+                                    vact_dly,
+                                    hact_dly,
+                                    pxd_dly):
         """
         Set sensor port input delays and mmcm phase
         @param num_sensor - sensor port number (0..3)
@@ -663,6 +663,24 @@ class X393Sensor(object):
         self.x393_axi_tasks.write_control_register(reg_addr + 3, dlys[3]) # {mmcm_phase, bpf,   vact, hact}
         self.set_sensor_io_ctl (num_sensor = num_sensor,
                                 set_delays = True)
+        
+    def set_sensor_hispi_lanes(self,
+                               num_sensor,
+                               lane0 = 0,
+                               lane1 = 1,
+                               lane2 = 2,
+                               lane3 = 3):
+        """
+        Set HiSPi sensor lane map (physical lane for each logical lane)
+        @param num_sensor - sensor port number (0..3)
+        @param lane0 - physical (input) lane number for logical (internal) lane 0
+        @param lane1 - physical (input) lane number for logical (internal) lane 1
+        @param lane2 - physical (input) lane number for logical (internal) lane 2
+        @param lane3 - physical (input) lane number for logical (internal) lane 3
+        """
+        data = ((lane0 & 3) << 0 ) | ((lane1 & 3) << 2 ) | ((lane2 & 3) << 4 ) | ((lane3 & 3) << 6 )
+        reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS;
+        self.x393_axi_tasks.write_control_register(reg_addr + 1, data)
 
     def set_sensor_io_jtag (self,
                             num_sensor,

sensor/sens_10398.v

@@ -41,7 +41,7 @@ module  sens_10398 #(
     parameter SENSIO_JTAG =        'h2,
 //    parameter SENSIO_WIDTH =       'h3, // set line width (1.. 2^16) if 0 - use HACT
     parameter SENSIO_DELAYS =      'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
-// 6 - delays, 7 - phase
+// 5, swap lanes 6 - delays, 7 - phase
     parameter SENSIO_STATUS_REG =  'h21,
 
     parameter SENS_JTAG_PGMEN =    8,
@@ -157,7 +157,7 @@ module  sens_10398 #(
     
     reg  [31:0] data_r; 
 //    reg   [3:0] set_idelay;
-
+    reg         set_lanes_map; // set sequence of lanes im the composite pixel line
     reg         set_idelays;    
     reg         set_iclk_phase;
     reg         set_ctrl_r;
@@ -213,6 +213,9 @@ module  sens_10398 #(
         if      (mrst)     data_r <= 0;
         else if (cmd_we)   data_r <= cmd_data;
         
+        if      (mrst) set_lanes_map <= 0;
+        else           set_lanes_map <=  cmd_we & (cmd_a==(SENSIO_DELAYS+1));
+
         if      (mrst) set_idelays <= 0;
         else           set_idelays <=  cmd_we & (cmd_a==(SENSIO_DELAYS+2));
                                              
@@ -362,7 +365,8 @@ module  sens_10398 #(
         .eof                    (eof),                    // output reg 
         .mclk                   (mclk),                   // input
         .mrst                   (mrst),                   // input
-        .dly_data               (data_r),                 // input[31:0] 
+        .dly_data               (data_r),                 // input[31:0]
+        .set_lanes_map          (set_lanes_map),          // input[3:0] 
         .set_idelay             ({4{set_idelays}}),       // input[3:0] 
         .ld_idelay              (ld_idelay),              // input
         .set_clk_phase          (set_iclk_phase),         // input

sensor/sens_hispi12l4.v

@@ -57,6 +57,7 @@ module  sens_hispi12l4#(
     parameter SENS_SS_MODE       =        "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
     parameter SENS_SS_MOD_PERIOD =         10000,        // integer 4000-40000 - SS modulation period in ns
 
+    parameter DEFAULT_LANE_MAP =           8'b11100100, // one-to-one map (or make it 8'b00111001 ?)
     parameter HISPI_MSB_FIRST =            0,
     parameter HISPI_NUMLANES =             4,
     parameter HISPI_DELAY_CLK =           "FALSE",      
@@ -89,6 +90,7 @@ module  sens_hispi12l4#(
     input                           mclk,
     input                           mrst,
     input  [HISPI_NUMLANES * 8-1:0] dly_data,        // delay value (3 LSB - fine delay) - @posedge mclk
+    input                           set_lanes_map,   // set number of physical lane for each logical one
     input      [HISPI_NUMLANES-1:0] set_idelay,      // mclk synchronous load idelay value
     input                           ld_idelay,       // mclk synchronous set idealy value
     input                           set_clk_phase,   // mclk synchronous set idealy value
@@ -109,7 +111,22 @@ module  sens_hispi12l4#(
     localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
     localparam FIFO_DEPTH = 4;
     reg      [HISPI_KEEP_IRST-1:0] irst_r;
-    wire                         irst = irst_r[0];
+    wire                          irst = irst_r[0];
+    reg  [HISPI_NUMLANES * 2-1:0] lanes_map;
+    reg  [HISPI_NUMLANES * 4-1:0] logical_lanes4;                   
+    always @ (posedge mclk) begin
+        if      (mrst)          lanes_map <= DEFAULT_LANE_MAP; //{2'h3,2'h2,2'h1,2'h0}; // 1-to-1 default map
+        else if (set_lanes_map) lanes_map <= dly_data[HISPI_NUMLANES * 2-1:0];
+    end
+    
+//non-parametrized lane switch (4x4)
+    always  @(posedge ipclk) begin
+        logical_lanes4[ 3: 0] <= sns_d[{lanes_map[1:0],2'b0} +:4];
+        logical_lanes4[ 7: 4] <= sns_d[{lanes_map[3:2],2'b0} +:4];
+        logical_lanes4[11: 8] <= sns_d[{lanes_map[5:4],2'b0} +:4];
+        logical_lanes4[15:12] <= sns_d[{lanes_map[7:6],2'b0} +:4];
+    end   
+    
     
     sens_hispi_clock #(
         .SENS_PHASE_WIDTH       (SENS_PHASE_WIDTH),
@@ -182,8 +199,13 @@ module  sens_hispi12l4#(
         .ipclk        (ipclk), // input
         .ipclk2x      (ipclk2x), // input
         .irst         (irst), // input
+//`ifdef REVERSE_LANES
+//        .din_p        ({sns_dp[0],sns_dp[1],sns_dp[2],sns_dp[3]}), // input[3:0] 
+//        .din_n        ({sns_dn[0],sns_dn[1],sns_dn[2],sns_dn[3]}), // input[3:0] 
+//`else
         .din_p        (sns_dp), // input[3:0] 
         .din_n        (sns_dn), // input[3:0] 
+//`endif        
         .dout         (sns_d) // output[15:0] 
     );
     
@@ -339,7 +361,7 @@ module  sens_hispi12l4#(
             ) sens_hispi_lane_i (
                 .ipclk    (ipclk),                     // input
                 .irst     (irst),                      // input
-                .din      (sns_d[4*i +: 4]),           // input[3:0] 
+                .din      (logical_lanes4[4*i +: 4]),           // input[3:0] 
                 .dout     (hispi_aligned[12*i +: 12]), // output[3:0] reg 
                 .dv       (hispi_dv[i]),               // output reg 
                 .embed    (hispi_embed[i]),            // output reg 

system_defines.vh

@@ -41,6 +41,7 @@
 //    `define USE_OLD_XDCT393  
 //  `define USE_PCLK2X
 //  `define USE_XCLK2X
+  `define REVERSE_LANES 1
   `define DEBUG_RING 1
 //  `define MCLK_VCO_MULT 16
 // DDR3 memory speed grade and density