working on files realted to sensor channels, added frame sequences to...

working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v

cmd_readback.v

+/*******************************************************************************
+ * Module: cmd_readback
+ * Date:2015-05-05  
+ * Author: andrey     
+ * Description: Store control register data and readback
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * cmd_readback.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  cmd_readback.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  cmd_readback#(
+    parameter AXI_WR_ADDR_BITS=              14,
+    parameter AXI_RD_ADDR_BITS =             14,
+    parameter CONTROL_RBACK_DEPTH=           10, // 
+    
+    parameter CONTROL_ADDR =             'h2000,  // AXI write address of control write registers
+    parameter CONTROL_ADDR_MASK =        'h3c00,  // AXI write address of control registers
+    parameter CONTROL_RBACK_ADDR =       'h2000,  // AXI write address of control write registers
+    parameter CONTROL_RBACK_ADDR_MASK =  'h3c00   // AXI write address of control registers
+)(
+    input                            rst,
+    input                            mclk,
+    input                            axi_clk,
+    input     [AXI_WR_ADDR_BITS-1:0] par_waddr,     // parallel address
+    input                     [31:0] par_data,      // parallel 32-bit data
+    input                            ad_stb,        // low address output strobe (and parallel A/D)
+    
+    input    [AXI_RD_ADDR_BITS-1:0] axird_pre_araddr,  // status read address, 1 cycle ahead of read data
+    input                           axird_start_burst, // start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer
+    input [CONTROL_RBACK_DEPTH-1:0] axird_raddr,       //   .raddr(read_in_progress?read_address[9:0]:10'h3ff),    // read address
+    input                           axird_ren,         //      .ren(bram_reg_re_w) ,      // read port enable
+//    input                        axird_regen,       //==axird_ren?? - remove?   .regen(bram_reg_re_w),        // output register enable
+    output                 [31:0]   axird_rdata,       // combinatorial multiplexed (add external register layer, modify axibram_read?)     .data_out(rdata[31:0]),       // data out
+    output                          axird_selected    // axird_rdata contains cvalid data from this module, vcalid next after axird_start_burst
+
+);
+    localparam integer DATA_2DEPTH = (1<<CONTROL_RBACK_DEPTH)-1;
+    reg  [31:0] ram [0:DATA_2DEPTH];
+    reg  [CONTROL_RBACK_DEPTH-1:0] waddr;
+    reg                            we;
+    reg                    [31: 0] wdata;
+    
+    wire                           select_w;
+    reg                            select_r;
+    reg                            select_d;
+    
+    wire                           rd;
+    wire                           regen;
+    reg                   [31:0]   axi_rback_rdata; 
+    reg                   [31:0]   axi_rback_rdata_r;
+    reg                            axird_regen;
+    wire                           we_w;
+    
+    assign we_w = ad_stb && (((par_waddr ^ CONTROL_ADDR) & CONTROL_ADDR_MASK)==0);
+    assign select_w = ((axird_pre_araddr ^ CONTROL_RBACK_ADDR) & CONTROL_RBACK_ADDR_MASK)==0;
+    assign rd =        axird_ren   && select_r;
+    assign regen =     axird_regen && select_d;
+    assign axird_rdata=axi_rback_rdata_r;
+    assign axird_selected = select_r; 
+    
+    
+    always @ (posedge rst or posedge axi_clk) begin
+        if (rst) axird_regen <= 0;
+        else    axird_regen <= axird_ren;
+        
+        if      (rst)               select_r <= 0;
+        else if (axird_start_burst) select_r <= select_w;
+    
+    end
+    always @ (posedge axi_clk) begin
+        if (rd)       axi_rback_rdata <= ram[axird_raddr];
+        if (regen)    axi_rback_rdata_r <= axi_rback_rdata;
+        select_d <=   select_r;
+    end
+    
+    always @ (posedge rst or posedge mclk) begin
+        if (rst) we <= 0;
+        else     we <= we_w;
+    end
+    always @ (posedge mclk) begin
+        if (we_w) wdata <= par_data;
+        if (we_w) waddr <= par_waddr[CONTROL_RBACK_DEPTH-1:0];
+        
+    end
+
+    always @ (posedge mclk) begin
+        if (we)     ram[waddr]  <= wdata; // shifted data here
+    end
+    
+
+endmodule
+

memctrl/cmd_encod_tiled_32_rd.v

@@ -36,7 +36,7 @@ TODO: Maybe allow less rows with different sequence (no autoprecharge/no activat
 number fo rows>1!
 
 Known issues:
-1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid)
+1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid - wrong - that was for tile16 mode)
 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width
  is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and
  frame full width? Seems easy to fix

memctrl/cmd_encod_tiled_32_wr.v

@@ -36,7 +36,7 @@ TODO: Maybe allow less rows with different sequence (no autoprecharge/no activat
 number fo rows>1!
 
 Known issues:
-1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid)
+1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid- wrong - that was for tile16 mode)
 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width
  is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and
  frame full width? Seems easy to fix

sensor/sens_parallel12.v

+/*******************************************************************************
+ * Module: sens_parallel12
+ * Date:2015-05-10  
+ * Author: andrey     
+ * Description: Sensor interface with 12-bit for parallel bus
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * sens_parallel12.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  sens_parallel12.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  sens_parallel12 (
+    input         rst,
+    input         pclk, // global clock input, pixel rate (96MHz for MT9P006)
+    input         pclk2x, // maybe not needed here
+    // sensor pads excluding i2c
+    input         vact,
+    input         hact, //output in fillfactory mode
+    inout         bpf,  // output in fillfactory mode
+    inout  [11:0] pxd, //actually only 2 LSBs are inouts
+    inout         mrst,
+    output        arst,
+    output        aro,
+    // output
+    output [15:0] ipxd,
+    output        vacts, 
+    
+    
+    // programming interface
+    input         mclk,     // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
+    input   [7:0] cmd_ad,      // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 
+    input         cmd_stb,     // strobe (with first byte) for the command a/d
+    output  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
+    output        status_rq,   // input request to send status downstream
+    input         status_start // Acknowledge of the first status packet byte (address)
+);
+
+
+endmodule
+

sensor/sensor_channel.v

+/*******************************************************************************
+ * Module: sensor_channel
+ * Date:2015-05-10  
+ * Author: andrey     
+ * Description: Top module for a sensor channel
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * sensor_channel.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  sensor_channel.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  sensor_channel#(
+    parameter SENSI2C_ABS_ADDR =    'h300,
+    parameter SENSI2C_REL_ADDR =    'h310,
+    parameter SENSI2C_ADDR_MASK =   'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
+    parameter SENSI2C_CTRL_ADDR =   'h320,
+    parameter SENSI2C_CTRL_MASK =   'h3fe,
+    parameter SENSI2C_CTRL =        'h0,
+    parameter SENSI2C_STATUS =      'h1,
+    parameter SENSI2C_STATUS_REG =  'h30,
+    parameter integer DRIVE = 12,
+    parameter IBUF_LOW_PWR = "TRUE",
+    parameter IOSTANDARD = "DEFAULT",
+`ifdef XIL_TIMING
+    parameter LOC = " UNPLACED",
+`endif
+    parameter SLEW = "SLOW"
+) (
+    input rst,
+    input pclk, // global clock input, pixel rate (96MHz for MT9P006)
+    // I/O pads, pin names match circuit diagram
+    inout [7:0] sns_dp,
+    inout [7:0] sns_dn,
+    inout       sns_clkp,
+    inout       sns_scl,
+    inout       sns_sda,
+    inout       sns_ctl,
+    inout       sns_pg,
+    // programming interface
+    input        mclk,     // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
+    input   [7:0] cmd_ad,      // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 
+    input         cmd_stb,     // strobe (with first byte) for the command a/d
+    output  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
+    output        status_rq,   // input request to send status downstream
+    input         status_start // Acknowledge of the first status packet byte (address)
+// (much) more will be added later    
+    
+);
+    sensor_i2c_io #(
+        .SENSI2C_ABS_ADDR(SENSI2C_ABS_ADDR),
+        .SENSI2C_REL_ADDR(SENSI2C_REL_ADDR),
+        .SENSI2C_ADDR_MASK(SENSI2C_ADDR_MASK),
+        .SENSI2C_CTRL_ADDR(SENSI2C_CTRL_ADDR),
+        .SENSI2C_CTRL_MASK(SENSI2C_CTRL_MASK),
+        .SENSI2C_CTRL(SENSI2C_CTRL),
+        .SENSI2C_STATUS(SENSI2C_STATUS),
+        .SENSI2C_STATUS_REG(SENSI2C_STATUS_REG),
+        .SENSI2C_DRIVE(SENSI2C_DRIVE),
+        .SENSI2C_IBUF_LOW_PWR(SENSI2C_IBUF_LOW_PWR),
+        .SENSI2C_IOSTANDARD(SENSI2C_IOSTANDARD),
+        .SENSI2C_SLEW(SENSI2C_SLEW)
+    ) sensor_i2c_io_i (
+        .rst(), // input
+        .mclk(), // input
+        .cmd_ad(), // input[7:0] 
+        .cmd_stb(), // input
+        .status_ad(), // output[7:0] 
+        .status_rq(), // output
+        .status_start(), // input
+        .frame_sync(), // input
+        .scl(), // inout
+        .sda() // inout
+    );
+
+
+endmodule
+

sensor/sensor_i2c_io.v

+/*******************************************************************************
+ * Module: sensor_i2c_io
+ * Date:2015-05-15  
+ * Author: andrey     
+ * Description: sensor_i2c with I/O pad elements
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * sensor_i2c_io.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  sensor_i2c_io.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  sensor_i2c_io#(
+    parameter SENSI2C_ABS_ADDR =    'h300,
+    parameter SENSI2C_REL_ADDR =    'h310,
+    parameter SENSI2C_ADDR_MASK =   'h3f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
+    parameter SENSI2C_CTRL_ADDR =   'h320,
+    parameter SENSI2C_CTRL_MASK =   'h3fe,
+    parameter SENSI2C_CTRL =        'h0,
+    parameter SENSI2C_STATUS =      'h1,
+    parameter SENSI2C_STATUS_REG =  'h30,
+    parameter integer SENSI2C_DRIVE = 12,
+    parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
+    parameter SENSI2C_IOSTANDARD = "DEFAULT",
+    parameter SENSI2C_SLEW = "SLOW"
+)(
+    input         rst,
+    input         mclk,         // global clock, half DDR3 clock, synchronizes all I/O thorough the command port
+    input   [7:0] cmd_ad,       // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 
+    input         cmd_stb,      // strobe (with first byte) for the command a/d
+    output  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
+    output        status_rq,   // input request to send status downstream
+    input         status_start,// Acknowledge of the first status packet byte (address)
+    input         frame_sync,  // increment/reset frame number
+    inout         scl,
+    inout         sda
+);
+        wire scl_in;
+        wire sda_in;
+        wire scl_out;
+        wire sda_out;
+        wire scl_en;
+        wire sda_en;
+
+    sensor_i2c #(
+        .SENSI2C_ABS_ADDR(SENSI2C_ABS_ADDR),
+        .SENSI2C_REL_ADDR(SENSI2C_REL_ADDR),
+        .SENSI2C_ADDR_MASK(SENSI2C_ADDR_MASK),
+        .SENSI2C_CTRL_ADDR(SENSI2C_CTRL_ADDR),
+        .SENSI2C_CTRL_MASK(SENSI2C_CTRL_MASK),
+        .SENSI2C_CTRL(SENSI2C_CTRL),
+        .SENSI2C_STATUS(SENSI2C_STATUS),
+        .SENSI2C_STATUS_REG(SENSI2C_STATUS_REG)
+    ) sensor_i2c_i (
+        .rst(rst), // input
+        .mclk(mclk), // input
+        .cmd_ad(cmd_ad), // input[7:0] 
+        .cmd_stb(cmd_stb), // input
+        .status_ad(status_ad), // output[7:0] 
+        .status_rq(status_rq), // output
+        .status_start(status_start), // input
+        .frame_sync(frame_sync), // input
+        .scl_in(scl_in), // input
+        .sda_in(sda_in), // input
+        .scl_out(scl_out), // output
+        .sda_out(sda_out), // output
+        .scl_en(scl_en), // output
+        .sda_en(sda_en) // output
+    );
+
+    iobuf #(
+        .DRIVE        (SENSI2C_DRIVE),
+        .IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
+        .IOSTANDARD   (SENSI2C_IOSTANDARD),
+        .SLEW         (SENSI2C_SLEW)
+    ) iobuf_scl_i (
+        .O     (scl_in), // output
+        .IO    (scl), // inout
+        .I     (scl_out), // input
+        .T     (!scl_en) // input
+    );
+
+    iobuf #(
+        .DRIVE        (SENSI2C_DRIVE),
+        .IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
+        .IOSTANDARD   (SENSI2C_IOSTANDARD),
+        .SLEW         (SENSI2C_SLEW)
+    ) iobuf_sda_i (
+        .O     (sda_in), // output
+        .IO    (sda), // inout
+        .I     (sda_out), // input
+        .T     (!sda_en) // input
+    );
+
+endmodule
+

wrap/iobuf.v

+/*******************************************************************************
+ * Module: iobuf
+ * Date:2015-05-15  
+ * Author: andrey     
+ * Description: Wrapper for IOBUF primitive
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * iobuf.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  iobuf.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  iobuf#(
+    parameter integer DRIVE = 12,
+    parameter IBUF_LOW_PWR = "TRUE",
+    parameter IOSTANDARD = "DEFAULT",
+`ifdef XIL_TIMING
+    parameter LOC = " UNPLACED",
+`endif
+    parameter SLEW = "SLOW"
+)(
+    output O,
+    inout  IO,
+    input  I,
+    input  T
+);
+
+    IOBUF #(
+        .DRIVE        (DRIVE),
+        .IBUF_LOW_PWR (IBUF_LOW_PWR),
+        .IOSTANDARD   (IOSTANDARD),
+        .SLEW         (SLEW)
+    ) IOBUF_i (
+        .O  (O), // output 
+        .IO (IO), // inout 
+        .I  (I), // input 
+        .T  (T) // input 
+    );
+endmodule
+