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Commit 69ef600d authored by Andrey Filippov's avatar Andrey Filippov
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merged with framepars - code for dct-iv

parents 26dad413 a409d2b4
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.gitignore
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...@@ -16,6 +16,7 @@ x393.prj ...@@ -16,6 +16,7 @@ x393.prj
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/*!
* <b>Module:</b>dct_iv8_1d
* @file dct_iv8_1d.v
* @date 2016-12-02
* @author Andrey Filippov
*
* @brief 1d 8-point DCT type IV for lapped mdct 16->8, operates in 16 clock cycles
* Uses 2 DSP blocks
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*dct_iv8_1d.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_iv8_1d.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
module dct_iv8_1d#(
parameter WIDTH = 24, // input data width
parameter OUT_WIDTH = 24, // 16, // output deata width
parameter OUT_RSHIFT = 3, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
parameter P_WIDTH = 48,
parameter COSINE_SHIFT= 17,
parameter COS_01_32 = 130441, // int(round((1<<17) * cos( 1*pi/32)))
parameter COS_03_32 = 125428, // int(round((1<<17) * cos( 3*pi/32)))
parameter COS_04_32 = 121095, // int(round((1<<17) * cos( 4*pi/32)))
parameter COS_05_32 = 115595, // int(round((1<<17) * cos( 5*pi/32)))
parameter COS_07_32 = 101320, // int(round((1<<17) * cos( 7*pi/32)))
parameter COS_08_32 = 92682, // int(round((1<<17) * cos( 8*pi/32)))
parameter COS_09_32 = 83151, // int(round((1<<17) * cos( 9*pi/32)))
parameter COS_11_32 = 61787, // int(round((1<<17) * cos(11*pi/32)))
parameter COS_12_32 = 50159, // int(round((1<<17) * cos(12*pi/32)))
parameter COS_13_32 = 38048, // int(round((1<<17) * cos(13*pi/32)))
parameter COS_15_32 = 12847 // int(round((1<<17) * cos(15*pi/32)))
)(
input clk,
input rst,
input en,
input [WIDTH -1:0] d_in, // X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
input start, // one cycle before first X6 input
output [OUT_WIDTH -1:0] dout,
output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
// start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
output reg en_out // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
);
// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
localparam RSHIFT1 = 2; // safe right shift for stage 1
localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates
localparam STAGE2_RSHIFT = COSINE_SHIFT + (A_WIDTH - OUT_WIDTH) +(OUT_RSHIFT-RSHIFT1); // divide by 4 in stage 1 - never saturates
// STAGE2_RSHIFT should be >0 ( >=1 ) for rounding
// register files on the D-inputs of DSPs
reg signed [A_WIDTH-1:0] dsp_din_1_ram[0:1] ; // just two registers
reg signed [A_WIDTH-1:0] dsp_din_2_ram[0:3] ; // 4 registers registers
reg dsp_din_1_wa;
reg dsp_din_1_ra;
reg dsp_din_1_we;
reg dsp_din_2_we;
reg [1:0] dsp_din_2_wa;
reg [1:0] dsp_din_2_ra;
reg signed [B_WIDTH-1:0] dsp_bin;
reg dsp_ceb1_1; // load b1 register
reg dsp_ceb2_1; // load b2 register
reg dsp_selb_1; // 0 - select b1, 1 - select b2
wire signed [A_WIDTH-1:0] dsp_ain_1;
reg dsp_cea1_1;
reg dsp_cea2_1;
wire signed [A_WIDTH-1:0] dsp_din_1;
reg dsp_ced_1;
reg dsp_sela_1;
// reg dsp_en_a_1; // Not used here 0: +/- D, 1: A or A +/- D
// reg dsp_en_d_1; // Not used here 0: A, 1: D or A +/- D
reg dsp_sub_a_1; //
reg dsp_neg_m_1; // 1 - negate multiplier result
reg dsp_accum_1; // 0 - use multiplier result, 1 add to accumulator
wire signed [P_WIDTH-1:0] dsp_cin_1;
reg dsp_cec_1;
reg dsp_post_add_1; // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
wire signed [P_WIDTH-1:0] dsp_p_1;
reg dsp_ceb1_2; // load b1 register
reg dsp_ceb2_2; // load b2 register
reg dsp_selb_2; // 0 - select b1, 1 - select b2
wire signed [A_WIDTH-1:0] dsp_ain_2;
reg dsp_cea1_2;
reg dsp_cea2_2;
wire signed [A_WIDTH-1:0] dsp_din_2;
reg dsp_sela_2; // 0 - select a1, 1 - select a2
reg dsp_sub_a_2; //
reg dsp_neg_m_2; // 1 - negate multiplier result
reg dsp_accum_2; // 0 - use multiplier result, 1 add to accumulator
wire signed [P_WIDTH-1:0] dsp_p_2;
reg [3:0] phase_cnt;
reg run_in; // receiving input data
reg restart; // restarting next block if en was active at phase=14;
reg run_out; // running output data
assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
assign dout = dsp_p_2 [STAGE2_RSHIFT +: OUT_WIDTH]; // dout_r;
generate
if (A_WIDTH > WIDTH) assign dsp_ain_1 = {{A_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
else assign dsp_ain_1 = d_in; // SuppressThisWarning VEditor (not implemented)
endgenerate
// assign dsp_cin_1 = {{P_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
// symmetrically lshift by COSINE_SHIFT (match multiplication by 1.0), add 0.5LSB for positive, subtract 0.5LSB for negative
wire din_zero = ~(|d_in);
assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};
//register files
assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
assign dsp_din_2 = dsp_din_2_ram[dsp_din_2_ra];
always @ (posedge clk) begin
if (dsp_din_1_we) dsp_din_1_ram[dsp_din_1_wa] <= dsp_ain_1;
if (dsp_din_2_we) dsp_din_2_ram[dsp_din_2_wa] <= dsp_ain_2;
end
always @ (posedge clk) begin
if (rst) restart <= 0;
else restart <= (phase_cnt == 14) && en;
if (rst) run_in <= 0;
else if (start || restart) run_in <= 1;
else if (phase_cnt==15) run_in <= 0;
if (rst) run_out <= 0;
else if (phase_cnt == 13) run_out <= run_in;
if (rst || (!run_in && !run_out)) phase_cnt <= 0;
else phase_cnt <= phase_cnt + 1;
pre2_start_out <= run_out && (phase_cnt == 14);
en_out <= run_out && !phase_cnt[0];
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
case (phase_cnt)
4'h0: dsp_bin <= COS_09_32;
4'h1: dsp_bin <= COS_04_32;
4'h2: dsp_bin <= COS_08_32;
4'h3: dsp_bin <= COS_03_32;
4'h4: dsp_bin <= COS_13_32;
4'h5: dsp_bin <= COS_12_32;
4'h6: dsp_bin <= 'bx;
4'h7: dsp_bin <= COS_05_32;
4'h8: dsp_bin <= COS_11_32;
4'h9: dsp_bin <= 'bx;
4'ha: dsp_bin <= COS_08_32;
4'hb: dsp_bin <= COS_15_32;
4'hc: dsp_bin <= COS_01_32;
4'hd: dsp_bin <= COS_12_32;
4'he: dsp_bin <= 'bx;
4'hf: dsp_bin <= COS_07_32;
endcase
end
// Control signals for each phase
wire p00 = (phase_cnt[3:0] == 0) && (run_in || run_out);
wire p01 = phase_cnt[3:0] == 1;
wire p02 = phase_cnt[3:0] == 2;
wire p03 = phase_cnt[3:0] == 3;
wire p04 = phase_cnt[3:0] == 4;
wire p05 = phase_cnt[3:0] == 5;
wire p06 = phase_cnt[3:0] == 6;
wire p07 = phase_cnt[3:0] == 7;
wire p08 = phase_cnt[3:0] == 8;
wire p09 = phase_cnt[3:0] == 9;
wire p10 = phase_cnt[3:0] == 10;
wire p11 = phase_cnt[3:0] == 11;
wire p12 = phase_cnt[3:0] == 12;
wire p13 = phase_cnt[3:0] == 13;
wire p14 = phase_cnt[3:0] == 14;
wire p15 = phase_cnt[3:0] == 15;
always @ (posedge clk) begin
// p00 | p01 | p02 | p03 | p04 | p05 | p06 | p07 | p08 | p09 | p10 | p11 | p12 | p13 | p14 | p15 ;
dsp_din_1_we <= p01 | p03 | p08 | p09 | p15 | start;
dsp_din_1_wa <= p15 | start;
dsp_din_1_ra <= p06 | p14 ;
dsp_cea1_1 <= p06 ;
dsp_cea2_1 <= p02 | p04 | p10 | p12 ;
dsp_ced_1 <= p00 | p02 | p05 | p06 | p08 | p09 | p13 | p14 ;
dsp_sela_1 <= p00 | p01 | p02 | p03 | p04 | p05 | p08 | p10 | p11 | p13 ;
dsp_sub_a_1 <= p00 | p01 | p02 | p04 | p05 | p06 | p11 | p15 ;
dsp_ceb1_1 <= p01 ;
dsp_ceb2_1 <= p02 | p05 | p10 | p13 ;
dsp_selb_1 <= p01 | p02 | p03 | p04 | p07 | p09 | p10 | p11 | p12 | p15 ;
dsp_cec_1 <= p00 | p05 | p13 ;
dsp_neg_m_1 <= p00 | p01 | p02 | p08 | p11 | p12 | p13 ;
dsp_accum_1 <= p00 | p02 | p08 | p10 ;
dsp_post_add_1 <= p04 | p05 | p12 | p13 ;
dsp_din_2_we <= | p06 | p07 | p14 | p15 ;
dsp_din_2_wa[0] <= p06 | p15 ;
dsp_din_2_wa[1] <= p14 | p15 ;
dsp_din_2_ra[0] <= p01 | p04 | p06 | p08 | p10 | p11 | p13 | p15 ;
dsp_din_2_ra[1] <= p03 | p04 | p05 | p06 | p07 | p08 | p09 | p10 ;
dsp_cea1_2 <= p02 | p10 ;
dsp_cea2_2 <= p04 | p12 ;
dsp_sela_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ; //~phase[0]
dsp_sub_a_2 <= p00 | p01 | p02 | p03 | p04 | p05 | p06 | p15 ;
dsp_ceb1_2 <= p00 | p03 | p08 | p11 ;
dsp_ceb2_2 <= p04 | p07 | p12 | p15 ;
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
dsp_neg_m_2 <= p03 | p06 | p12 | p15 ; //~phase[0]
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end
dsp_ma_preadd_c #(
.B_WIDTH (B_WIDTH),
.A_WIDTH (A_WIDTH),
.P_WIDTH (P_WIDTH)
) dsp_ma_preadd_c_1_i (
.clk (clk), // input
.rst (rst), // input
.bin (dsp_bin), // input[17:0] signed
.ceb1 (dsp_ceb1_1), // input
.ceb2 (dsp_ceb2_1), // input
.selb (dsp_selb_1), // input
.ain (dsp_ain_1), // input[24:0] signed
.cea1 (dsp_cea1_1), // input
.cea2 (dsp_cea2_1), // input
.din (dsp_din_1), // input[24:0] signed
.ced (dsp_ced_1), // input
.cin (dsp_cin_1), // input[47:0] signed
.cec (dsp_cec_1), // input
.cead (1'b1), // input
.sela (dsp_sela_1), // input
.en_a (1'b1), // input
.en_d (1'b1), // input
.sub_a (dsp_sub_a_1), // input
.neg_m (dsp_neg_m_1), // input
.accum (dsp_accum_1), // input
.post_add (dsp_post_add_1), // input
.pout (dsp_p_1) // output[47:0] signed
);
dsp_ma_preadd_c #(
.B_WIDTH (B_WIDTH),
.A_WIDTH (A_WIDTH),
.P_WIDTH (P_WIDTH)
) dsp_ma_preadd_c_2_i (
.clk (clk), // input
.rst (rst), // input
.bin (dsp_bin), // input[17:0] signed
.ceb1 (dsp_ceb1_2), // input
.ceb2 (dsp_ceb2_2), // input
.selb (dsp_selb_2), // input
.ain (dsp_ain_2), // input[24:0] signed
.cea1 (dsp_cea1_2), // input
.cea2 (dsp_cea2_2), // input
.din (dsp_din_2), // input[24:0] signed
.ced (1'b1), // input
.cin ({P_WIDTH{1'b1}}),// input[47:0] signed
.cec (1'b0), // input
.cead (1'b1), // input
.sela (dsp_sela_2), // input
.en_a (1'b1), // input
.en_d (1'b1), // input
.sub_a (dsp_sub_a_2), // input
.neg_m (dsp_neg_m_2), // input
.accum (dsp_accum_2), // input
.post_add (1'b0), // input
.pout (dsp_p_2) // output[47:0] signed
);
endmodule
dsp/dct_tests_01.tf 0 → 100644
View file @ 69ef600d
/*!
* <b>Module:</b>dct_tests_01
* @file dct_tests_01.tf
* @date 2016-12-02
* @author Andrey Filippov
*
* @brief 1d 8-point DCT type IV for lapped mdct 16->8, operates in 16 clock cycles
* Uses 2 DSP blocks
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*dct_tests_01.tf is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_tests_01.tf is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
// No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
// will reduce needed resources
//`define DCT_INPUT_UNITY
module dct_tests_01 ();
// parameter fstname="dct_tests_01.fst";
`ifdef IVERILOG
`ifdef NON_VDT_ENVIROMENT
parameter fstname="dct_tests_01.fst";
`else
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else // IVERILOG
`ifdef CVC
`ifdef NON_VDT_ENVIROMENT
parameter fstname = "x393.fst";
`else // NON_VDT_ENVIROMENT
`include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else
parameter fstname = "dct_tests_01.fst";
`endif // CVC
`endif // IVERILOG
parameter CLK_PERIOD = 10; // ns
parameter WIDTH = 24; // input data width
// parameter OUT_WIDTH = 16; // output data width
parameter OUT_WIDTH = 24; // output data width
parameter OUT_RSHIFT = 3; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
reg RST = 1'b1;
reg CLK = 1'b0;
reg [3:0] phase_in;
reg [3:0] phase_out;
reg run_in;
reg run_out;
reg run_out_d;
reg en_x = 0;
// reg end_x = 0;
reg [2:0] x_ra;
wire [2:0] x_wa = phase_in[2:0];
wire x_we = !phase_in[3] && run_in;
reg [WIDTH-1:0] x_in;
reg [WIDTH-1:0] x_out;
reg [WIDTH-1:0] x_ram[0:7];
wire [WIDTH-1:0] x_out_w = x_ram[x_ra];
reg start = 0;
wire [OUT_WIDTH-1:0] y_dct; // S uppressThisWarning VEditor - simulation only
wire pre2_start_out; // S uppressThisWarning VEditor - simulation only
wire en_out; // S uppressThisWarning VEditor - simulation only
reg y_pre_we;
reg y_we;
reg [3:0] phase_y=8;
reg [2:0] y_wa;
reg [2:0] y_ra;
reg y_dv=0;
reg signed [OUT_WIDTH-1:0] y_ram[0:7];
wire signed [OUT_WIDTH-1:0] y_out = y_ram[y_ra]; // SuppressThisWarning VEditor - simulation only
reg signed [WIDTH-1:0] data_in[0:63];
reg signed [OUT_WIDTH-1:0] data_out[0:63];
integer i,j;
initial begin
for (i=0; i<64; i=i+1) begin
`ifdef DCT_INPUT_UNITY
data_in[i] = (i[2:0] == i[5:3]) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
`else
data_in[i] = $random;
`endif
end
$display("Input data in line-scan order:");
for (i=0; i<64; i=i+8) begin
$display ("%d, %d, %d, %d, %d, %d, %d, %d",data_in[i+0],data_in[i+1],data_in[i+2],data_in[i+3],
data_in[i+4],data_in[i+5],data_in[i+6],data_in[i+7]);
end
$display("");
$display("Input data - transposed:");
j=0;
for (i=0; i < 8; i=i+1) begin
$display ("%d, %d, %d, %d, %d, %d, %d, %d",data_in[i+ 0],data_in[i+ 8],data_in[i+16],data_in[i+24],
data_in[i+32],data_in[i+40],data_in[i+48],data_in[i+56]);
end
$display("");
end
always #(CLK_PERIOD/2) CLK = ~CLK;
initial begin
$dumpfile(fstname);
$dumpvars(0,dct_tests_01); // SuppressThisWarning VEditor
#100;
RST = 0;
#100;
repeat (10) @(posedge CLK);
#1 en_x = 1;
for (i = 0; i < 64; i = i+1) begin
@(posedge CLK);
#1;
x_in = data_in[i]; // >>x_wa;
if (i==63) begin
en_x = 0;
end
if (&i[2:0]) repeat (8) @(posedge CLK);
end
#1 x_in = 0;
/*
// running 'one' - just make a period == 17
repeat (7) begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}}; // >>x_wa;
@(posedge CLK);
#1 x_in = 0;
repeat (15) @(posedge CLK); // 16+1= 17, non-zero will go through all of the 8 x[i]
end
begin
@(posedge CLK);
#1 x_in = {2'b1,{WIDTH-2{1'b0}}};
@(posedge CLK);
#1 x_in = 0;
en_x = 0;
end
*/
repeat (64) @(posedge CLK);
$display("");
$display("output data - transposed:");
for (i=0; i<64; i=i+8) begin
$display ("%d, %d, %d, %d, %d, %d, %d, %d",data_out[i+0],data_out[i+1],data_out[i+2],data_out[i+3],
data_out[i+4],data_out[i+5],data_out[i+6],data_out[i+7]);
end
$finish;
end
initial j = 0;
always @ (posedge CLK) begin
if (y_dv) begin
//$display (" y[0x%x] => 0x%x %d, j=%d @%t",y_ra,y_out,y_out,j,$time);
data_out[{j[2:0],j[5:3]}] = y_out; // transpose array
#1 j = j+1;
end
end
always @ (posedge CLK) begin
if (RST) run_in <= 0;
else if (en_x) run_in <= 1;
else if (phase_in == 15) run_in <= 0;
if (RST) run_out <= 0;
else if ((phase_in == 5) || (phase_out==15)) run_out <= run_in;
if (!run_in) phase_in <= 0;
else phase_in <= phase_in + 1;
if (!run_out) phase_out <= 0;
else phase_out <= phase_out + 1;
run_out_d <= run_out;
if (RST) start <= 0;
else start <= run_out & !run_out_d;
{y_we,y_pre_we} <= {y_pre_we, en_out};
if (RST) phase_y <= 8;
else if (pre2_start_out) phase_y <= 0;
else if (y_pre_we) phase_y <= phase_y + 1;
if (RST) y_dv <= 0;
else if ((phase_y == 6) && y_we) y_dv <= 1;
else if (y_ra == 7) y_dv <= 0;
if (!y_dv) y_ra <= 0;
else y_ra <= y_ra + 1;
if (y_we) y_ram[y_wa] <= y_dct;
if (x_we) x_ram[x_wa] <= x_in;
x_out <= x_out_w;
//X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
case (phase_out)
4'h0: x_ra <= 2;
4'h1: x_ra <= 7;
4'h2: x_ra <= 3;
4'h3: x_ra <= 4;
4'h4: x_ra <= 5;
4'h5: x_ra <= 6;
4'h6: x_ra <= 0;
4'h7: x_ra <= 1;
4'h8: x_ra <= 'bx;
4'h9: x_ra <= 3;
4'ha: x_ra <= 5;
4'hb: x_ra <= 4;
4'hc: x_ra <= 'bx;
4'hd: x_ra <= 6;
4'he: x_ra <= 7;
4'hf: x_ra <= 'bx;
endcase
case (phase_y[2:0])
3'h0: y_wa <= 0;
3'h1: y_wa <= 7;
3'h2: y_wa <= 4;
3'h3: y_wa <= 3;
3'h4: y_wa <= 1;
3'h5: y_wa <= 6;
3'h6: y_wa <= 2;
3'h7: y_wa <= 5;
endcase
end
/* Instance template for module dct_iv8_1d */
dct_iv8_1d #(
.WIDTH (WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT),
.B_WIDTH (18),
.A_WIDTH (25),
.P_WIDTH (48),
.COSINE_SHIFT (17),
.COS_01_32 (130441),
.COS_03_32 (125428),
.COS_04_32 (121095),
.COS_05_32 (115595),
.COS_07_32 (101320),
.COS_08_32 (92682),
.COS_09_32 (83151),
.COS_11_32 (61787),
.COS_12_32 (50159),
.COS_13_32 (38048),
.COS_15_32 (12847)
) dct_iv8_1d_i (
.clk (CLK), // input
.rst (RST), // input
.en (run_in), // input
.d_in (x_out), // input[23:0]
.start (start), // input
.dout (y_dct), // output[15:0]
.pre2_start_out (pre2_start_out), // output reg
.en_out (en_out) // output reg
);
endmodule
dsp/dsp_ma_preadd.v
View file @ 69ef600d
...@@ -224,7 +224,7 @@ module dsp_ma_preadd #( ...@@ -224,7 +224,7 @@ module dsp_ma_preadd #(
en_d_r <= en_d; en_d_r <= en_d;
sub_a_r <= sub_a; sub_a_r <= sub_a;
m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{1'b0}}, m_wire}; m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{m_wire[A_WIDTH+B_WIDTH-1]}}, m_wire};
p_reg <= p_reg_cond + m_reg_pm; p_reg <= p_reg_cond + m_reg_pm;
......
dsp/dsp_ma_preadd_c.v 0 → 100644
View file @ 69ef600d
/*!
* dsp_ma_preadd_c
* @file dsp_ma_preadd.v
* @date 2016-06-05
* @author Andrey Filippov
*
* @brief DSP with multi-input multiplier and accumulator with pre-adder
* and post-adder
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
* dsp_ma_preadd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dsp_ma_preadd.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`define INSTANTIATE_DSP48E1
`undef INSTANTIATE_DSP48E1
module dsp_ma_preadd_c #(
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
parameter P_WIDTH = 48)
(
input clk,
input rst,
input signed [B_WIDTH-1:0] bin,
input ceb1, // load b1 register
input ceb2, // load b2 register
input selb, // 0 - select b1, 1 - select b2
input signed [A_WIDTH-1:0] ain,
input cea1, // clock enable a1 reg
input cea2, // clock enable a2 reg
input signed [A_WIDTH-1:0] din,
input ced, // enable d-reg
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input cead, // enable ad register (after pre-adder)
input sela, // 0 - select a1, 1 - select a2
input en_a, // 1 - enable a input (0 - zero) ~inmode[1]
input en_d, // 1 - enable d input (0 - zero) ~inmode[2]
input sub_a, // 0 - pre-add (D+A), 1 - pre-subtract (D-A)
input neg_m, // 1 - negate multiplier result
input accum, // 0 - use multiplier result, 1 add to accumulator
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
output signed [P_WIDTH-1:0] pout
);
`ifdef INSTANTIATE_DSP48E1
wire [4:0] inmode = {~selb,
sub_a,
en_d,
~en_a,
~sela};
wire [3:0] alumode = {2'b0,
neg_m,
neg_m};
wire [6:0] opmode = {1'b0,
accum | post_add,
post_add,
2'b01,
2'b01};
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second
.B_INPUT ("DIRECT"),
.CARRYINREG (1),
.CARRYINSELREG (1),
.CREG (1), //(0),
.DREG (1),
.INMODEREG (1),
.IS_ALUMODE_INVERTED (4'b0),
.IS_CARRYIN_INVERTED (1'b0),
.IS_CLK_INVERTED (1'b0),
.IS_INMODE_INVERTED (5'b0),
.IS_OPMODE_INVERTED (7'b0),
.MASK (48'hffffffffffff),
.MREG (1),
.OPMODEREG (1),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"), //("FALSE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48")
) DSP48E1_i (
.ACOUT (), // output[29:0]
.BCOUT (), // output[17:0]
.CARRYCASCOUT (), // output
.CARRYOUT (), // output[3:0]
.MULTSIGNOUT (), // output
.OVERFLOW (), // output
.P (pout), // output[47:0]
.PATTERNBDETECT (), // output
.PATTERNDETECT (), // output
.PCOUT (), // output[47:0]
.UNDERFLOW (), // output
.A ({{30-A_WIDTH{ain[A_WIDTH-1]}}, ain}), // input[29:0]
.ACIN (30'b0), // input[29:0]
.ALUMODE (alumode), // input[3:0]
.B (bin), // input[17:0]
.BCIN (18'b0), // input[17:0]
.C (cin), // input[47:0]
.CARRYCASCIN (1'b0), // input
.CARRYIN (1'b0), // input
.CARRYINSEL (3'h0), // input[2:0] // later modify?
.CEA1 (cea1), // input
.CEA2 (cea2), // input
.CEAD (cead), // input
.CEALUMODE (1'b1), // input
.CEB1 (ceb1), // input
.CEB2 (ceb2), // input
.CEC (cec), // input
.CECARRYIN (1'b0), // input
.CECTRL (1'b1), // input
.CED (ced), // input
.CEINMODE (1'b1), // input
.CEM (1'b1), // input
.CEP (1'b1), // input
.CLK (clk), // input
.D (din), // input[24:0]
.INMODE (inmode), // input[4:0]
.MULTSIGNIN (1'b0), // input
.OPMODE (opmode), // input[6:0]
.PCIN (48'b0), // input[47:0]
.RSTA (rst), // input
.RSTALLCARRYIN (rst), // input
.RSTALUMODE (rst), // input
.RSTB (rst), // input
.RSTC (rst), // input
.RSTCTRL (rst), // input
.RSTD (rst), // input
.RSTINMODE (rst), // input
.RSTM (rst), // input
.RSTP (rst) // input
);
`else
// Will try to make it infer DSP48e1
reg signed [B_WIDTH-1:0] b1_reg;
reg signed [B_WIDTH-1:0] b2_reg;
reg signed [A_WIDTH-1:0] a1_reg;
reg signed [A_WIDTH-1:0] a2_reg;
reg signed [A_WIDTH-1:0] d_reg;
reg signed [P_WIDTH-1:0] c_reg;
reg signed [A_WIDTH-1:0] ad_reg;
reg signed [P_WIDTH-1:0] m_reg;
reg signed [P_WIDTH-1:0] p_reg;
wire signed [A_WIDTH+B_WIDTH-1:0] m_wire;
wire signed [B_WIDTH-1:0] b_wire;
wire signed [A_WIDTH-1:0] a_wire;
wire signed [A_WIDTH-1:0] d_wire;
reg selb_r;
reg sela_r;
reg en_a_r;
reg en_d_r;
reg sub_a_r;
reg neg_m_r;
reg accum_r;
reg post_add_r;
wire signed [P_WIDTH-1:0] m_reg_pm;
wire signed [P_WIDTH-1:0] p_reg_cond;
/*
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
*/
assign pout = p_reg;
assign b_wire = selb_r ? b2_reg : b1_reg;
assign a_wire = en_a_r ? (sela_r ? a2_reg : a1_reg) : {A_WIDTH{1'b0}};
// assign d_wire = en_d_r ? (sub_a_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
assign d_wire = en_d_r ? d_reg : {A_WIDTH{1'b0}};
assign m_wire = ad_reg * b_wire;
assign m_reg_pm = neg_m_r ? - m_reg : m_reg;
// assign p_reg_cond = accum_r ? p_reg : 0;
assign p_reg_cond = post_add_r? c_reg: (accum_r ? p_reg : 0);
always @ (posedge clk) begin
if (rst) b1_reg <= 0;
else if (ceb1) b1_reg <= bin;
if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin;
if (rst) a1_reg <= 0;
else if (cea1) a1_reg <= ain;
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain;
if (rst) d_reg <= 0;
else if (ced) d_reg <= din;
if (rst) c_reg <= 0;
else if (cec) c_reg <= cin;
if (rst) ad_reg <= 0;
else if (cead) ad_reg <= sub_a_r? (d_wire - a_wire): (d_wire + a_wire);
neg_m_r <= neg_m;
accum_r <= accum;
post_add_r <= post_add;
selb_r <= selb;
sela_r <= sela;
en_a_r <= en_a;
en_d_r <= en_d;
sub_a_r <= sub_a;
m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{m_wire[A_WIDTH+B_WIDTH-1]}}, m_wire};
p_reg <= p_reg_cond + m_reg_pm;
end
`endif
endmodule
py393/x393_jpeg.py
View file @ 69ef600d
...@@ -2563,6 +2563,10 @@ set_camsync_inout 0 7 0 ...@@ -2563,6 +2563,10 @@ set_camsync_inout 0 7 0
#reset_camsync_inout 0 # start with internal trigger #reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None> #set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf set_camsync_mode 1 1 1 1 0 0xf
set_camsync_period 10000 # 100 usec # and start set_camsync_period 10000 # 100 usec # and start
...@@ -2621,6 +2625,7 @@ r ...@@ -2621,6 +2625,7 @@ r
read_status 0x21 read_status 0x21
r r
jpeg_sim_multi 4 jpeg_sim_multi 4
r r
read_status 0x21 read_status 0x21
r r
......
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