Skip to content

X
x393
Commit 691579c0 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

commands and status for LWIR/VOSPI, exported to C

parent c49619fd
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 957 additions and 254 deletions
includes/x393_parameters.vh
View file @ 691579c0
...@@ -35,6 +35,9 @@ ...@@ -35,6 +35,9 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
// All paremeters should be defined for all defines values - needed to export to C
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
...@@ -152,14 +155,14 @@ ...@@ -152,14 +155,14 @@
parameter SLEW_CLK = "SLOW", parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE", parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz `ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0, parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT `ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT , parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else `else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif `endif
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
...@@ -533,7 +536,40 @@ ...@@ -533,7 +536,40 @@
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI //`ifdef HISPI
//`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
//`else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
...@@ -926,7 +962,8 @@ ...@@ -926,7 +962,8 @@
parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor parameter MULTICLK_DIV_XCLK = 12, // 100 MHz for compressor
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz) parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`else `else
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz) parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
parameter MULTICLK_DIV_XCLK2X = 6, // unused value
`endif `endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types) // Additional parameters for multi-clock PLL (phases and buffer types)
......
py393/vrlg.py
View file @ 691579c0
This diff is collapsed.
py393/x393_export_c.py
View file @ 691579c0
...@@ -322,7 +322,9 @@ class X393ExportC(object): ...@@ -322,7 +322,9 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status", stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(),self._enc_status_sens_io_hispi()], data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()],
name = "x393_status_sens_io", typ="ro", name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
...@@ -431,7 +433,8 @@ class X393ExportC(object): ...@@ -431,7 +433,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control", stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(), data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi()], self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()],
name = "x393_sensio_ctl", typ="wo", name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA", stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
...@@ -1853,7 +1856,7 @@ class X393ExportC(object): ...@@ -1853,7 +1856,7 @@ class X393ExportC(object):
dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)")) dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)")) dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output")) dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state")) dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output")) dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number")) dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw return dw
...@@ -1876,11 +1879,26 @@ class X393ExportC(object): ...@@ -1876,11 +1879,26 @@ class X393ExportC(object):
# dw.append(("rel_sol", 18, 3,0, "When SOL active on the last lane @ipclk, latches all other lanes SOL")) # dw.append(("rel_sol", 18, 3,0, "When SOL active on the last lane @ipclk, latches all other lanes SOL"))
# dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)")) # dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
# dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output")) # dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state")) dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output")) dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number")) dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw return dw
def _enc_status_sens_io_vospi(self):
dw=[]
dw.append(("segment_id", 0, 4,0, "ID of the last received segment: 1-4 for the good frame, 0 - for ITAR-skipped frames"))
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
dw.append(("fake in", 11, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self): def _enc_status_sens_i2c(self):
dw=[] dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO")) dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
...@@ -2107,6 +2125,31 @@ class X393ExportC(object): ...@@ -2107,6 +2125,31 @@ class X393ExportC(object):
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value")) dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
return dw return dw
def _enc_sensio_ctrl_vospi(self):
dw=[]
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("rst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("rst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
return dw
def _enc_sensio_jtag(self): def _enc_sensio_jtag(self):
dw=[] dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level")) dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
......
sensor/sens_lepton3.v
View file @ 691579c0
This diff is collapsed.
sensor/sensor_channel.v
View file @ 691579c0
...@@ -227,14 +227,44 @@ module sensor_channel#( ...@@ -227,14 +227,44 @@ module sensor_channel#(
parameter NUM_FRAME_BITS = 4, parameter NUM_FRAME_BITS = 4,
`ifndef HISPI `ifdef HISPI
`ifndef LWIR `elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7, parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif `endif
`endif
// sens_parallel12 other parameters // sens_parallel12 other parameters
...@@ -501,9 +531,12 @@ module sensor_channel#( ...@@ -501,9 +531,12 @@ module sensor_channel#(
reg dav_r; reg dav_r;
wire [15:0] dout_w; wire [15:0] dout_w;
wire dav_w; wire dav_w;
//`ifndef LWIR `ifdef LWIR
wire trig; wire trig; // SuppressThisWarning VEditor - (yet) unused
//`endif `else
wire trig;
`endif
wire prsts; // @pclk - includes sensor reset and sensor PLL reset wire prsts; // @pclk - includes sensor reset and sensor PLL reset
reg sof_out_r; reg sof_out_r;
reg eof_out_r; reg eof_out_r;
...@@ -536,14 +569,24 @@ module sensor_channel#( ...@@ -536,14 +569,24 @@ module sensor_channel#(
`ifdef DEBUG_RING `ifdef DEBUG_RING
`ifdef HISPI `ifdef HISPI
`elsif LWIR
`else `else
reg vact_to_fifo_r; reg vact_to_fifo_r;
`endif `endif
reg hact_to_fifo_r; `ifdef LWIR
reg [15:0] debug_line_cntr; // reg hact_to_fifo_r;
reg [15:0] debug_lines; reg [15:0] debug_line_cntr = 0;
reg [15:0] hact_cntr; reg [15:0] debug_lines = 0;
reg [15:0] vact_cntr; reg [15:0] hact_cntr = 0;
// reg [15:0] vact_cntr;
`else
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`endif
`ifdef HISPI `ifdef HISPI
always @(posedge pclk) begin always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo; // vact_to_fifo_r <= vact_to_fifo;
...@@ -813,7 +856,7 @@ module sensor_channel#( ...@@ -813,7 +856,7 @@ module sensor_channel#(
`endif `endif
`endif `endif
`ifndef LWIR //`ifndef LWIR
pulse_cross_clock pulse_cross_clock_eof_mclk_i ( pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prsts), // input extended to include sensor reset and rst_mmcm .rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input .src_clk (pclk), // input
...@@ -822,7 +865,7 @@ module sensor_channel#( ...@@ -822,7 +865,7 @@ module sensor_channel#(
.out_pulse (eof_mclk), // output .out_pulse (eof_mclk), // output
.busy() // output .busy() // output
); );
`endif //`endif
`ifdef HISPI `ifdef HISPI
...@@ -955,30 +998,60 @@ module sensor_channel#( ...@@ -955,30 +998,60 @@ module sensor_channel#(
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH), .SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN), .SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE), .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH), .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH), .SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), .CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), .CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK), .BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X), .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), .SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), .SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH) .STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // pot used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2,
) sens_lepton3_i ( ) sens_lepton3_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
......
sensor/sensors393.v
View file @ 691579c0
...@@ -223,12 +223,44 @@ module sensors393 #( ...@@ -223,12 +223,44 @@ module sensors393 #(
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI `ifdef HISPI
`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7, parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif `endif
// other parameters for histogram_saxi module // other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0, parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8, parameter HIST_SAXI_MODE_WIDTH = 8,
...@@ -644,7 +676,40 @@ module sensors393 #( ...@@ -644,7 +676,40 @@ module sensors393 #(
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD), .SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW), .SENSI2C_SLEW (SENSI2C_SLEW),
.NUM_FRAME_BITS (NUM_FRAME_BITS), .NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifndef HISPI `ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH), .SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH), .SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY), .SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
......
sensor/vospi_segment_61.v
View file @ 691579c0
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
module vospi_segment_61#( module vospi_segment_61#(
parameter VOSPI_PACKET_WORDS = 80, parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2, parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1, parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4, parameter VOSPI_SEGMENT_LAST = 4,
...@@ -52,23 +53,26 @@ module vospi_segment_61#( ...@@ -52,23 +53,26 @@ module vospi_segment_61#(
)( )(
input rst, input rst,
input clk, input clk,
input start, // start reading segment input start, // start reading segment
input [3:0] exp_segment, // expected segment (1,2,3,4) input [3:0] exp_segment, // expected segment (1,2,3,4)
input segm0_ok, // OK to read segment 0 instead of the current ( exp_segment still has to be 1..4) input segm0_ok, // OK to read segment 0 instead of the current ( exp_segment still has to be 1..4)
input out_en, // enable frame output generation (will finish current frame if disabled, single-pulse input out_en, // enable frame output generation (will finish current frame if disabled, single-pulse
// runs a single frame // runs a single frame
// SPI signals // SPI signals
output spi_clken, // enable clock on spi_clk output spi_clken, // enable clock on spi_clk
output spi_cs, // active low output spi_cs, // active low
input miso, // input from the sensor input miso, // input from the sensor
output [15:0] dout, // 16-bit data received output in_busy, // waiting for or receiving a segment
output hact, // data valid output out_busy,
output sof, // start of frame output reg segment_done, // finished receiving segment (good or bad). next after busy off
output eof, // end of frame output discard_segment, // segment was disc arded
output crc_err, // crc error happened for any packet (valid at eos) output [15:0] dout, // 16-bit data received
output [3:0] id // segment number (valid at eos) output hact, // data valid
output sof, // start of frame
output eof, // end of frame
output crc_err, // crc error happened for any packet (valid at eos)
output [3:0] id // segment number (valid at eos)
); );
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) * localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1); (VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
...@@ -86,10 +90,10 @@ module vospi_segment_61#( ...@@ -86,10 +90,10 @@ module vospi_segment_61#(
reg [ 7:0] full_packet; // current full packet number in a fragment reg [ 7:0] full_packet; // current full packet number in a fragment
reg [ 7:0] full_packet_verified; // next packet verified (will not be discarded later) reg [ 7:0] full_packet_verified; // next packet verified (will not be discarded later)
reg full_packet_frame; // lsb of the input frame // not needed? reg full_packet_frame; // lsb of the input frame // not needed?
reg discard_set; // start discard_segment reg discard_set; // start discard_segment_r
wire segment_good_w; // recognized expected segment, OK to read FIFO wire segment_good_w; // recognized expected segment, OK to read FIFO
reg segment_good; // recognized expected segment, OK to read FIFO reg segment_good; // recognized expected segment, OK to read FIFO
reg discard_segment; // read and discard the rest of the current segment reg discard_segment_r; // read and discard the rest of the current segment
reg running_good; // passed packet 20 reg running_good; // passed packet 20
wire packet_done; // read full packet wire packet_done; // read full packet
wire packet_busy; // receiving SPI packet (same as spi_clken, !spi_cs) wire packet_busy; // receiving SPI packet (same as spi_clken, !spi_cs)
...@@ -101,12 +105,12 @@ module vospi_segment_61#( ...@@ -101,12 +105,12 @@ module vospi_segment_61#(
wire is_last_segment_w; wire is_last_segment_w;
reg start_d; reg start_d;
wire segment_stb; wire segment_stb;
reg crc_err_r; // reg crc_err_r;
wire packet_crc_err; wire packet_crc_err;
reg packet_start; reg packet_start;
wire we; // write data to buffer wire we; // write data to buffer
wire segment_done; wire segment_done_w;
reg segment_busy; reg segment_busy_r;
reg segment_running; // may be discarded reg segment_running; // may be discarded
reg [3:0] segment_id_r; reg [3:0] segment_id_r;
wire frame_in_done; wire frame_in_done;
...@@ -116,11 +120,16 @@ module vospi_segment_61#( ...@@ -116,11 +120,16 @@ module vospi_segment_61#(
assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST); assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST);
assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok); assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT); assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment && packet_dv; assign we = segment_running && !discard_segment_r && packet_dv;
assign crc_err = crc_err_r; assign crc_err = packet_done && packet_crc_err; // crc_err_r;
assign segment_done = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ; assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ;
assign id = segment_id_r; assign id = segment_id_r;
assign frame_in_done = segment_done && last_segment_in; assign frame_in_done = segment_done_w && last_segment_in;
assign in_busy= segment_busy_r; // waiting for or receiving a segment
assign discard_segment= discard_segment_r; // segment was disc arded
// To Buffer // To Buffer
always @ (posedge clk) begin always @ (posedge clk) begin
// if (rst) first_segment_in <= 0; // if (rst) first_segment_in <= 0;
...@@ -131,14 +140,14 @@ module vospi_segment_61#( ...@@ -131,14 +140,14 @@ module vospi_segment_61#(
start_d <= start; start_d <= start;
discard_set <= segment_running && !discard_segment && segment_stb && !segment_good_w; discard_set <= segment_running && !discard_segment_r && segment_stb && !segment_good_w;
segment_good <= segment_running && !discard_segment && segment_stb && segment_good_w; segment_good <= segment_running && !discard_segment_r && segment_stb && segment_good_w;
if (segment_running && !discard_segment && segment_stb) segment_id_r <= packet_id[15:12]; if (segment_running && !discard_segment_r && segment_stb) segment_id_r <= packet_id[15:12];
if (start) discard_segment <= 0; if (start) discard_segment_r <= 0;
else if (discard_set) discard_segment <= 1; else if (discard_set) discard_segment_r <= 1;
if (start) running_good <= 0; if (start) running_good <= 0;
else if (segment_good) running_good <= 1; else if (segment_good) running_good <= 1;
...@@ -150,28 +159,30 @@ module vospi_segment_61#( ...@@ -150,28 +159,30 @@ module vospi_segment_61#(
if (start_d) segment_start_packet <= full_packet; if (start_d) segment_start_packet <= full_packet;
if (start_d) segment_start_waddr <= waddr; if (start_d) segment_start_waddr <= waddr;
if (rst || (start && is_first_segment_w)) full_packet <= 0; if (rst || (start && is_first_segment_w)) full_packet <= 0;
else if (discard_set) full_packet <= segment_start_packet; else if (discard_set) full_packet <= segment_start_packet;
else if (!discard_segment && packet_done) full_packet <= full_packet + 1; else if (!discard_segment_r && packet_done) full_packet <= full_packet + 1;
// if (rst || start) crc_err_r <= 0;
// else if (packet_done && packet_crc_err) crc_err_r <= 0;
if (rst || start) crc_err_r <= 0; if (rst) segment_busy_r <= 0;
else if (packet_done && packet_crc_err) crc_err_r <= 0; else if (start) segment_busy_r <= 1'b1;
else if (segment_done_w) segment_busy_r <= 1'b0;
if (rst) segment_busy <= 0; segment_done <= segment_done_w; // module output reg
else if (start) segment_busy <= 1'b1;
else if (segment_done) segment_busy <= 1'b0;
if (!segment_busy || start) segment_running <= 0; if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1; else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
packet_start <= !rst && !packet_busy && segment_busy; packet_start <= !rst && !packet_busy && segment_busy_r;
if (rst) waddr <= 0; if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr; else if (discard_set) waddr <= segment_start_waddr;
else if (we) waddr <= waddr + 1; else if (we) waddr <= waddr + 1;
if (rst) full_packet_frame <= 0; // not needed? if (rst) full_packet_frame <= 0; // not needed?
else if (frame_in_done) full_packet_frame <=~full_packet_frame; else if (frame_in_done) full_packet_frame <=~full_packet_frame;
end end
// From buffer, generating frame // From buffer, generating frame
reg out_request; reg out_request;
...@@ -209,6 +220,7 @@ module vospi_segment_61#( ...@@ -209,6 +220,7 @@ module vospi_segment_61#(
assign hact = hact_r[2]; assign hact = hact_r[2];
assign eof = eof_r[2]; assign eof = eof_r[2];
assign sof = sof_r; assign sof = sof_r;
assign out_busy = out_request | out_frame;
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst) hact_r <= 0; if (rst) hact_r <= 0;
...@@ -250,8 +262,8 @@ module vospi_segment_61#( ...@@ -250,8 +262,8 @@ module vospi_segment_61#(
end end
vospi_packet_80 #( vospi_packet_80 #(
.VOSPI_PACKET_WORDS(80), .VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80,
.VOSPI_NO_INVALID(1) .VOSPI_NO_INVALID (VOSPI_NO_INVALID) // 1
) vospi_packet_80_i ( ) vospi_packet_80_i (
.rst (rst), // input .rst (rst), // input
.clk (clk), // input .clk (clk), // input
......
util_modules/gpio393.v
View file @ 691579c0
...@@ -221,27 +221,3 @@ module gpio393 #( ...@@ -221,27 +221,3 @@ module gpio393 #(
endmodule endmodule
module gpio_bit (
// input rst, // global reset
input clk, // system clock
input srst, // @posedge clk - sync reset
input we,
input [1:0] d_in, // input bits
output d_out, // output data
output en_out); // enable output
reg d_r = 0;
reg en_r = 0;
assign d_out = d_r;
assign en_out = en_r;
always @ (posedge clk) begin
if (srst) d_r <= 0;
else if (we && (|d_in)) d_r <= !d_in[0];
if (srst) en_r <= 0;
else if (we && (|d_in)) en_r <= !(&d_in);
end
endmodule
x393.v
View file @ 691579c0
...@@ -1834,7 +1834,41 @@ assign axi_grst = axi_rst_pre; ...@@ -1834,7 +1834,41 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR), .SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD), .SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW), .SENSI2C_SLEW (SENSI2C_SLEW),
`ifndef HISPI `ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH), .SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH), .SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY), .SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment