Commit 659e1009 authored by Andrey Filippov's avatar Andrey Filippov

Corrected histograms modules

parent b2d85b91
eclipse.preferences.version=1
encoding//attic/gen_hist_test.py=utf-8
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
......
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Sep 8 23:28:43 2016
[*] Mon Sep 12 14:47:46 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160908170329425.fst"
[dumpfile_mtime] "Thu Sep 8 23:28:35 2016"
[dumpfile_size] 111373882
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160912080538929.fst"
[dumpfile_mtime] "Mon Sep 12 14:47:39 2016"
[dumpfile_size] 92122479
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
[timestart] 0
[size] 1820 1171
[pos] 1928 23
*-25.450548 115800000 239467388 239402388 239527388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 95143150
[size] 1814 1171
[pos] 1936 23
*-13.913612 95182388 77654500 77716800 80133500 86987400 89448000 91674200 91801500 95195280 96480090 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.ddr3_i.ddr3_i.
[treeopen] x393_dut.simul_axi_master_wdata_i.
......@@ -56,20 +56,26 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk4.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk6.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk8.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.timing393_i.
[sst_width] 409
[signals_width] 315
[sst_width] 435
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 641
[sst_vpaned_height] 642
@820
x393_dut.TEST_TITLE[639:0]
@800200
......@@ -2512,6 +2518,10 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_chn[1
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dv[3:0]
x393_dut.x393_i.sensors393_i.frame_num0[3:0]
x393_dut.x393_i.sensors393_i.frame_num1[3:0]
x393_dut.x393_i.sensors393_i.frame_num2[3:0]
x393_dut.x393_i.sensors393_i.frame_num3[3:0]
@800200
-chn0
@28
......@@ -2520,103 +2530,340 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_hact_out
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_pxd_out[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_seq[3:0]
@800200
-sens_histogram_0
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_di[7:0]
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_di[7:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(16)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(17)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(18)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(19)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(20)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(21)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(22)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(23)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(24)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(25)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
@1401200
-group_end
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.dbg_hist_data[7:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.top_margin
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.line_start_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.left_margin
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@28
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@1401200
-group_end
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d0[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d2[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d4[7:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r0[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r1[31:0]
@1401200
-group_end
@c00022
[color] 5
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
@28
[color] 5
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(16)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(17)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(18)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(19)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(20)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(21)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(22)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(23)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(24)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(25)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(26)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(27)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(28)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(29)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(30)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(31)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_data_differ
[color] 2
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_addr_differ
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_1c_in
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_1c_out
@200
-
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_rwaddr[8:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@1401200
-group_end
@c08022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@1401200
-group_end
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_write
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.sof
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_read
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done[1:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk_d
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_frame[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr_zero_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_odd
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_re_even[2:0]
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_re_odd[2:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_done_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@200
-other channels
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.odd
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_b_w_odd[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_b_w_even[31:0]
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_even
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_even_d
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_odd_d
@1000200
-sens_histogram_0
-chn0
@800200
@c00200
-histogram_saxi
@c00022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(3)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(4)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(5)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(6)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(7)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.nreset
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame0[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn0[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn1[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn2[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn3[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame1[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame2[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame3[3:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid0
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data0[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data1[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data2[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data3[31:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.first_burst
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awvalid
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awready
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@1000200
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3
@1401200
-histogram_saxi
@800200
@c00200
-simul_saxi
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.arst
......@@ -2703,20 +2950,12 @@ x393_dut.simul_saxi_gp0_wr_i.waddr_i.next_fill[3:0]
-
@1000200
-waddr
@1401200
-simul_saxi
@1000200
-histgograms
@800200
-ps7
@28
x393_dut.x393_i.ps7_i.SAXIGP0ACLK
x393_dut.x393_i.ps7_i.SAXIGP0ARESETN
x393_dut.x393_i.ps7_i.MAXIGP0ACLK
x393_dut.x393_i.ps7_i.MAXIGP0ARESETN
@200
-
@1000200
-ps7
@200
-
[pattern_trace] 1
[pattern_trace] 0
......@@ -35,7 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300b4; //-a parallel, and more - -0.180/33, 80.68 %
parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
// parameter FPGA_VERSION = 32'h039300b6; //parallel, working on histograms odd colors bug -0.207 /58, 79.68%
// parameter FPGA_VERSION = 32'h039300b5; //parallel, moving histograms earlier -0.123/30, 79.47
// parameter FPGA_VERSION = 32'h039300b4; //-a parallel, and more - -0.180/33, 80.68 %
// parameter FPGA_VERSION = 32'h039300b4; // parallel, and more -0.094/37, 80.18 %
// parameter FPGA_VERSION = 32'h039300b3; // parallel, and more -0.052/8, 79.56%
// parameter FPGA_VERSION = 32'h039300b2; // parallel, and more -0.163 /47, 79.93%
......
......@@ -301,7 +301,7 @@
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -513,7 +513,8 @@
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00,// invert bayer setting
// parameter [1:0] XOR_HIST_BAYER = 2'b00,// invert bayer setting
parameter [1:0] XOR_HIST_BAYER = 2'b01,// invert bayer setting
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
......
......@@ -61,7 +61,7 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "RUN1", //"NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE0 = "RUN1", //"NORM", // "RUN1", "HIST_TEST"
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "RUN1", // "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
......
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160 fff fff 2cf 91e 129 fff fcd caa 776 1cf 081 21b 915 262 4db fff fff 17f 000 245 fff 000 fff 3da 483 189 9c8 000 000 ec5 53f fff 152 9a3 b8d fff 84b 94e 000 e6c 652 000 1b1 98e fff 141 c09 3e8 fff fff a2a fff 487 9bc fff 000 e38 47f fff db3 2cc fff e43
f6c fbd cae fff 181 fff a9f 18c 0a5 68d 000 fff a39 fff b7c fff 000 b91 fb9 96d 44e 000 ce0 000 000 594 5ac 9a9 000 a83 bd3 700 99d fff 9e8 1dd aae 2c3 b00 1e3 fff 000 a3f 000 f35 e49 fff fff 4c3 63e 000 000 82e 000 000 bec 12b fff fff fff 8de fff 000 01c
0ed fff 6cb b4c 6c0 fff 9f5 6c2 95b a93 2e9 000 1ef 936 000 000 844 d2c fff 264 a3d 310 f6c a70 000 e1b c35 40d 000 000 a8e f27 fff a6d eea c3c fff 11c 000 21c 5bc 110 b65 fbb 2f9 000 217 f26 fff 3c5 820 b5a 64d fff 7ae b92 c6a 6f2 913 000 000 f2d fff cfc
3ba ff3 000 fff 60e 3c5 fff 569 fff 6d9 fff 6d7 927 000 000 de7 a5a fff 000 000 fff 63f 5b8 fff 14c 0f4 a35 bd9 81f 054 fff 000 5dd e34 3d3 000 fff aa9 8a2 7bc c7d 000 000 000 000 fff 000 000 000 d3e a93 000 8e4 c46 bed 595 73b fff e98 305 7da 000 000 ec3
364 000 000 ed0 dcd 000 690 e2a 7a4 000 5ac d59 fff 000 a8b c35 6b3 fff 28d fff fff 6a2 5d9 6a2 c38 3fb 401 44d fff 000 709 fff 749 9cc 606 000 78f 000 535 fff 000 b30 000 056 765 768 3b5 000 000 fff 45b ee9 d41 f2c 459 fff 464 fff 27c 83e fff 2cf 000 f48
......@@ -264,7 +264,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
) (
input rst_in,
......
......@@ -84,7 +84,7 @@ module mcntrl_linear_rw #(
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
// just continue.
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
)(
input mrst,
input mclk,
......
......@@ -898,8 +898,8 @@ class X393ExportC(object):
z3z3=(z3,z3)
sdefines +=[
(('Windows for histogram subchannels',)),
(("X393_HISTOGRAM_LT", cs, vrlg.HISTOGRAM_RADDR0 + ba, iam, z3z3, "x393_hist_left_top", "rw", "Specify histograms left/top")),
(("X393_HISTOGRAM_WH", cs, vrlg.HISTOGRAM_RADDR0 + 1 + ba, iam, z3z3, "x393_hist_width_height_m1", "rw", "Specify histograms width/height")),
(("X393_HISTOGRAM_LT", cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_LEFT_TOP + ba, iam, z3z3, "x393_hist_left_top", "rw", "Specify histograms left/top")),
(("X393_HISTOGRAM_WH", cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_WIDTH_HEIGHT + ba, iam, z3z3, "x393_hist_width_height_m1", "rw", "Specify histograms width/height")),
]
ba = vrlg.SENSOR_GROUP_ADDR
ia = vrlg.SENSOR_BASE_INC
......
......@@ -1051,6 +1051,16 @@ setup_all_sensors True None 0x4
cd /usr/local/verilog/; test_mcntrl.py @hargs-after
specify_phys_memory
specify_window
#reset
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 4 0x600 0x4 #reset reset compressor (+2)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x1c48 # reset reset compressor memory (+0)
write_cmd_frame_sequencer 0 1 8 0x6c0 0x3d4b # enable run compressor memory (+2)
write_cmd_frame_sequencer 0 1 8 0x600 0x7 # enable run compressor (+0)
set_rtc # maybe not needed as it can be set differently
camsync_setup 0xf # sensor mask - use local timestamps)
jpeg_write "img.jpeg" 0 80
......@@ -1286,6 +1296,7 @@ killall lighttpd; /usr/sbin/lighttpd -f /etc/lighttpd.conf
/www/pages/exif.php init=/etc/Exif_template.xml
setSensorClock 24.0 "2V5_LVDS"
set_rtc # maybe not needed as it can be set differently
......@@ -1683,12 +1694,105 @@ write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
jpeg_sim_multi 12
################## Simulate Parallel 7 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_sensor_histogram_window 0 0 4 4 25 21
set_sensor_histogram_window 1 0 4 4 41 21
set_sensor_histogram_window 2 0 4 4 25 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
r
read_status 0x21
r
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
jpeg_sim_multi 3
r
read_status 0x21
r
write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
jpeg_sim_multi 4
jpeg_sim_multi 4
jpeg_sim_multi 4
#write_cmd_frame_sequencer 0 1 4 0x6c0 0x1c49 # stop compressor memory (+0)
#write_cmd_frame_sequencer 0 1 6 0x6c0 0x3d4b # enable run compressor memory (+2)
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
bitstream_set_path /usr/local/verilog/x393_hispi.bit
......
......@@ -1858,7 +1858,7 @@ input mem mtd4 ram1
"""
raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
if self.DEBUG_MODE:
if self.DEBUG_MODE or True:
print("set_sensor_histogram_window():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
......
......@@ -38,31 +38,39 @@
*/
`timescale 1ns/1ps
module sens_histogram_mux(
module sens_histogram_mux#(
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
input mclk,
input en,
input rq0,
input [NUM_FRAME_BITS-1:0] hist_frame0, // frame number matching histogram output
output grant0,
input dav0,
input [31:0] din0,
input rq1,
input [NUM_FRAME_BITS-1:0] hist_frame1, // frame number matching histogram output
output grant1,
input dav1,
input [31:0] din1,
input rq2,
input [NUM_FRAME_BITS-1:0] hist_frame2, // frame number matching histogram output
output grant2,
input dav2,
input [31:0] din2,
input rq3,
input [NUM_FRAME_BITS-1:0] hist_frame3, // frame number matching histogram output
output grant3,
input dav3,
input [31:0] din3,
output rq,
output [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
input grant, // grant may stay longer, not masked by rq?
output [1:0] chn,
output dv,
......@@ -100,6 +108,8 @@ module sens_histogram_mux(
assign dav_in = mux_sel[1] ? (mux_sel[0] ? dav3 : dav2) : (mux_sel[0] ? dav1 : dav0);
assign din = mux_sel[1] ? (mux_sel[0] ? din3 : din2) : (mux_sel[0] ? din1 : din0);
assign rq_in = mux_sel[1] ? (mux_sel[0] ? rq3 : rq2) : (mux_sel[0] ? rq1 : rq0);
assign hist_frame = mux_sel[1] ? (mux_sel[0] ? hist_frame3 : hist_frame2) : (mux_sel[0] ? hist_frame1 : hist_frame0);
assign burst_done_w = dav_out && !dav_in;
assign chn_start = {4{start_w}} & {enc_rq[1] & enc_rq[0], enc_rq[1] & ~enc_rq[0], ~enc_rq[1] & enc_rq[0], ~enc_rq[1] & ~enc_rq[0]};
assign chn_sel = {mux_sel[1] & mux_sel[0], mux_sel[1] & ~mux_sel[0], ~mux_sel[1] & mux_sel[0], ~mux_sel[1] & ~mux_sel[0]};
......
......@@ -46,7 +46,9 @@ module sens_histogram_snglclk #(
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00// 11 // invert bayer setting
parameter [1:0] XOR_HIST_BAYER = 2'b00,// 11 // invert bayer setting
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 // SuppressThisWarning VEditor - not used
`endif
......@@ -55,7 +57,7 @@ module sens_histogram_snglclk #(
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// input pclk2x,
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer, valid at sof
input sof,
input eof,
input hact,
......@@ -65,6 +67,7 @@ module sens_histogram_snglclk #(
input hist_en, // @mclk - gracefully enable/disable histogram
input hist_rst, // @mclk - immediately disable if true
output hist_rq,
output reg [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
input hist_grant,
output [31:0] hist_do,
output reg hist_dv,
......@@ -77,19 +80,17 @@ module sens_histogram_snglclk #(
input debug_di // input from the debug ring
`endif
`ifdef DEBUG_HISTOGRAMS
,output [3:0] dbg_hist_data
`endif
);
localparam HIST_WIDTH = (HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32;
reg hist_bank_pclk;
reg [NUM_FRAME_BITS-1:0] hist_frame_ram[0:1]; // frame numbers (in and out)
reg hist_bank_write;
reg [8:0] hist_rwaddr_even; // {bayer[1], pixel}
reg [8:0] hist_rwaddr_odd; // {bayer[1], pixel}
reg hist_bank_mclk;
reg hist_bank_read;
wire set_left_top_w;
wire set_width_height_w;
......@@ -122,8 +123,10 @@ module sens_histogram_snglclk #(
reg [1:0] hact_d;
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
reg [1:0] hist_done; // @pclk single cycle
wire hist_done_mclk;
reg hist_done_mclk_d; // next cycle after hist_done_mclk (hist_bank_read valid)
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
// reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
......@@ -170,12 +173,17 @@ module sens_histogram_snglclk #(
if (sof) debug_lines <= debug_line_cntr;
end
`endif
// frame number transfer from write (pclk) to read (mclk)
always @ (posedge pclk) if (sof) hist_frame_ram[hist_bank_write] <= frame_num_seq;
always @ (posedge mclk) if (hist_done_mclk_d) hist_frame <= hist_frame_ram[hist_bank_read];
always @ (posedge mclk) begin
if (set_left_top_w) lt_mclk <= pio_data;
if (set_width_height_w) wh_mclk <= pio_data;
end
always @ (posedge pclk) begin
if (set_left_top_pclk) {top,left} <= lt_mclk[31:0];
if (set_width_height_pclk) {height_m1,width_m1} <= wh_mclk[31:0];
......@@ -195,9 +203,10 @@ module sens_histogram_snglclk #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
hist_done[0] <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
hist_done[1] <= hist_done[0];
if (!en || hist_done) frame_active <= 0;
if (!en || hist_done[0]) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
......@@ -219,9 +228,9 @@ module sens_histogram_snglclk #(
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi[0]) hcntr <= hcntr - 1;
if (!en) hist_bank_pclk <= 0;
//else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;// NOT applicable in this module
else if (hist_done) hist_bank_pclk <= !hist_bank_pclk;
if (!en) hist_bank_write <= 0;
else if (hist_done[0]) hist_bank_write <= !hist_bank_write;
// hist_xfer_busy to extend en
if (!en) hist_xfer_busy <= 0;
else if (hist_xfer_done) hist_xfer_busy <= 0;
......@@ -244,7 +253,6 @@ module sens_histogram_snglclk #(
end
// assign hlstart = hcntr_zero_w && left_margin && hact_d[0];
reg [6:0] memen_even;
reg [6:0] memen_odd;
wire set_ra_even = memen_even[0];
......@@ -278,22 +286,6 @@ module sens_histogram_snglclk #(
reg eq_prev; // pixel equals previous of the same color
wire eq_prev_d3; // eq_prev delayed by 3 clocks to select r1 source
// wire start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
`ifdef DEBUG_HISTOGRAMS
assign dbg_hist_data[3:0] = {frame_active, hist_done, vert_woi, vcntr_zero_w };
// assign dbg_hist_data[3:0] = {frame_active, hist_rst_pclk, hist_en_pclk, vcntr_zero_w };
reg [2:0] dbg_toggle=0;
// assign dbg_hist_data[3:0] = {dbg_toggle, en_new, en, vcntr_zero_w };
// assign dbg_hist_data[3:0] = {dbg_toggle, vcntr_zero_w }; // version b4 (toggles)
// hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
// if (hist_rst_pclk) en <= 0;
// else if (hist_en_pclk) en <= 1;
// reg en;
// reg en_new; // @ pclk - enable new frame
always @(posedge pclk) begin
if (sof) dbg_toggle <= dbg_toggle+1;
end
`endif
// hist_di is 2 cycles ahead of hor_woi
......@@ -327,9 +319,12 @@ module sens_histogram_snglclk #(
r_load <= {r_load[2:0], regen_even | regen_odd};
r0_sel <= regen_odd;
eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
// eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
// eq_prev <= hor_woi[2] && (px_d2 == px_d0);
eq_prev_prev <= hor_woi[5] && (px_d4 == px_d0);
eq_prev <= hor_woi[3] && (px_d2 == px_d0);
eq_prev <= hor_woi[2] && (px_d2 == px_d0);
if (r_load[0]) r0 <= eq_prev_prev_d2 ? r3 : (r0_sel ? hist_new_odd : hist_new_even);
......@@ -347,9 +342,10 @@ module sens_histogram_snglclk #(
reg en_rq_start;
always @ (posedge mclk) begin
hist_done_mclk_d <= hist_done_mclk;
en_mclk <= en && !hist_rst;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (hist_done_mclk_d) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
......@@ -357,7 +353,7 @@ module sens_histogram_snglclk #(
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// prevent starting rq if grant is still on (back-to-back)
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
hist_rq_r <= !hist_rst & en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
......@@ -366,8 +362,6 @@ module sens_histogram_snglclk #(
else if (hist_grant) hist_re[0] <= 1;
hist_re[2:1] <= hist_re[1:0];
// reg hist_re_even;
// reg hist_re_odd;
if (!hist_out || (&hist_raddr[7:0])) hist_re_even <= 0;
else if (hist_grant && !hist_re[0]) hist_re_even <= !hist_raddr[8];
......@@ -375,21 +369,16 @@ module sens_histogram_snglclk #(
if (!hist_out || (&hist_raddr[7:0])) hist_re_odd <= 0;
else if (hist_grant && !hist_re[0]) hist_re_odd <= hist_raddr[8];
// if (!hist_out || (&hist_raddr[7:1])) hist_re_even_odd[0] <= 0;
// else if (hist_re[0]) hist_re_even_odd[0] <= ~hist_re_even_odd[0];
// else if (hist_grant) hist_re_even_odd[0] <= 1; // hist_re[0] == 0 here
if (!en_mclk) hist_bank_mclk <= 0;
// else if (hist_xfer_done_mclk && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_mclk <= !hist_bank_mclk; // Not applicable in this module
else if (hist_xfer_done_mclk) hist_bank_mclk <= !hist_bank_mclk;
if (hist_done_mclk) hist_bank_read <= !hist_bank_write; // it already changed
hist_dv <= hist_re[2];
end
always @ (posedge pclk) begin
if (!en) wait_readout <= 0;
// else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1; // Not applicable in this module
else if (hist_xfer_done) wait_readout <= 0;
end
......@@ -516,7 +505,7 @@ module sens_histogram_snglclk #(
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hist_done), // input
.in_pulse (hist_done[1]), // input // so hist_done[0] is over before hist_done_mclk started
.out_pulse (hist_done_mclk), // output
.busy() // output
);
......@@ -536,8 +525,8 @@ module sens_histogram_snglclk #(
if ((HISTOGRAM_RAM_MODE=="BUF32") || (HISTOGRAM_RAM_MODE=="NOBUF"))// impossible to use a two RAMB18E1 32-bit wide
sens_hist_ram_snglclk_32 sens_hist_ram_snglclk_32_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.addr_a_even ({hist_bank_write, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_write, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2), // input[31:0]
.data_out_a_even (hist_new_even), // output[31:0]
.data_out_a_odd (hist_new_odd), // output[31:0]
......@@ -548,7 +537,7 @@ module sens_histogram_snglclk #(
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.addr_b ({hist_bank_read,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
......@@ -556,8 +545,8 @@ module sens_histogram_snglclk #(
else if (HISTOGRAM_RAM_MODE=="BUF18")
sens_hist_ram_snglclk_18 sens_hist_ram_snglclk_18_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.addr_a_even ({hist_bank_write, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_write, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2[17:0]), // input[31:0]
.data_out_a_even (hist_new_even[17:0]), // output[31:0]
.data_out_a_odd (hist_new_odd[17:0]), // output[31:0]
......@@ -568,7 +557,7 @@ module sens_histogram_snglclk #(
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.addr_b ({hist_bank_read,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
......@@ -576,7 +565,6 @@ module sens_histogram_snglclk #(
endgenerate
endmodule
module sens_hist_ram_snglclk_32(
......@@ -607,7 +595,8 @@ module sens_hist_ram_snglclk_32(
always @(posedge mclk) begin
re_even_d <= re_even;
re_odd_d <= re_odd;
odd <= re_odd;
// odd <= re_odd;
odd <= re_odd_d;
data_out_b <= odd ? data_out_b_w_odd : data_out_b_w_even;
end
......@@ -744,8 +733,12 @@ module sens_hist_ram_snglclk_18(
endmodule
module sens_histogram_snglclk_dummy(
module sens_histogram_snglclk_dummy #(
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
output hist_rq,
output [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
output [31:0] hist_do,
output hist_dv
`ifdef DEBUG_RING
......@@ -756,6 +749,7 @@ module sens_histogram_snglclk_dummy(
assign hist_rq = 0;
assign hist_do = 0;
assign hist_dv = 0;
assign hist_frame = 0;
`ifdef DEBUG_RING
assign debug_do = debug_di;
`endif
......
......@@ -144,10 +144,6 @@ module sens_parallel12 #(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start // Acknowledge of the first status packet byte (address)
`ifdef DEBUG_HISTOGRAMS
,input [7:0] dbg_hist_data
`endif
);
// delaying vact and pxd by one clock cycle to match hact register
......@@ -251,13 +247,7 @@ module sens_parallel12 #(
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy,
`ifdef DEBUG_HISTOGRAMS
dbg_hist_data,
`else
ps_out,
`endif
xfpgatdo, senspgmin};
assign hact_out = hact_r;
......
......@@ -338,8 +338,6 @@ module sensor_channel#(
input trig_in, // per-sensor trigger input
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
// 16/8-bit mode data to memory (8-bits are packed by 2 in 16 mode @posedge pclk
output [15:0] dout, // @posedge pclk
output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off
......@@ -352,6 +350,7 @@ module sensor_channel#(
// histogram interface to S_AXI, 256x32bit continuous bursts @posedge mclk, each histogram having 4 bursts
output hist_request, // request to transfer a burst
output [NUM_FRAME_BITS-1:0] hist_frame,
input hist_grant, // request to transfer over S_AXI granted
output [1:0] hist_chn, // output[1:0] histogram (sub) channel, valid with request and transfer
output hist_dvalid, // output data valid - active when sending a burst
......@@ -432,7 +431,6 @@ module sensor_channel#(
wire gamma_eof_in;
wire [1:0] gamma_bayer; // gamma module mode register bits -> lens_flat module
wire [7:0] gamma_pxd_out;
wire gamma_hact_out;
wire gamma_sof_out;
......@@ -440,12 +438,15 @@ module sensor_channel#(
wire [31:0] sensor_ctrl_data;
wire sensor_ctrl_we;
// reg [SENSOR_MODE_WIDTH-1:0] mode;
reg [3:0] hist_en;
reg en_mclk; // enable this channel
wire en_pclk; // enable in pclk domain
reg [3:0] hist_nrst;
reg bit16; // 16-bit mode, 0 - 8 bit mode
wire [NUM_FRAME_BITS-1:0] hist_frame0;
wire [NUM_FRAME_BITS-1:0] hist_frame1;
wire [NUM_FRAME_BITS-1:0] hist_frame2;
wire [NUM_FRAME_BITS-1:0] hist_frame3;
wire [3:0] hist_rq;
wire [3:0] hist_gr;
wire [3:0] hist_dv;
......@@ -464,25 +465,6 @@ module sensor_channel#(
reg eof_out_r;
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
`ifdef DEBUG_HISTOGRAMS
wire [7:0] dbg_hist_data;
wire [3:0] dbg_hist_data_hist;
reg [15:0] dbg_cntr;
// reg [1:0] dbg_cntr; // verion B4 - toggles
always @ (posedge pclk) begin
// if (prst) dbg_cntr <= 0;
// else
// if (sof_out_r) dbg_cntr <= dbg_cntr + 1;
if (hist_gr[0] && hist_rq[0]) dbg_cntr <= dbg_cntr + 1; // verion B4 - toggles
end
assign dbg_hist_data = {dbg_cntr[11], hist_en[0], hist_gr[0], hist_rq[0], dbg_hist_data_hist[3:0]};
// assign dbg_hist_data = {prst, hist_en[0], dbg_cntr, dbg_hist_data_hist[3:0]}; // verion B4
// .hist_en (hist_en[0]), // input
// .hist_rst (!hist_nrst[0]), // input
`endif
// TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
assign lens_pxd_in = {pxd[11:0],4'b0};
assign lens_hact_in = hact;
......@@ -968,10 +950,6 @@ module sensor_channel#(
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start) // input
`ifdef DEBUG_HISTOGRAMS
, .dbg_hist_data (dbg_hist_data)
`endif
);
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
......@@ -1177,7 +1155,8 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1185,6 +1164,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1194,6 +1174,7 @@ module sensor_channel#(
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq[0]), // output
.hist_frame (hist_frame0), // output[3:0] reg
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]), // output
......@@ -1203,16 +1184,15 @@ module sensor_channel#(
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
`ifdef DEBUG_HISTOGRAMS
,.dbg_hist_data(dbg_hist_data_hist[3:0])
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_0_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_frame (hist_frame0), // output[3:0] reg
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
......@@ -1282,7 +1262,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1290,6 +1272,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1299,6 +1282,7 @@ module sensor_channel#(
.hist_en (hist_en[1]), // input
.hist_rst (!hist_nrst[1]), // input
.hist_rq (hist_rq[1]), // output
.hist_frame (hist_frame1), // output[3:0] reg
.hist_grant (hist_gr[1]), // input
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]), // output
......@@ -1311,8 +1295,11 @@ module sensor_channel#(
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_1_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_frame (hist_frame1), // output[3:0] reg
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
......@@ -1381,7 +1368,8 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1389,6 +1377,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1398,6 +1387,7 @@ module sensor_channel#(
.hist_en (hist_en[2]), // input
.hist_rst (!hist_nrst[2]), // input
.hist_rq (hist_rq[2]), // output
.hist_frame (hist_frame2), // output[3:0] reg
.hist_grant (hist_gr[2]), // input
.hist_do (hist_do2), // output[31:0]
.hist_dv (hist_dv[2]), // output
......@@ -1410,8 +1400,11 @@ module sensor_channel#(
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_2_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_frame (hist_frame2), // output[3:0] reg
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
`ifdef DEBUG_RING
......@@ -1481,7 +1474,8 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1492,12 +1486,14 @@ module sensor_channel#(
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.hist_di (gamma_pxd_out), // input[7:0]
.bayer (gamma_bayer), // input[1:0]
.mclk (mclk), // input
.hist_en (hist_en[3]), // input
.hist_rst (!hist_nrst[3]), // input
.hist_rq (hist_rq[3]), // output
.hist_frame (hist_frame3), // output[3:0] reg
.hist_grant (hist_gr[3]), // input
.hist_do (hist_do3), // output[31:0]
.hist_dv (hist_dv[3]), // output
......@@ -1510,8 +1506,11 @@ module sensor_channel#(
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_3_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_frame (hist_frame3), // output[3:0] reg
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
......@@ -1522,26 +1521,33 @@ module sensor_channel#(
`endif
endgenerate
sens_histogram_mux sens_histogram_mux_i (
sens_histogram_mux #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_mux_i (
.mclk (mclk), // input
.en (|hist_nrst), // input
.rq0 (hist_rq[0]), // input
.hist_frame0 (hist_frame0), // input[3:0]
.grant0 (hist_gr[0]), // output
.dav0 (hist_dv[0]), // input
.din0 (hist_do0), // input[31:0]
.rq1 (hist_rq[1]), // input
.hist_frame1 (hist_frame1), // input[3:0]
.grant1 (hist_gr[1]), // output
.dav1 (hist_dv[1]), // input
.din1 (hist_do1), // input[31:0]
.rq2 (hist_rq[2]), // input
.hist_frame2 (hist_frame2), // input[3:0]
.grant2 (hist_gr[2]), // output
.dav2 (hist_dv[2]), // input
.din2 (hist_do2), // input[31:0]
.rq3 (hist_rq[3]), // input
.hist_frame3 (hist_frame3), // input[3:0]
.grant3 (hist_gr[3]), // output
.dav3 (hist_dv[3]), // input
.din3 (hist_do3), // input[31:0]
.rq (hist_request), // output
.hist_frame (hist_frame), // input[3:0]
.grant (hist_grant), // input
.chn (hist_chn), // output[1:0]
.dv (hist_dvalid), // output
......
......@@ -456,6 +456,7 @@ module sensors393 #(
wire [127:0] hist_data;
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
......@@ -708,6 +709,8 @@ module sensors393 #(
.sof_out_mclk (sof_out_mclk[i]), // output
.sof_late_mclk(sof_late_mclk[i]), // output
.hist_request (hist_request[i]), // output
.hist_frame (hist_frame[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // output[3:0]
.hist_grant (hist_grant[i]), // input
.hist_chn (hist_chn[2 * i +: 2]), // output[1:0]
.hist_dvalid (hist_dvalid[i]), // output
......@@ -758,35 +761,34 @@ module sensors393 #(
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) histogram_saxi_i (
// .rst (rst), // input
.mclk (mclk), // input
.aclk (aclk), // input
.mrst (mrst), // input
.arst (arst), // input
.frame0 (frame_num0), // input[3:0]
.frame0 (hist_frame[NUM_FRAME_BITS*0 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request0 (hist_request[0]), // input
.hist_grant0 (hist_grant[0]), // output
.hist_chn0 (hist_chn[0 * 2 +: 2]), // input[1:0]
.hist_dvalid0 (hist_dvalid[0]), // input
.hist_data0 (hist_data[0 * 32 +: 32]),// input[31:0]
.frame1 (frame_num1), // input[3:0]
.hist_data0 (hist_data[0 * 32 +: 32]), // input[31:0]
.frame1 (hist_frame[NUM_FRAME_BITS*1 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request1 (hist_request[1]), // input
.hist_grant1 (hist_grant[1]), // output
.hist_chn1 (hist_chn[1 * 2 +: 2]), // input[1:0]
.hist_dvalid1 (hist_dvalid[1]), // input
.hist_data1 (hist_data[1 * 32 +: 32]),// input[31:0]
.frame2 (frame_num2), // input[3:0]
.hist_data1 (hist_data[1 * 32 +: 32]), // input[31:0]
.frame2 (hist_frame[NUM_FRAME_BITS*2 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request2 (hist_request[2]), // input
.hist_grant2 (hist_grant[2]), // output
.hist_chn2 (hist_chn[2 * 2 +: 2]), // input[1:0]
.hist_dvalid2 (hist_dvalid[2]), // input
.hist_data2 (hist_data[2 * 32 +: 32]),// input[31:0]
.frame3 (frame_num3), // input[3:0]
.hist_data2 (hist_data[2 * 32 +: 32]), // input[31:0]
.frame3 (hist_frame[NUM_FRAME_BITS*3 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request3 (hist_request[3]), // input
.hist_grant3 (hist_grant[3]), // output
.hist_chn3 (hist_chn[3 * 2 +: 2]), // input[1:0]
.hist_dvalid3 (hist_dvalid[3]), // input
.hist_data3 (hist_data[3 * 32 +: 32]),// input[31:0]
.hist_data3 (hist_data[3 * 32 +: 32]), // input[31:0]
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.saxi_awaddr (saxi_awaddr), // output[31:0]
......
......@@ -172,6 +172,7 @@ initial begin
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "HIST_TEST") $readmemh({`ROOTPATH,"/input_data/sensor_hist_test.dat"},sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
......
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