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Commit 659e1009 authored by Andrey Filippov's avatar Andrey Filippov
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Corrected histograms modules

parent b2d85b91
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Showing with 880 additions and 465 deletions
.settings/org.eclipse.core.resources.prefs
View file @ 659e1009
eclipse.preferences.version=1
encoding//attic/gen_hist_test.py=utf-8
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
......
cocotb/x393_cocotb_02.sav
View file @ 659e1009
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Sep 8 23:28:43 2016
[*] Mon Sep 12 14:47:46 2016
[*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160908170329425.fst"
[dumpfile_mtime] "Thu Sep 8 23:28:35 2016"
[dumpfile_size] 111373882
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160912080538929.fst"
[dumpfile_mtime] "Mon Sep 12 14:47:39 2016"
[dumpfile_size] 92122479
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
[timestart] 0
[size] 1820 1171
[pos] 1928 23
*-25.450548 115800000 239467388 239402388 239527388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 95143150
[size] 1814 1171
[pos] 1936 23
*-13.913612 95182388 77654500 77716800 80133500 86987400 89448000 91674200 91801500 95195280 96480090 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.ddr3_i.ddr3_i.
[treeopen] x393_dut.simul_axi_master_wdata_i.
......@@ -56,20 +56,26 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk4.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk6.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk8.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.timing393_i.
[sst_width] 409
[signals_width] 315
[sst_width] 435
[signals_width] 312
[sst_expanded] 1
[sst_vpaned_height] 641
[sst_vpaned_height] 642
@820
x393_dut.TEST_TITLE[639:0]
@800200
......@@ -2512,6 +2518,10 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_chn[1
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dv[3:0]
x393_dut.x393_i.sensors393_i.frame_num0[3:0]
x393_dut.x393_i.sensors393_i.frame_num1[3:0]
x393_dut.x393_i.sensors393_i.frame_num2[3:0]
x393_dut.x393_i.sensors393_i.frame_num3[3:0]
@800200
-chn0
@28
......@@ -2520,103 +2530,340 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_sof_
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_hact_out
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.gamma_pxd_out[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_seq[3:0]
@800200
-sens_histogram_0
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_di[7:0]
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_di[7:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(16)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(17)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(18)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(19)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(20)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(21)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(22)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(23)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(24)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
(25)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.status[25:0]
@1401200
-group_end
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.dbg_hist_data[7:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.top_margin
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.line_start_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r_load[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.left_margin
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@28
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hor_woi[6:0]
@1401200
-group_end
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d0[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d2[7:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d4[7:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r0[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r1[31:0]
@1401200
-group_end
@c00022
[color] 5
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
@28
[color] 5
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(10)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(11)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(12)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(13)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(14)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(15)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(16)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(17)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(18)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(19)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(20)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(21)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(22)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(23)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(24)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(25)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(26)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(27)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(28)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(29)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(30)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
[color] 5
(31)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r2[31:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_data_differ
[color] 2
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_addr_differ
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_1c_in
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_1c_out
@200
-
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_rwaddr[8:0]
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
@1401200
-group_end
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@1401200
-group_end
@c08022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
@1401200
-group_end
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_write
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.sof
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_read
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done[1:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk_d
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_frame[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr_zero_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(5)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(6)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(7)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(8)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
(9)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_even
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_odd
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_re_even[2:0]
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_re_odd[2:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_done_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@200
-other channels
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_even[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.dbg_sum_odd[31:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.odd
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_b_w_odd[31:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_b_w_even[31:0]
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_even
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_odd
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_even_d
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.re_odd_d
@1000200
-sens_histogram_0
-chn0
@800200
@c00200
-histogram_saxi
@c00022
x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
@28
(0)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(1)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(2)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(3)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(4)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(5)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(6)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
(7)x393_dut.x393_i.sensors393_i.histogram_saxi_i.mode[7:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.nreset
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame0[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn0[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn1[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn2[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_chn3[1:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame1[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame2[3:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.frame3[3:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_grant0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_dvalid0
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data0[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data1[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data2[31:0]
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_data3[31:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.first_burst
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awvalid
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awready
@22
x393_dut.x393_i.sensors393_i.histogram_saxi_i.saxi_awaddr[31:0]
@1000200
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request0
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request1
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request2
x393_dut.x393_i.sensors393_i.histogram_saxi_i.hist_request3
@1401200
-histogram_saxi
@800200
@c00200
-simul_saxi
@28
x393_dut.x393_i.sensors393_i.histogram_saxi_i.arst
......@@ -2703,20 +2950,12 @@ x393_dut.simul_saxi_gp0_wr_i.waddr_i.next_fill[3:0]
-
@1000200
-waddr
@1401200
-simul_saxi
@1000200
-histgograms
@800200
-ps7
@28
x393_dut.x393_i.ps7_i.SAXIGP0ACLK
x393_dut.x393_i.ps7_i.SAXIGP0ARESETN
x393_dut.x393_i.ps7_i.MAXIGP0ACLK
x393_dut.x393_i.ps7_i.MAXIGP0ARESETN
@200
-
@1000200
-ps7
@200
-
[pattern_trace] 1
[pattern_trace] 0
fpga_version.vh
View file @ 659e1009
......@@ -35,8 +35,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300b4; //-a parallel, and more - -0.180/33, 80.68 %
// parameter FPGA_VERSION = 32'h039300b4; // parallel, and more -0.094/37, 80.18 %
parameter FPGA_VERSION = 32'h039300b7; //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
// parameter FPGA_VERSION = 32'h039300b6; //parallel, working on histograms odd colors bug -0.207 /58, 79.68%
// parameter FPGA_VERSION = 32'h039300b5; //parallel, moving histograms earlier -0.123/30, 79.47
// parameter FPGA_VERSION = 32'h039300b4; //-a parallel, and more - -0.180/33, 80.68 %
// parameter FPGA_VERSION = 32'h039300b4; // parallel, and more -0.094/37, 80.18 %
// parameter FPGA_VERSION = 32'h039300b3; // parallel, and more -0.052/8, 79.56%
// parameter FPGA_VERSION = 32'h039300b2; // parallel, and more -0.163 /47, 79.93%
// parameter FPGA_VERSION = 32'h039300b1; // parallel, more debug -0.335/86, 79.66%
......
includes/x393_parameters.vh
View file @ 659e1009
......@@ -301,7 +301,7 @@
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024, // initial delay value for start pulse
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -513,7 +513,8 @@
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00,// invert bayer setting
// parameter [1:0] XOR_HIST_BAYER = 2'b00,// invert bayer setting
parameter [1:0] XOR_HIST_BAYER = 2'b01,// invert bayer setting
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
......
includes/x393_simulation_parameters.vh
View file @ 659e1009
......@@ -61,10 +61,10 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "RUN1", //"NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "RUN1", // "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SENSOR_IMAGE_TYPE0 = "RUN1", //"NORM", // "RUN1", "HIST_TEST"
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "RUN1", // "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
......
input_data/sensor_hist_test.dat 0 → 100644
View file @ 659e1009
440 000 fff 797 454 d6d 000 b0a 546 000 be3 635 c11 f42 69e 000 000 872 fff a72 315 c8e e4f 17e 000 000 797 731 ab2 fff fff f3c 8de 000 265 c1e 93f 7d6 fff 4df 2dc 000 fff c57 000 42e e60 000 b4b 0cc f8b 07a ab2 d97 6a0 12d 076 524 fff 837 124 175 6c0 ce8
000 c7c 000 541 729 fff 1c4 cea 000 511 dd3 000 b8c 87e 97a a6b 171 000 153 fff 9a2 fff dd4 ef9 ccf fff 4de c18 fff fff 84a c59 138 000 501 b6e 000 e41 a8a 244 f54 000 73d 000 000 8fe 7d6 cb7 a2a fff 56d 000 5fb fff fff a53 f3e 9b2 fff 168 73a e0a 492 000
fff 23d 5e3 7e3 fff 6df 7df 000 fff 000 fff 741 661 7a7 fff cf2 000 a0f 121 000 4ad 575 e23 000 fff 000 000 040 000 c0e e33 fff 4f2 b48 fff 030 c07 939 7c9 451 efe e73 6b5 fd9 1b6 0b8 fff 32a bbd 1e9 85b 29d 497 58a 391 c20 fff 8c8 000 74f 000 fff 99c 000
6bc fff e4f 99f 082 3ee e03 fff fae 2c7 47d 000 fff 000 d41 4da 9e3 275 6d4 5d8 2cf 000 1ce 09d fe9 ffc 454 ed2 2bc 000 b55 b57 fff fff 9bd 874 e4b 000 b3e 371 b56 c8d 357 ffb 000 04c ed1 b45 48a e6a 560 87e 000 a89 fff 97b 30d d79 82a 14d d3a 6b3 4b1 fff
945 000 dae c79 000 000 776 796 000 3ef fff e93 1fc 000 fff 000 1ba 000 d49 120 3c1 e2c 0f6 0ec ecc fff 000 275 914 290 407 000 4af fff 87b 000 000 71a 1e1 133 4ef fe9 11e cca 397 e42 f72 000 242 b92 fff eae 9e9 8c9 000 000 8a1 fff 4c1 6c2 f75 c11 45f 0fb
549 fff fff c20 40d 511 000 fff cb2 a8d f6f fff 000 33d 4ed 13d 000 46e e57 fff 5ea fff 885 000 000 fff a34 000 c6d b4c f6a 000 8db 31d ea4 fff 000 6a1 82b 63d 619 000 fff 700 5c2 8f4 73e 6bd 560 f35 b25 000 9d8 fff 000 c95 3f9 fff 000 91d 2b3 cf1 bef 2ae
85f 481 fff fff fff 000 35d 74b 2c0 ca5 000 5ca 8e0 cc4 fff 5f5 c63 000 000 02f 000 fff 96d fff ab9 ef5 000 689 0bd 000 fff fba 5fb fd1 e2e c1c 000 1ca 000 132 de3 709 12a 000 8b7 91a 000 610 651 c59 e5c fff 0b3 1b8 24e bc2 f85 000 170 fff 000 fff c31 5d0
fff 000 adf 1dc 000 e72 20d b72 000 0ae ec7 fff 777 8cd 095 a1b 3d9 000 6e3 233 664 fff fff 02a 643 a43 455 ee2 ca1 f72 210 ab3 fff 000 469 fff d3f c84 000 8b7 fde ec2 320 781 b8b 0ad 122 989 ba6 6cd a4d 000 fff 000 77c 4b7 657 fff 1f9 d51 98b 000 ee2 f3f
2e7 000 079 000 f3f 000 086 000 994 9ff ac9 d6a 3cb 0d2 61b 000 fff 594 ae5 000 fff fff 14f 505 fff fff b6b 000 000 2a4 96e 000 fff 000 000 fff fff 6be 000 000 84f 03f b3d 703 fff 59d 000 68b 81a ca8 000 fff 000 883 000 1b2 0f1 5f8 941 d17 daf fff 7e7 2a1
fff 559 227 d1e c48 fff fff b24 3f9 a3d fff 000 09f 7f7 fff 2b8 6c3 5a6 ced 000 000 c43 c64 000 ab0 cb1 584 000 220 5c3 fff 000 f9b 000 d38 000 1a1 d93 7ca 4fe fff fff fff 697 0c7 bf6 9ba 000 f57 000 fff d8f 000 000 000 ea0 000 000 f81 8f5 fff 000 8d2 46a
082 fff 4c2 0e5 5d0 cfb 954 053 000 5d7 472 5f8 a01 b3a b9e 000 eaf 1d0 8be 222 a90 4d5 6ef 000 bdf 000 909 d6f afb c56 72a dec 038 786 b57 000 bc1 000 fff d8f d65 000 a02 fff fff d29 000 b94 fff 948 e42 16a 000 5f8 000 000 87f c87 1e3 fb4 e30 5b2 000 5f1
b74 d22 0c2 000 c66 1cc e79 a5b fff 3d2 000 864 fff 9da 000 7dc b28 fff 000 000 058 6ef dfd 018 000 4aa 016 903 7b5 000 f0d fff 40a 52f f0a dcb fff fff 4e0 a4f 1c0 81e 61f cd0 fff 000 fff 1f0 000 000 f58 3a6 000 012 000 623 fff 000 daa 301 000 938 000 000
de1 d9e f74 fd8 9de f91 000 b4b 566 fff f45 ece d16 253 afa fff 512 b02 832 000 126 d2a 000 fd1 fff eaf e8f 000 fff bc5 66f 0d3 cff f24 6f4 d86 273 000 000 5cf 1b3 ed1 000 fff fff 3ec 2a9 3f0 6b9 000 d8e 155 000 913 a0e fff 4be fff 000 000 fff 51c 000 000
34e 387 9dc 39d 4d0 8d8 fff 7d0 860 fff fff 4f3 905 47a 122 426 000 987 018 000 744 2bc 000 fff fff fff f9a fff e7a ff9 000 423 2b5 000 2c5 fff 17e be3 148 3b2 000 9c6 fff 23b 000 e8f fff fff 851 3e4 a42 000 a6c fff 000 000 fff fff 57d 000 fb2 a6e 1ca 8fd
000 74e e51 fff 34a fff fff b35 9de 69f 54a 218 213 c99 661 0e4 343 604 9ec 596 528 e00 666 fff ca5 000 d75 24f 302 6a8 3ef b59 fff fbb fff 7e5 394 e6b baa 1a6 fff 327 38e 000 fff 000 fff b7e ec2 000 000 1b6 b9e 99a 000 c21 000 e60 0bd dbb 000 5b7 cda 0fa
336 fff dbf f84 d5a 318 804 fff e89 7c5 fff 000 000 000 e97 523 07c 000 067 16a fff dc7 fff 0ff 34d 084 000 9dd b7b 184 60c f5e 3e4 fff a28 7f1 4f4 02d fff fb1 8d7 889 e22 fff 000 b40 fff ed6 714 fff 916 fff fff 000 000 fff 000 266 fff 0f6 fff a12 fff 3d5
992 60d 000 a55 000 2f0 4fa 0b8 35b cf2 fff 352 000 000 fff 869 28b f8c 83f 71b fff f12 fff 93c 8d9 43b 814 190 fff c49 f7a fff 90a fff 058 239 f90 fff 551 975 b5f fff f4e 9f7 a93 6ae f5d 000 000 fff 24a f91 512 fff 5a1 9f8 7d9 4e4 f41 459 0b8 000 299 000
f68 000 fff 672 dd2 c0c fba 000 fff 73a 1b8 be2 000 20c 000 358 50d fff 000 b9c f3b 6ce 000 31e 000 72f 267 365 c43 fff 000 000 fff d50 a09 fff 000 867 4d2 fff 012 6f0 000 865 aee 000 d59 ede 3a2 fff 45a 000 000 fc2 fff 645 fff 000 1e4 48b 000 767 000 000
5ba 009 fff 000 8f1 248 000 413 000 23e a26 dc7 e9d fff 000 000 fff 000 fff 898 828 cac fff a79 fb9 000 484 000 fff b82 000 d24 000 b6d 169 cce 000 53b 000 301 dc3 af8 fff 96f 38f fff 2f1 fff 000 fff c11 8b9 a57 000 0f8 a39 000 fff 2e4 fff b14 574 69d 000
000 eec fff 000 99d 3b3 a4c 000 000 fe6 000 489 fff 443 fff 000 7e4 328 e94 000 0b6 901 54a 75c e32 000 f76 fff 7a5 8c6 2a2 000 0d0 226 000 000 c46 8cf 000 000 80f 427 d3d fff c8b 000 000 d4e 94b f77 2fe d35 b27 f7c 57a ad3 8f5 000 fff e0d b23 165 cff a1e
fff ad4 1a1 dda 000 000 000 9ee 85e fff a92 000 928 546 fff 000 fff f7a cb5 000 fff 797 fff 684 000 e39 fff 000 088 8fb 6f6 000 0b8 fff a36 000 000 e13 b2a fff 82c e3b d0e 821 259 fff b7b d3f fff fff 44a e32 930 aa6 cfc fff c62 fff fff 52c 000 d1d bd5 7c9
000 fff fff 395 3cb c5c f03 068 000 000 2c6 d6b fff fff 2c9 59b 0b2 f93 000 1ec 18f 293 000 000 fff b7b 9b6 e6d 849 130 ce3 8c1 000 d99 52f 000 4eb fff 000 000 c18 fff 98c 3e0 000 fff 493 ee1 41e c71 f7a 176 24b e41 000 fff dbd fff 22e e3b fff c52 4cc fff
d51 000 6ef fff 16e 976 6a4 ee1 000 836 000 b71 bf0 000 000 73d fff 7de fff 000 05c fff 3c6 627 5c8 ae1 000 f8a 000 469 2ad 72c fff 45d 000 000 000 bc2 cd0 7d3 e1a c3c 597 fff 14e 27f 000 44e a9b 834 8da e13 000 000 000 413 000 d73 fff 3bb fff b32 5f9 000
7d5 b64 de0 c33 61e ce1 fff ae9 46e fff e4e 000 61a 821 fff fff 4ec 000 79e d80 175 fff d38 33c 000 947 769 2c1 ab2 fff 83e fff 8eb 000 800 78e 000 ffb e21 fff 000 7a4 94b fd9 fff 000 8b0 f55 909 9a8 000 460 a1b 000 23b 000 184 255 000 ac8 1a2 000 fff d65
83d 000 3aa c54 383 000 b9e f6d bd0 000 000 fff fff 22d 000 4c7 fff f2b 26c 70e cea 000 ac2 fff ade 343 d2c 459 624 9da 22f 000 89b 8c6 7a3 000 fff 000 000 bbe 000 8d1 649 96c 000 fff 000 d2e 000 72c cd0 c5d d99 cf6 390 4a7 36c bf9 4dd fff 4fb 4e0 5fb 000
fa7 000 37e 6be e28 ad7 f4c 661 fff 000 fff 3d3 8e8 911 42c c1d 97a fc3 985 e3b 926 526 fff c4d 82a c51 3ee d64 fff 569 dc8 8b2 f4d fff ce9 fff 437 fff 20a d76 fff 187 872 000 5a5 575 fff 663 c82 259 b05 fff 0a0 7e7 4ae 529 931 b87 6e0 000 81b 000 64e fff
fff afa fff fff d43 000 8fb fff 12b 000 6cf 000 000 ecc 9c4 ed8 915 fae fff 855 000 fff 000 000 000 000 9a6 fff 000 000 4d2 000 a97 534 722 000 fff ca3 e06 872 000 fff 2ad bf8 000 fff 24b c69 746 a3d 60f 000 5f3 000 000 a40 c90 a3a 622 e46 efa 8f4 f22 ad2
991 fff 000 000 0d6 6b8 0d6 097 fff b73 170 7db b45 000 000 000 bb0 fff 000 000 fff e67 f26 165 60a 712 262 000 a29 fff 66f 23d 3c7 02d 4e1 fa7 452 d93 000 564 834 000 529 000 b06 043 644 b79 a3f 000 000 9d9 647 fff 821 e3e faf fff fff fff 04b 631 ec9 484
3bb fff fff b2d a65 0aa 39f 64d 106 000 c6a 000 d10 c3d 9dc 5af 000 298 809 fff aad fff 381 fff 1ec 000 0b1 000 053 f06 043 cdd 0a4 cd6 fff fff 000 000 c19 019 177 b23 fff 1e5 c35 e5c 70f 64a 1f9 b49 198 c32 000 000 000 9b1 000 a89 fff 000 5ba 657 190 f85
000 5b5 fff 0a0 000 000 fff 771 fff f62 000 13b fff e33 fff 000 000 d61 dbe b88 d07 640 28a fff d37 ba6 584 ab4 23b e5a 69e 000 03c fff 1a8 af8 000 01f 09e 000 000 b38 89a e9c 000 4c4 000 000 841 fff 000 91f 302 fff 000 fb5 000 d83 7be dea fff 206 fff 43d
dfa a9c 443 289 b0d 178 d8b 000 dfa 8ab 000 a7c 3bd 629 615 9d9 387 fff 000 00b 4ca 950 656 19c a68 07d 0e3 02f 2b2 000 000 7b4 e0a e49 8c4 a18 775 004 c80 000 000 396 414 000 915 368 3e4 69e f6f 296 000 5a8 fff 80b 4e8 829 e3c fff ead 158 52e fff 000 ce9
000 fff fff 000 000 cc6 fff fff fff e18 000 fff fff e66 22a 056 000 000 961 e59 fff fff 194 249 c46 000 000 000 491 0c7 557 e5c 2c3 a04 dc4 0a8 ce0 37e 000 fa0 38b 39a fff 000 000 613 000 21d fff 65b 0c7 b9d 78d fff 18e 90f 6c6 000 91f 616 fff 7d0 127 fff
000 fff 3c9 615 a31 fff 5f4 110 171 000 fff bee fff da8 b07 fff b5e 000 735 fee 3cc 635 83d 8b6 fff 3d5 0b7 000 603 000 fff 000 8c0 000 fff de4 81d de5 fff fff 3ec dad 000 000 e54 fff 27e f3a fff 3f5 000 d8e fa2 461 000 fff 000 76c fff 000 673 131 fff 69a
813 a08 501 5a2 722 568 d53 fff 43f fff fff 603 c83 000 000 0bd e81 aea f33 9cd 36a 822 5da fff 120 fff 573 899 7a5 6be f44 d2c f00 fff 193 000 9ea fff 76f 768 e22 000 f88 000 5e0 a9b a82 000 164 791 000 ef3 1f6 cc8 000 b8a 8cc 000 000 d04 000 67d 2a6 46e
000 4ee 7ec bbb d1d fff 498 b0a f17 f24 997 997 624 000 cd3 b86 fff 000 fff 8c9 c91 789 9ec f94 c35 442 000 000 dc3 792 295 fff 69e c80 b55 cb4 3dc 869 b7d fff 616 000 8a7 966 99b 8cc fff 240 fff 5fa 000 a6b 740 bb9 000 fde 000 755 85d 5de 8ba fff 530 7a7
b76 2ef fff efa fff 7ab 000 cfe 000 f08 58e 000 6e8 5fa 3a3 fff 6ca fff 640 e1c ace fff 000 fff 0d5 3f8 000 d52 73a 000 65d 76d fff 9c9 000 8f8 79f 858 05f 5f0 d24 086 000 47f 29e a5d 000 f1b 225 592 866 fa6 000 c04 4b9 fff 699 1ff 678 5c5 5cb 7bd fff 0d4
2ed 120 fff d78 71d fff 967 845 8b6 34d 000 374 000 e42 fff 8cc cbb c19 eb6 c54 290 f15 bc4 000 8b7 fff fff 64a fff 985 fff 10d fff fff 000 75e f3a 1a6 fff 000 431 ddc c95 000 000 ff9 0cf 57a 000 fff 000 9f9 000 000 000 000 a6b a01 c3d 35f bfd 000 329 312
b93 f7b fff 9f5 69d 653 2e9 638 7f1 5b5 d6f 1f5 0ad fff 48c 424 f30 4bb 234 fff f6e fff 9dd 000 fff 000 000 8be 54c 6b7 a05 bc0 1bd e44 3c9 068 000 fff 000 70b 000 fe7 cff 000 751 79c f67 8a0 fff 720 fdc 68e 74e fff fff fff fff 000 914 d7e 000 000 000 fff
866 6ea 000 fff fff 1f3 bd7 fff 000 de1 52c c2c a04 20e fff 000 746 d23 fff 000 000 fff bb0 000 000 d9f 4ed 78d 000 fff b60 f95 9f2 f9d d67 726 159 5f5 fff 015 a60 743 7b8 000 000 000 581 000 84b ec6 000 fff 3be 0e4 8c0 2e5 53b 319 fff 8b6 7ac 000 8f0 01f
9ed 7ba d9b 884 951 5f8 5f0 c64 000 34e 502 07a fff 517 9e6 541 ab9 439 ebf fff 202 b99 adc fff 279 840 c7b 000 fff f8e fff 000 000 000 9f6 ab2 8dd 3e9 fff a32 76e 8ac 000 77b 83c fff 913 000 8c5 000 2d2 fff fff a00 fff 89c df4 000 fff 000 624 fff 819 c05
7b4 cdd 5c6 ab4 000 fff 97c 533 fff ecd 8da a84 4e3 a25 fff 135 000 000 fff 738 000 63e 000 d48 0e9 4c2 df1 fff b99 3cb 000 fff fff d86 a30 000 0e8 bf6 000 487 a20 fff f07 000 000 3b4 10a fff 000 a5d a41 b65 609 6c9 705 fff 000 293 fff fff 73b fff b46 459
d1d ca8 000 000 fff b1b bd6 4b2 56c b1d 0d2 12d 9a8 3ab fff f29 000 000 000 f74 fff 476 b04 e6d 579 d2b be1 000 1c2 cfd 396 000 1f9 000 0b9 4be 000 2ea 2e2 af8 cb8 fff a9d 000 3da 7ec a25 e8f 64d 000 f49 e55 000 000 000 c7f 000 000 cdf 9f4 fff fff cef 95f
5d6 000 26f 000 fff 000 96d fff 000 fff 93d c84 144 b2e 26d b3c 000 75e 52a 000 e6a fff fff 37f d54 05a 0b3 eb5 a98 000 cdc 8ea 83a 8bf fff 70d 6d1 b17 c60 62c 336 b8d 710 50f 377 aa7 fff 000 883 000 70e fff 115 60c 000 000 788 68e ab7 0dd fff 66d 6a8 89a
fff fff 000 7ac 657 7e8 d3c fff 353 bc3 4f2 593 03a fe0 879 000 876 ca1 fff 000 000 d71 fff 445 fff 16b 000 77f 000 fff 000 ae6 000 7ee fff fff 2d9 fff f46 94b 98c 0b1 fff f18 000 38e 57e 000 78b fff 8f2 000 d1f 18f fff a2f 9ca fff 000 44d fff 431 000 000
fff 000 b52 000 fff 000 a97 5eb 01b fff a95 f8a a63 a22 47b 94a 3b1 588 633 903 000 83f 3c7 fff fff fff fff 000 c97 0e6 000 fff fff 708 163 6bc 394 0eb eff 9df 086 000 fff 0e6 f40 f7b fff eea b09 477 df4 fff 000 a64 78e a51 88e 6b9 000 29d 6c0 427 000 b79
6fc 5f1 fff 0e6 fff a68 fff 72c a69 b2b 69b 05c 41b 401 156 000 142 000 20a 1a3 000 000 4bd 823 000 50e 000 90f 2f2 8cc 8cd 433 fff 1eb 000 11c fff 8b4 7c8 795 fff 78e 72b 000 6c7 991 b55 970 fff 000 b3a c44 4ba 276 e37 d4c fff 603 000 000 fff 559 81b 7c4
fff 7fa 2df 60a 949 7c3 259 000 fc8 c08 fff 000 000 000 bf0 2a8 1a7 b91 b68 94a 000 76f a17 97f 708 000 000 fff 31d 9e2 b91 636 361 fff d62 ac3 000 d6d ba4 7c1 fff c35 3fc fff 318 8df 7ff fec 5dd 201 b54 000 cd1 cfe 7ed 000 e23 ef9 94f fff edc e09 8fb e38
173 7b2 07c 3b9 000 000 834 000 cf5 0f4 329 000 dd2 a61 21d a31 f45 9e1 f7d 730 000 dfb 000 3a4 987 e90 a01 000 076 f56 2d4 fff fff 000 80b 000 000 880 fff 000 c32 433 fd0 ea7 6ef 000 0da edd cec 963 c66 93d 334 0a0 256 000 000 36a 9c2 77b a35 30f 0c4 000
000 fff fff 000 000 d90 000 80e 91e fff e2e 000 d65 000 d13 2f9 000 fff 1ff 000 e09 cde fff 7d3 2f1 000 000 5d1 000 69a a69 619 c66 fff d99 702 2c1 a1a 011 26a 69a 887 5aa 2bd fde 77c 4f8 965 86b 266 fff 000 fff 000 000 c3a fff fff 267 649 ec3 29f a0a 000
000 773 000 9cb 000 052 fff 000 000 8a0 fff 728 000 2b6 357 ce9 000 fff 000 68b fff 000 a51 483 000 506 000 c07 2f1 920 4e1 380 3f2 161 514 221 fff 713 fff fff 8fb fff bfd ed1 2eb 000 fff fff f04 3b7 978 495 56b 079 000 e96 94e c7d 331 000 4c5 301 2f3 fd8
cbe bff fff fff 42b b94 539 a16 3b2 f5a 40d 03b fff 3fa fff fff 6ab fff 000 fff dd9 000 000 86a 365 000 3ad 000 304 000 8c3 ae0 1c4 e67 382 fd2 d30 fff 899 c18 000 cd2 82d db4 259 78d fff 000 16a fff 01b 97c fff a5b fa7 088 b7c 217 9c2 2aa fff 000 fff 5c5
213 76c 3c9 a9d 000 273 b2f 000 3e8 10b 000 8a2 428 282 133 104 000 c0c 9ee 30a 4cf fff 000 000 b57 000 a34 fff f60 942 000 000 fff 000 fff fff e8a 029 000 000 dd8 3e8 fff fff 000 e3f d12 fff fff fff ef1 bc9 14f 7fa fff 3fe 3bd a4a 02b 000 000 12a 000 000
8f3 87f 33e 000 fff fff 000 c73 13d 6c2 769 000 000 667 000 bd8 fff 000 fff 000 50d 040 4af 000 6d3 000 d61 00e f0e 000 bf7 ef5 a1e e17 33a 1e8 a95 34e 000 e7e 0a4 000 40c 000 000 000 000 17a 283 ef6 762 000 8c8 fff 000 468 acf 000 682 79c 092 728 fff 5f4
000 fff fff 481 000 fff fff d6f f50 922 6ab 000 e93 000 fff ec3 fff a53 000 2e1 000 c39 000 000 509 388 146 fff dfb adb fff 748 d8e fff 004 fff ad4 43e b1e 3e3 ab8 a48 fff 417 809 fff 421 000 d80 cf6 fff 000 cc8 000 9ce 82d 454 465 000 84e aaa 000 000 000
fff 990 ae3 03f 3cf 000 000 fff fff 98e 000 000 fff fff 000 381 000 000 1b8 028 000 000 f67 fff e41 000 7a5 4b5 629 308 000 a4d 622 64c 000 e4c 000 b60 6a4 63e d46 000 000 e31 e9a fff f86 798 d88 000 b32 fff 14b 4e3 000 fff 9e3 856 fff fff fb9 22b 2f7 565
ec4 43e fff fff eb2 fa5 8d5 059 d08 acc e5a 874 b6e c2e 1ec 000 ab6 b2a fff b04 7e0 fff fff 24e 422 b58 989 000 213 24b 91a 000 2de ea6 973 c85 000 8d9 fa2 000 000 eb8 51a 283 a81 b46 9e1 000 ab1 263 000 fff 000 8da 000 70c 000 fff fff 000 e5b c66 a0b 4ee
5ff 000 059 859 fff fff f72 fff 36c fd9 fff 3c5 051 4f0 edc ed6 3c3 178 000 000 ea4 342 7a7 2e5 000 282 a28 fff 000 3c0 fff 9c7 f98 08a a24 000 85e 79d 654 6d4 b11 03a 0a9 9bc 630 000 ef9 2ab fff 63c 283 000 f28 351 f2d 000 fff 37b fff d7d 000 2c4 000 041
e91 fff 0fe 54b f65 a35 a9a 01a fff 000 3d7 fff 14c 946 a50 fff e23 006 c88 dd0 b43 fff 8ec fff 1cf fff bd5 54b cf2 b94 000 e89 fff 9bb 000 f71 1b8 063 561 586 888 9f4 fff fff fff d51 464 000 68f fff fff 4df 1e8 a20 611 000 2ec 608 84b ae7 000 330 b81 f39
df1 fff 000 000 000 009 5b5 3f6 000 170 c3c 000 b94 fff c5e fff 699 fff 000 fff bd3 985 fff eb0 fff 34d fff c43 000 fe5 6bc fff 000 dde 1bb 55e 2f6 d28 fff fff 313 8da 4df 71d 000 fff 113 1cb b77 e0c 000 295 62b fff 457 000 000 a47 1e2 6f4 6ea 000 c67 5f1
160 fff fff 2cf 91e 129 fff fcd caa 776 1cf 081 21b 915 262 4db fff fff 17f 000 245 fff 000 fff 3da 483 189 9c8 000 000 ec5 53f fff 152 9a3 b8d fff 84b 94e 000 e6c 652 000 1b1 98e fff 141 c09 3e8 fff fff a2a fff 487 9bc fff 000 e38 47f fff db3 2cc fff e43
f6c fbd cae fff 181 fff a9f 18c 0a5 68d 000 fff a39 fff b7c fff 000 b91 fb9 96d 44e 000 ce0 000 000 594 5ac 9a9 000 a83 bd3 700 99d fff 9e8 1dd aae 2c3 b00 1e3 fff 000 a3f 000 f35 e49 fff fff 4c3 63e 000 000 82e 000 000 bec 12b fff fff fff 8de fff 000 01c
0ed fff 6cb b4c 6c0 fff 9f5 6c2 95b a93 2e9 000 1ef 936 000 000 844 d2c fff 264 a3d 310 f6c a70 000 e1b c35 40d 000 000 a8e f27 fff a6d eea c3c fff 11c 000 21c 5bc 110 b65 fbb 2f9 000 217 f26 fff 3c5 820 b5a 64d fff 7ae b92 c6a 6f2 913 000 000 f2d fff cfc
3ba ff3 000 fff 60e 3c5 fff 569 fff 6d9 fff 6d7 927 000 000 de7 a5a fff 000 000 fff 63f 5b8 fff 14c 0f4 a35 bd9 81f 054 fff 000 5dd e34 3d3 000 fff aa9 8a2 7bc c7d 000 000 000 000 fff 000 000 000 d3e a93 000 8e4 c46 bed 595 73b fff e98 305 7da 000 000 ec3
364 000 000 ed0 dcd 000 690 e2a 7a4 000 5ac d59 fff 000 a8b c35 6b3 fff 28d fff fff 6a2 5d9 6a2 c38 3fb 401 44d fff 000 709 fff 749 9cc 606 000 78f 000 535 fff 000 b30 000 056 765 768 3b5 000 000 fff 45b ee9 d41 f2c 459 fff 464 fff 27c 83e fff 2cf 000 f48
memctrl/mcntrl393.v
View file @ 659e1009
......@@ -249,22 +249,22 @@ module mcntrl393 #(
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
// bits in mode control word
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
) (
input rst_in,
......
memctrl/mcntrl_linear_rw.v
View file @ 659e1009
......@@ -84,7 +84,7 @@ module mcntrl_linear_rw #(
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
// just continue.
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
)(
input mrst,
input mclk,
......
py393/x393_export_c.py
View file @ 659e1009
......@@ -898,8 +898,8 @@ class X393ExportC(object):
z3z3=(z3,z3)
sdefines +=[
(('Windows for histogram subchannels',)),
(("X393_HISTOGRAM_LT", cs, vrlg.HISTOGRAM_RADDR0 + ba, iam, z3z3, "x393_hist_left_top", "rw", "Specify histograms left/top")),
(("X393_HISTOGRAM_WH", cs, vrlg.HISTOGRAM_RADDR0 + 1 + ba, iam, z3z3, "x393_hist_width_height_m1", "rw", "Specify histograms width/height")),
(("X393_HISTOGRAM_LT", cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_LEFT_TOP + ba, iam, z3z3, "x393_hist_left_top", "rw", "Specify histograms left/top")),
(("X393_HISTOGRAM_WH", cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_WIDTH_HEIGHT + ba, iam, z3z3, "x393_hist_width_height_m1", "rw", "Specify histograms width/height")),
]
ba = vrlg.SENSOR_GROUP_ADDR
ia = vrlg.SENSOR_BASE_INC
......
py393/x393_jpeg.py
View file @ 659e1009
......@@ -1051,6 +1051,16 @@ setup_all_sensors True None 0x4
cd /usr/local/verilog/; test_mcntrl.py @hargs-after
specify_phys_memory
specify_window
#reset
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 4 0x600 0x4 #reset reset compressor (+2)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x1c48 # reset reset compressor memory (+0)
write_cmd_frame_sequencer 0 1 8 0x6c0 0x3d4b # enable run compressor memory (+2)
write_cmd_frame_sequencer 0 1 8 0x600 0x7 # enable run compressor (+0)
set_rtc # maybe not needed as it can be set differently
camsync_setup 0xf # sensor mask - use local timestamps)
jpeg_write "img.jpeg" 0 80
......@@ -1286,6 +1296,7 @@ killall lighttpd; /usr/sbin/lighttpd -f /etc/lighttpd.conf
/www/pages/exif.php init=/etc/Exif_template.xml
setSensorClock 24.0 "2V5_LVDS"
set_rtc # maybe not needed as it can be set differently
......@@ -1683,12 +1694,105 @@ write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
jpeg_sim_multi 12
################## Simulate Parallel 7 ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_sensor_histogram_window 0 0 4 4 25 21
set_sensor_histogram_window 1 0 4 4 41 21
set_sensor_histogram_window 2 0 4 4 25 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#sequencer test
#ctrl_cmd_frame_sequencer <num_sensor> <reset=False> <start=False> <stop=False>
ctrl_cmd_frame_sequencer 0 0 1 0
write_cmd_frame_sequencer 0 1 1 0x700 0x6
write_cmd_frame_sequencer 0 1 1 0x700 0x9
write_cmd_frame_sequencer 0 1 1 0x700 0xa0
write_cmd_frame_sequencer 0 1 1 0x700 0x50
write_cmd_frame_sequencer 0 0 3 0x700 0xa000
write_cmd_frame_sequencer 0 1 0 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0xe00
write_cmd_frame_sequencer 0 0 3 0x700 0xa
write_cmd_frame_sequencer 0 0 2 0x700 0x6
write_cmd_frame_sequencer 0 0 2 0x700 0x9
write_cmd_frame_sequencer 0 0 2 0x700 0x60
write_cmd_frame_sequencer 0 0 2 0x700 0x90
write_cmd_frame_sequencer 0 0 2 0x700 0x600
write_cmd_frame_sequencer 0 0 2 0x700 0x900
r
read_status 0x21
r
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
jpeg_sim_multi 3
r
read_status 0x21
r
write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
jpeg_sim_multi 4
jpeg_sim_multi 4
jpeg_sim_multi 4
#write_cmd_frame_sequencer 0 1 4 0x6c0 0x1c49 # stop compressor memory (+0)
#write_cmd_frame_sequencer 0 1 6 0x6c0 0x3d4b # enable run compressor memory (+2)
################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs
bitstream_set_path /usr/local/verilog/x393_hispi.bit
......
py393/x393_sensor.py
View file @ 659e1009
......@@ -1858,7 +1858,7 @@ input mem mtd4 ram1
"""
raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
if self.DEBUG_MODE:
if self.DEBUG_MODE or True:
print("set_sensor_histogram_window():")
print("num_sensor = ", num_sensor)
print("subchannel = ", subchannel)
......
sensor/sens_histogram_mux.v
View file @ 659e1009
......@@ -38,35 +38,43 @@
*/
`timescale 1ns/1ps
module sens_histogram_mux(
input mclk,
input en,
module sens_histogram_mux#(
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
input mclk,
input en,
input rq0,
output grant0,
input dav0,
input [31:0] din0,
input rq0,
input [NUM_FRAME_BITS-1:0] hist_frame0, // frame number matching histogram output
output grant0,
input dav0,
input [31:0] din0,
input rq1,
output grant1,
input dav1,
input [31:0] din1,
input rq1,
input [NUM_FRAME_BITS-1:0] hist_frame1, // frame number matching histogram output
output grant1,
input dav1,
input [31:0] din1,
input rq2,
output grant2,
input dav2,
input [31:0] din2,
input rq2,
input [NUM_FRAME_BITS-1:0] hist_frame2, // frame number matching histogram output
output grant2,
input dav2,
input [31:0] din2,
input rq3,
output grant3,
input dav3,
input [31:0] din3,
input rq3,
input [NUM_FRAME_BITS-1:0] hist_frame3, // frame number matching histogram output
output grant3,
input dav3,
input [31:0] din3,
output rq,
input grant, // grant may stay longer, not masked by rq?
output [1:0] chn,
output dv,
output [31:0] dout
output rq,
output [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
input grant, // grant may stay longer, not masked by rq?
output [1:0] chn,
output dv,
output [31:0] dout
);
reg [2:0] burst0;
......@@ -97,9 +105,11 @@ module sens_histogram_mux(
assign pri_rq = {rq3 & ~rq2 & ~rq1 & ~rq0, rq2 & ~rq1 & ~ rq0, rq1 & ~ rq0, rq0};
assign busy_w = |burst0 || (|burst1) || (|burst2) || (|burst3);
assign start_w = enc_rq[2] && !busy_r && !started;
assign dav_in = mux_sel[1] ? (mux_sel[0] ? dav3 : dav2) : (mux_sel[0] ? dav1 : dav0);
assign din = mux_sel[1] ? (mux_sel[0] ? din3 : din2) : (mux_sel[0] ? din1 : din0);
assign rq_in = mux_sel[1] ? (mux_sel[0] ? rq3 : rq2) : (mux_sel[0] ? rq1 : rq0);
assign dav_in = mux_sel[1] ? (mux_sel[0] ? dav3 : dav2) : (mux_sel[0] ? dav1 : dav0);
assign din = mux_sel[1] ? (mux_sel[0] ? din3 : din2) : (mux_sel[0] ? din1 : din0);
assign rq_in = mux_sel[1] ? (mux_sel[0] ? rq3 : rq2) : (mux_sel[0] ? rq1 : rq0);
assign hist_frame = mux_sel[1] ? (mux_sel[0] ? hist_frame3 : hist_frame2) : (mux_sel[0] ? hist_frame1 : hist_frame0);
assign burst_done_w = dav_out && !dav_in;
assign chn_start = {4{start_w}} & {enc_rq[1] & enc_rq[0], enc_rq[1] & ~enc_rq[0], ~enc_rq[1] & enc_rq[0], ~enc_rq[1] & ~enc_rq[0]};
assign chn_sel = {mux_sel[1] & mux_sel[0], mux_sel[1] & ~mux_sel[0], ~mux_sel[1] & mux_sel[0], ~mux_sel[1] & ~mux_sel[0]};
......
sensor/sens_histogram_snglclk.v
View file @ 659e1009
......@@ -46,30 +46,33 @@ module sens_histogram_snglclk #(
parameter HISTOGRAM_ADDR_MASK = 'h7fe,
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
parameter [1:0] XOR_HIST_BAYER = 2'b00// 11 // invert bayer setting
parameter [1:0] XOR_HIST_BAYER = 2'b00,// 11 // invert bayer setting
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
`ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 // SuppressThisWarning VEditor - not used
`endif
)(
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// input pclk2x,
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
input [1:0] bayer,
input mclk,
input hist_en, // @mclk - gracefully enable/disable histogram
input hist_rst, // @mclk - immediately disable if true
output hist_rq,
input hist_grant,
output [31:0] hist_do,
output reg hist_dv,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb // strobe (with first byte) for the command a/d
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer, valid at sof
input sof,
input eof,
input hact,
input [7:0] hist_di, // 8-bit pixel data
input [1:0] bayer,
input mclk,
input hist_en, // @mclk - gracefully enable/disable histogram
input hist_rst, // @mclk - immediately disable if true
output hist_rq,
output reg [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
input hist_grant,
output [31:0] hist_do,
output reg hist_dv,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb // strobe (with first byte) for the command a/d
// , input monochrome // NOT supported in this implementation - use software to sum
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
......@@ -77,19 +80,17 @@ module sens_histogram_snglclk #(
input debug_di // input from the debug ring
`endif
`ifdef DEBUG_HISTOGRAMS
,output [3:0] dbg_hist_data
`endif
);
localparam HIST_WIDTH = (HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32;
reg hist_bank_pclk;
reg [NUM_FRAME_BITS-1:0] hist_frame_ram[0:1]; // frame numbers (in and out)
reg hist_bank_write;
reg [8:0] hist_rwaddr_even; // {bayer[1], pixel}
reg [8:0] hist_rwaddr_odd; // {bayer[1], pixel}
reg hist_bank_mclk;
reg hist_bank_read;
wire set_left_top_w;
wire set_width_height_w;
......@@ -122,8 +123,10 @@ module sens_histogram_snglclk #(
reg [1:0] hact_d;
reg top_margin; // above (before) active window
reg hist_done; // @pclk single cycle
reg [1:0] hist_done; // @pclk single cycle
wire hist_done_mclk;
reg hist_done_mclk_d; // next cycle after hist_done_mclk (hist_bank_read valid)
reg vert_woi; // vertically in window TESTED ACTIVE
reg left_margin; // left of (before) active window
// reg [2:0] woi; // @ pclk2x - inside WOI (and delayed
......@@ -169,13 +172,18 @@ module sens_histogram_snglclk #(
if (sof) debug_lines <= debug_line_cntr;
end
`endif
`endif
// frame number transfer from write (pclk) to read (mclk)
always @ (posedge pclk) if (sof) hist_frame_ram[hist_bank_write] <= frame_num_seq;
always @ (posedge mclk) if (hist_done_mclk_d) hist_frame <= hist_frame_ram[hist_bank_read];
always @ (posedge mclk) begin
if (set_left_top_w) lt_mclk <= pio_data;
if (set_width_height_w) wh_mclk <= pio_data;
end
always @ (posedge pclk) begin
if (set_left_top_pclk) {top,left} <= lt_mclk[31:0];
if (set_width_height_pclk) {height_m1,width_m1} <= wh_mclk[31:0];
......@@ -195,9 +203,10 @@ module sens_histogram_snglclk #(
if (!en ||(pre_first_line && !hact)) vert_woi <= 0;
else if (vcntr_zero_w & line_start_w) vert_woi <= top_margin;
hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
hist_done[0] <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
hist_done[1] <= hist_done[0];
if (!en || hist_done) frame_active <= 0;
if (!en || hist_done[0]) frame_active <= 0;
else if (sof && en_new) frame_active <= 1;
......@@ -219,9 +228,9 @@ module sens_histogram_snglclk #(
else if (hcntr_zero_w && left_margin) hcntr <= width_m1;
else if (left_margin || hor_woi[0]) hcntr <= hcntr - 1;
if (!en) hist_bank_pclk <= 0;
//else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;// NOT applicable in this module
else if (hist_done) hist_bank_pclk <= !hist_bank_pclk;
if (!en) hist_bank_write <= 0;
else if (hist_done[0]) hist_bank_write <= !hist_bank_write;
// hist_xfer_busy to extend en
if (!en) hist_xfer_busy <= 0;
else if (hist_xfer_done) hist_xfer_busy <= 0;
......@@ -244,7 +253,6 @@ module sens_histogram_snglclk #(
end
// assign hlstart = hcntr_zero_w && left_margin && hact_d[0];
reg [6:0] memen_even;
reg [6:0] memen_odd;
wire set_ra_even = memen_even[0];
......@@ -278,22 +286,6 @@ module sens_histogram_snglclk #(
reg eq_prev; // pixel equals previous of the same color
wire eq_prev_d3; // eq_prev delayed by 3 clocks to select r1 source
// wire start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
`ifdef DEBUG_HISTOGRAMS
assign dbg_hist_data[3:0] = {frame_active, hist_done, vert_woi, vcntr_zero_w };
// assign dbg_hist_data[3:0] = {frame_active, hist_rst_pclk, hist_en_pclk, vcntr_zero_w };
reg [2:0] dbg_toggle=0;
// assign dbg_hist_data[3:0] = {dbg_toggle, en_new, en, vcntr_zero_w };
// assign dbg_hist_data[3:0] = {dbg_toggle, vcntr_zero_w }; // version b4 (toggles)
// hist_done <= vert_woi && (eof || (vcntr_zero_w && line_start_w)); // hist done never asserted, line_start_w - active
// if (hist_rst_pclk) en <= 0;
// else if (hist_en_pclk) en <= 1;
// reg en;
// reg en_new; // @ pclk - enable new frame
always @(posedge pclk) begin
if (sof) dbg_toggle <= dbg_toggle+1;
end
`endif
// hist_di is 2 cycles ahead of hor_woi
......@@ -327,9 +319,12 @@ module sens_histogram_snglclk #(
r_load <= {r_load[2:0], regen_even | regen_odd};
r0_sel <= regen_odd;
eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
// eq_prev_prev <= hor_woi[4] && (px_d4 == px_d0);
// eq_prev <= hor_woi[2] && (px_d2 == px_d0);
eq_prev_prev <= hor_woi[5] && (px_d4 == px_d0);
eq_prev <= hor_woi[3] && (px_d2 == px_d0);
eq_prev <= hor_woi[2] && (px_d2 == px_d0);
if (r_load[0]) r0 <= eq_prev_prev_d2 ? r3 : (r0_sel ? hist_new_odd : hist_new_even);
......@@ -347,17 +342,18 @@ module sens_histogram_snglclk #(
reg en_rq_start;
always @ (posedge mclk) begin
hist_done_mclk_d <= hist_done_mclk;
en_mclk <= en && !hist_rst;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
if (!en_mclk) hist_out <= 0;
else if (hist_done_mclk_d) hist_out <= 1;
else if (&hist_raddr) hist_out <= 0;
hist_out_d <= hist_out;
// reset address each time new transfer is started
if (!hist_out) hist_raddr <= 0;
else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
// prevent starting rq if grant is still on (back-to-back)
// prevent starting rq if grant is still on (back-to-back)
if (!hist_out) en_rq_start <= 0;
else if (!hist_grant) en_rq_start <= 1;
hist_rq_r <= !hist_rst & en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
......@@ -366,8 +362,6 @@ module sens_histogram_snglclk #(
else if (hist_grant) hist_re[0] <= 1;
hist_re[2:1] <= hist_re[1:0];
// reg hist_re_even;
// reg hist_re_odd;
if (!hist_out || (&hist_raddr[7:0])) hist_re_even <= 0;
else if (hist_grant && !hist_re[0]) hist_re_even <= !hist_raddr[8];
......@@ -375,21 +369,16 @@ module sens_histogram_snglclk #(
if (!hist_out || (&hist_raddr[7:0])) hist_re_odd <= 0;
else if (hist_grant && !hist_re[0]) hist_re_odd <= hist_raddr[8];
// if (!hist_out || (&hist_raddr[7:1])) hist_re_even_odd[0] <= 0;
// else if (hist_re[0]) hist_re_even_odd[0] <= ~hist_re_even_odd[0];
// else if (hist_grant) hist_re_even_odd[0] <= 1; // hist_re[0] == 0 here
if (!en_mclk) hist_bank_mclk <= 0;
// else if (hist_xfer_done_mclk && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_mclk <= !hist_bank_mclk; // Not applicable in this module
else if (hist_xfer_done_mclk) hist_bank_mclk <= !hist_bank_mclk;
if (hist_done_mclk) hist_bank_read <= !hist_bank_write; // it already changed
hist_dv <= hist_re[2];
end
always @ (posedge pclk) begin
if (!en) wait_readout <= 0;
// else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1; // Not applicable in this module
else if (hist_xfer_done) wait_readout <= 0;
end
......@@ -516,7 +505,7 @@ module sens_histogram_snglclk #(
.rst (prst), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (hist_done), // input
.in_pulse (hist_done[1]), // input // so hist_done[0] is over before hist_done_mclk started
.out_pulse (hist_done_mclk), // output
.busy() // output
);
......@@ -536,8 +525,8 @@ module sens_histogram_snglclk #(
if ((HISTOGRAM_RAM_MODE=="BUF32") || (HISTOGRAM_RAM_MODE=="NOBUF"))// impossible to use a two RAMB18E1 32-bit wide
sens_hist_ram_snglclk_32 sens_hist_ram_snglclk_32_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.addr_a_even ({hist_bank_write, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_write, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2), // input[31:0]
.data_out_a_even (hist_new_even), // output[31:0]
.data_out_a_odd (hist_new_odd), // output[31:0]
......@@ -548,7 +537,7 @@ module sens_histogram_snglclk #(
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.addr_b ({hist_bank_read,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
......@@ -556,8 +545,8 @@ module sens_histogram_snglclk #(
else if (HISTOGRAM_RAM_MODE=="BUF18")
sens_hist_ram_snglclk_18 sens_hist_ram_snglclk_18_i (
.pclk (pclk), // input
.addr_a_even ({hist_bank_pclk, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_pclk, hist_rwaddr_odd}), // input[9:0]
.addr_a_even ({hist_bank_write, hist_rwaddr_even}), // input[9:0]
.addr_a_odd ({hist_bank_write, hist_rwaddr_odd}), // input[9:0]
.data_in_a (r2[17:0]), // input[31:0]
.data_out_a_even (hist_new_even[17:0]), // output[31:0]
.data_out_a_odd (hist_new_odd[17:0]), // output[31:0]
......@@ -568,7 +557,7 @@ module sens_histogram_snglclk #(
.we_a_even (we_even), // input
.we_a_odd (we_odd), // input
.mclk (mclk), // input
.addr_b ({hist_bank_mclk,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.addr_b ({hist_bank_read,hist_raddr[9],hist_raddr[7:0]}), // input[9:0]
.data_out_b (hist_do), // output[31:0] reg
.re_even (hist_re_even), // input
.re_odd (hist_re_odd) // input
......@@ -576,7 +565,6 @@ module sens_histogram_snglclk #(
endgenerate
endmodule
module sens_hist_ram_snglclk_32(
......@@ -607,7 +595,8 @@ module sens_hist_ram_snglclk_32(
always @(posedge mclk) begin
re_even_d <= re_even;
re_odd_d <= re_odd;
odd <= re_odd;
// odd <= re_odd;
odd <= re_odd_d;
data_out_b <= odd ? data_out_b_w_odd : data_out_b_w_even;
end
......@@ -744,8 +733,12 @@ module sens_hist_ram_snglclk_18(
endmodule
module sens_histogram_snglclk_dummy(
module sens_histogram_snglclk_dummy #(
parameter NUM_FRAME_BITS = 4 // number of bits use for frame number
)(
output hist_rq,
output [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
output [31:0] hist_do,
output hist_dv
`ifdef DEBUG_RING
......@@ -756,6 +749,7 @@ module sens_histogram_snglclk_dummy(
assign hist_rq = 0;
assign hist_do = 0;
assign hist_dv = 0;
assign hist_frame = 0;
`ifdef DEBUG_RING
assign debug_do = debug_di;
`endif
......
sensor/sens_parallel12.v
View file @ 659e1009
......@@ -144,10 +144,6 @@ module sens_parallel12 #(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start // Acknowledge of the first status packet byte (address)
`ifdef DEBUG_HISTOGRAMS
,input [7:0] dbg_hist_data
`endif
);
// delaying vact and pxd by one clock cycle to match hact register
......@@ -251,13 +247,7 @@ module sens_parallel12 #(
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy,
`ifdef DEBUG_HISTOGRAMS
dbg_hist_data,
`else
ps_out,
`endif
xfpgatdo, senspgmin};
assign hact_out = hact_r;
......
sensor/sensor_channel.v
View file @ 659e1009
......@@ -294,68 +294,67 @@ module sensor_channel#(
) (
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
`ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
input mrst, // @posedge mclk, sync reset
input prst, // @posedge pclk, sync reset
// I/O pads, pin names match circuit diagram
`ifdef HISPI
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp,
input sns_clkn,
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp,
input sns_clkn,
`else
inout [7:0] sns_dp,
inout [7:0] sns_dn,
inout sns_clkp,
inout sns_clkn,
inout [7:0] sns_dp,
inout [7:0] sns_dn,
inout sns_clkp,
inout sns_clkn,
`endif
inout sns_scl,
inout sns_sda,
inout sns_scl,
inout sns_sda,
`ifdef HISPI
output sns_ctl,
output sns_ctl,
`else
inout sns_ctl,
inout sns_ctl,
`endif
inout sns_pg,
inout sns_pg,
// programming interface
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad_in, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb_in, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] cmd_ad_in, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb_in, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
input trigger_mode, // running in triggered mode (0 - free running mode)
input trig_in, // per-sensor trigger input
input trigger_mode, // running in triggered mode (0 - free running mode)
input trig_in, // per-sensor trigger input
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
// 16/8-bit mode data to memory (8-bits are packed by 2 in 16 mode @posedge pclk
output [15:0] dout, // @posedge pclk
output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off
output last_in_line, // valid with dout_valid - last in line dout
output [15:0] dout, // @posedge pclk
output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off
output last_in_line, // valid with dout_valid - last in line dout
output sof_out, // @pclk start of frame 1-clk pulse with the same delays as output data
output eof_out, // @pclk end of frame 1-clk pulse with the same delays as output data
output sof_out_mclk, // @mclk filtered, possibly decimated start of frame
output sof_late_mclk, // @mclk filtered, possibly decimated start of frame, delayed by specified number of lines
output sof_out, // @pclk start of frame 1-clk pulse with the same delays as output data
output eof_out, // @pclk end of frame 1-clk pulse with the same delays as output data
output sof_out_mclk, // @mclk filtered, possibly decimated start of frame
output sof_late_mclk, // @mclk filtered, possibly decimated start of frame, delayed by specified number of lines
// histogram interface to S_AXI, 256x32bit continuous bursts @posedge mclk, each histogram having 4 bursts
output hist_request, // request to transfer a burst
input hist_grant, // request to transfer over S_AXI granted
output [1:0] hist_chn, // output[1:0] histogram (sub) channel, valid with request and transfer
output hist_dvalid, // output data valid - active when sending a burst
output [31:0] hist_data // output[31:0] histogram data
output hist_request, // request to transfer a burst
output [NUM_FRAME_BITS-1:0] hist_frame,
input hist_grant, // request to transfer over S_AXI granted
output [1:0] hist_chn, // output[1:0] histogram (sub) channel, valid with request and transfer
output hist_dvalid, // output data valid - active when sending a burst
output [31:0] hist_data // output[31:0] histogram data
`ifdef DEBUG_RING
,output debug_do, // output to the debug ring
input debug_sl, // 0 - idle, (1,0) - shift, (1,1) - load
......@@ -394,94 +393,77 @@ module sensor_channel#(
localparam HISTOGRAM_ADDR3 = (SENSOR_NUM_HISTOGRAM > 3)?(SENSOR_BASE_ADDR + HISTOGRAM_RADDR3):-1; //
reg [7:0] cmd_ad; // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
reg cmd_stb; // strobe (with first byte) for the command a/d
reg [7:0] cmd_ad; // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
reg cmd_stb; // strobe (with first byte) for the command a/d
wire [7:0] sens_i2c_status_ad;
wire sens_i2c_status_rq;
wire sens_i2c_status_start;
wire [7:0] sens_phys_status_ad;
wire sens_phys_status_rq;
wire sens_phys_status_start;
wire [7:0] sens_i2c_status_ad;
wire sens_i2c_status_rq;
wire sens_i2c_status_start;
wire [7:0] sens_phys_status_ad;
wire sens_phys_status_rq;
wire sens_phys_status_start;
`ifndef HISPI
wire ipclk; // Use in FIFO
wire [11:0] pxd_to_fifo;
wire vact_to_fifo; // frame active @posedge ipclk
wire hact_to_fifo; // line active @posedge ipclk
wire ipclk; // Use in FIFO
wire [11:0] pxd_to_fifo;
wire vact_to_fifo; // frame active @posedge ipclk
wire hact_to_fifo; // line active @posedge ipclk
`endif
// data from FIFO
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
wire hact; // line active @posedge ipclk
wire sof; // start of frame
wire eof; // end of frame
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
wire hact; // line active @posedge ipclk
wire sof; // start of frame
wire eof; // end of frame
wire sof_out_sync; // sof filtetred, optionally decimated (for linescan mode)
wire sof_out_sync; // sof filtetred, optionally decimated (for linescan mode)
wire [15:0] lens_pxd_in;
wire lens_hact_in;
wire lens_sof_in;
wire lens_eof_in;
wire [15:0] lens_pxd_in;
wire lens_hact_in;
wire lens_sof_in;
wire lens_eof_in;
wire [15:0] gamma_pxd_in;
wire gamma_hact_in;
wire gamma_sof_in;
wire gamma_eof_in;
wire [1:0] gamma_bayer; // gamma module mode register bits -> lens_flat module
wire [15:0] gamma_pxd_in;
wire gamma_hact_in;
wire gamma_sof_in;
wire gamma_eof_in;
wire [1:0] gamma_bayer; // gamma module mode register bits -> lens_flat module
wire [7:0] gamma_pxd_out;
wire gamma_hact_out;
wire gamma_sof_out;
wire gamma_eof_out;
wire [7:0] gamma_pxd_out;
wire gamma_hact_out;
wire gamma_sof_out;
wire gamma_eof_out;
wire [31:0] sensor_ctrl_data;
wire sensor_ctrl_we;
// reg [SENSOR_MODE_WIDTH-1:0] mode;
reg [3:0] hist_en;
reg en_mclk; // enable this channel
wire en_pclk; // enable in pclk domain
reg [3:0] hist_nrst;
reg bit16; // 16-bit mode, 0 - 8 bit mode
wire [3:0] hist_rq;
wire [3:0] hist_gr;
wire [3:0] hist_dv;
wire [31:0] hist_do0;
wire [31:0] hist_do1;
wire [31:0] hist_do2;
wire [31:0] hist_do3;
reg [7:0] gamma_data_r;
reg [15:0] dout_r;
reg dav_8bit;
reg dav_r;
wire [15:0] dout_w;
wire dav_w;
wire trig;
reg sof_out_r;
reg eof_out_r;
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
`ifdef DEBUG_HISTOGRAMS
wire [7:0] dbg_hist_data;
wire [3:0] dbg_hist_data_hist;
reg [15:0] dbg_cntr;
// reg [1:0] dbg_cntr; // verion B4 - toggles
always @ (posedge pclk) begin
// if (prst) dbg_cntr <= 0;
// else
// if (sof_out_r) dbg_cntr <= dbg_cntr + 1;
if (hist_gr[0] && hist_rq[0]) dbg_cntr <= dbg_cntr + 1; // verion B4 - toggles
end
assign dbg_hist_data = {dbg_cntr[11], hist_en[0], hist_gr[0], hist_rq[0], dbg_hist_data_hist[3:0]};
// assign dbg_hist_data = {prst, hist_en[0], dbg_cntr, dbg_hist_data_hist[3:0]}; // verion B4
// .hist_en (hist_en[0]), // input
// .hist_rst (!hist_nrst[0]), // input
`endif
wire [31:0] sensor_ctrl_data;
wire sensor_ctrl_we;
reg [3:0] hist_en;
reg en_mclk; // enable this channel
wire en_pclk; // enable in pclk domain
reg [3:0] hist_nrst;
reg bit16; // 16-bit mode, 0 - 8 bit mode
wire [NUM_FRAME_BITS-1:0] hist_frame0;
wire [NUM_FRAME_BITS-1:0] hist_frame1;
wire [NUM_FRAME_BITS-1:0] hist_frame2;
wire [NUM_FRAME_BITS-1:0] hist_frame3;
wire [3:0] hist_rq;
wire [3:0] hist_gr;
wire [3:0] hist_dv;
wire [31:0] hist_do0;
wire [31:0] hist_do1;
wire [31:0] hist_do2;
wire [31:0] hist_do3;
reg [7:0] gamma_data_r;
reg [15:0] dout_r;
reg dav_8bit;
reg dav_r;
wire [15:0] dout_w;
wire dav_w;
wire trig;
reg sof_out_r;
reg eof_out_r;
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
// TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
assign lens_pxd_in = {pxd[11:0],4'b0};
......@@ -968,10 +950,6 @@ module sensor_channel#(
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start) // input
`ifdef DEBUG_HISTOGRAMS
, .dbg_hist_data (dbg_hist_data)
`endif
);
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
......@@ -1177,7 +1155,8 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1185,6 +1164,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1194,25 +1174,25 @@ module sensor_channel#(
.hist_en (hist_en[0]), // input
.hist_rst (!hist_nrst[0]), // input
.hist_rq (hist_rq[0]), // output
.hist_frame (hist_frame0), // output[3:0] reg
.hist_grant (hist_gr[0]), // input
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[1]) // input
`endif
`ifdef DEBUG_HISTOGRAMS
,.dbg_hist_data(dbg_hist_data_hist[3:0])
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_0_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_0_i (
.hist_rq (hist_rq[0]), // output
.hist_frame (hist_frame0), // output[3:0] reg
.hist_do (hist_do0), // output[31:0]
.hist_dv (hist_dv[0]) // output
`ifdef DEBUG_RING
......@@ -1282,7 +1262,9 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1290,6 +1272,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1299,6 +1282,7 @@ module sensor_channel#(
.hist_en (hist_en[1]), // input
.hist_rst (!hist_nrst[1]), // input
.hist_rq (hist_rq[1]), // output
.hist_frame (hist_frame1), // output[3:0] reg
.hist_grant (hist_gr[1]), // input
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]), // output
......@@ -1311,8 +1295,11 @@ module sensor_channel#(
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_1_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_1_i (
.hist_rq (hist_rq[1]), // output
.hist_frame (hist_frame1), // output[3:0] reg
.hist_do (hist_do1), // output[31:0]
.hist_dv (hist_dv[1]) // output
`ifdef DEBUG_RING
......@@ -1381,7 +1368,8 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
......@@ -1389,6 +1377,7 @@ module sensor_channel#(
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
......@@ -1398,6 +1387,7 @@ module sensor_channel#(
.hist_en (hist_en[2]), // input
.hist_rst (!hist_nrst[2]), // input
.hist_rq (hist_rq[2]), // output
.hist_frame (hist_frame2), // output[3:0] reg
.hist_grant (hist_gr[2]), // input
.hist_do (hist_do2), // output[31:0]
.hist_dv (hist_dv[2]), // output
......@@ -1410,10 +1400,13 @@ module sensor_channel#(
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_2_i (
.hist_rq(hist_rq[2]), // output
.hist_frame (hist_frame2), // output[3:0] reg
.hist_do(hist_do2), // output[31:0]
.hist_dv(hist_dv[2]) // output
`ifdef DEBUG_RING
,.debug_do (debug_ring[2]), // output
.debug_di (debug_ring[3]) // input
......@@ -1481,37 +1474,43 @@ module sensor_channel#(
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.XOR_HIST_BAYER (XOR_HIST_BAYER)
.XOR_HIST_BAYER (XOR_HIST_BAYER),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) sens_histogram_3_i (
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.hist_di (gamma_pxd_out), // input[7:0]
.bayer (gamma_bayer), // input[1:0]
.mclk (mclk), // input
.hist_en (hist_en[3]), // input
.hist_rst (!hist_nrst[3]), // input
.hist_rq (hist_rq[3]), // output
.hist_grant (hist_gr[3]), // input
.hist_do (hist_do3), // output[31:0]
.hist_dv (hist_dv[3]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
.mrst (mrst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.sof (gamma_sof_out), // input
.eof (gamma_eof_out), // input
.hact (gamma_hact_out), // input
.frame_num_seq (frame_num_seq), // input[3:0]
.hist_di (gamma_pxd_out), // input[7:0]
.bayer (gamma_bayer), // input[1:0]
.mclk (mclk), // input
.hist_en (hist_en[3]), // input
.hist_rst (!hist_nrst[3]), // input
.hist_rq (hist_rq[3]), // output
.hist_frame (hist_frame3), // output[3:0] reg
.hist_grant (hist_gr[3]), // input
.hist_do (hist_do3), // output[31:0]
.hist_dv (hist_dv[3]), // output
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb) // input
`ifdef DEBUG_RING
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
,.debug_do (debug_ring[3]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[4]) // input
`endif
);
else
sens_histogram_snglclk_dummy sens_histogram_3_i (
sens_histogram_snglclk_dummy #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_3_i (
.hist_rq(hist_rq[3]), // output
.hist_frame (hist_frame3), // output[3:0] reg
.hist_do(hist_do3), // output[31:0]
.hist_dv(hist_dv[3]) // output
`ifdef DEBUG_RING
......@@ -1522,30 +1521,37 @@ module sensor_channel#(
`endif
endgenerate
sens_histogram_mux sens_histogram_mux_i (
.mclk (mclk), // input
.en (|hist_nrst), // input
.rq0 (hist_rq[0]), // input
.grant0 (hist_gr[0]), // output
.dav0 (hist_dv[0]), // input
.din0 (hist_do0), // input[31:0]
.rq1 (hist_rq[1]), // input
.grant1 (hist_gr[1]), // output
.dav1 (hist_dv[1]), // input
.din1 (hist_do1), // input[31:0]
.rq2 (hist_rq[2]), // input
.grant2 (hist_gr[2]), // output
.dav2 (hist_dv[2]), // input
.din2 (hist_do2), // input[31:0]
.rq3 (hist_rq[3]), // input
.grant3 (hist_gr[3]), // output
.dav3 (hist_dv[3]), // input
.din3 (hist_do3), // input[31:0]
.rq (hist_request), // output
.grant (hist_grant), // input
.chn (hist_chn), // output[1:0]
.dv (hist_dvalid), // output
.dout (hist_data) // output[31:0]
sens_histogram_mux #(
.NUM_FRAME_BITS (NUM_FRAME_BITS)
) sens_histogram_mux_i (
.mclk (mclk), // input
.en (|hist_nrst), // input
.rq0 (hist_rq[0]), // input
.hist_frame0 (hist_frame0), // input[3:0]
.grant0 (hist_gr[0]), // output
.dav0 (hist_dv[0]), // input
.din0 (hist_do0), // input[31:0]
.rq1 (hist_rq[1]), // input
.hist_frame1 (hist_frame1), // input[3:0]
.grant1 (hist_gr[1]), // output
.dav1 (hist_dv[1]), // input
.din1 (hist_do1), // input[31:0]
.rq2 (hist_rq[2]), // input
.hist_frame2 (hist_frame2), // input[3:0]
.grant2 (hist_gr[2]), // output
.dav2 (hist_dv[2]), // input
.din2 (hist_do2), // input[31:0]
.rq3 (hist_rq[3]), // input
.hist_frame3 (hist_frame3), // input[3:0]
.grant3 (hist_gr[3]), // output
.dav3 (hist_dv[3]), // input
.din3 (hist_do3), // input[31:0]
.rq (hist_request), // output
.hist_frame (hist_frame), // input[3:0]
.grant (hist_grant), // input
.chn (hist_chn), // output[1:0]
.dv (hist_dvalid), // output
.dout (hist_data) // output[31:0]
);
......
sensor/sensors393.v
View file @ 659e1009
......@@ -456,6 +456,7 @@ module sensors393 #(
wire [127:0] hist_data;
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
......@@ -708,6 +709,8 @@ module sensors393 #(
.sof_out_mclk (sof_out_mclk[i]), // output
.sof_late_mclk(sof_late_mclk[i]), // output
.hist_request (hist_request[i]), // output
.hist_frame (hist_frame[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // output[3:0]
.hist_grant (hist_grant[i]), // input
.hist_chn (hist_chn[2 * i +: 2]), // output[1:0]
.hist_dvalid (hist_dvalid[i]), // output
......@@ -758,62 +761,61 @@ module sensors393 #(
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
) histogram_saxi_i (
// .rst (rst), // input
.mclk (mclk), // input
.aclk (aclk), // input
.mrst (mrst), // input
.arst (arst), // input
.frame0 (frame_num0), // input[3:0]
.hist_request0 (hist_request[0]), // input
.hist_grant0 (hist_grant[0]), // output
.hist_chn0 (hist_chn[0 * 2 +: 2]), // input[1:0]
.hist_dvalid0 (hist_dvalid[0]), // input
.hist_data0 (hist_data[0 * 32 +: 32]),// input[31:0]
.frame1 (frame_num1), // input[3:0]
.hist_request1 (hist_request[1]), // input
.hist_grant1 (hist_grant[1]), // output
.hist_chn1 (hist_chn[1 * 2 +: 2]), // input[1:0]
.hist_dvalid1 (hist_dvalid[1]), // input
.hist_data1 (hist_data[1 * 32 +: 32]),// input[31:0]
.frame2 (frame_num2), // input[3:0]
.hist_request2 (hist_request[2]), // input
.hist_grant2 (hist_grant[2]), // output
.hist_chn2 (hist_chn[2 * 2 +: 2]), // input[1:0]
.hist_dvalid2 (hist_dvalid[2]), // input
.hist_data2 (hist_data[2 * 32 +: 32]),// input[31:0]
.frame3 (frame_num3), // input[3:0]
.hist_request3 (hist_request[3]), // input
.hist_grant3 (hist_grant[3]), // output
.hist_chn3 (hist_chn[3 * 2 +: 2]), // input[1:0]
.hist_dvalid3 (hist_dvalid[3]), // input
.hist_data3 (hist_data[3 * 32 +: 32]),// input[31:0]
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.saxi_awaddr (saxi_awaddr), // output[31:0]
.saxi_awvalid (saxi_awvalid), // output
.saxi_awready (saxi_awready), // input
.saxi_awid (saxi_awid), // output[5:0]
.saxi_awlock (saxi_awlock), // output[1:0]
.saxi_awcache (saxi_awcache), // output[3:0]
.saxi_awprot (saxi_awprot), // output[2:0]
.saxi_awlen (saxi_awlen), // output[3:0]
.saxi_awsize (saxi_awsize), // output[1:0]
.saxi_awburst (saxi_awburst), // output[1:0]
.saxi_awqos (saxi_awqos), // output[3:0]
.saxi_wdata (saxi_wdata), // output[31:0]
.saxi_wvalid (saxi_wvalid), // output
.saxi_wready (saxi_wready), // input
.saxi_wid (saxi_wid), // output[5:0]
.saxi_wlast (saxi_wlast), // output
.saxi_wstrb (saxi_wstrb), // output[3:0]
.saxi_bvalid (saxi_bvalid), // input
.saxi_bready (saxi_bready), // output
.saxi_bid (saxi_bid), // input[5:0]
.saxi_bresp (saxi_bresp) // input[1:0]
.mclk (mclk), // input
.aclk (aclk), // input
.mrst (mrst), // input
.arst (arst), // input
.frame0 (hist_frame[NUM_FRAME_BITS*0 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request0 (hist_request[0]), // input
.hist_grant0 (hist_grant[0]), // output
.hist_chn0 (hist_chn[0 * 2 +: 2]), // input[1:0]
.hist_dvalid0 (hist_dvalid[0]), // input
.hist_data0 (hist_data[0 * 32 +: 32]), // input[31:0]
.frame1 (hist_frame[NUM_FRAME_BITS*1 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request1 (hist_request[1]), // input
.hist_grant1 (hist_grant[1]), // output
.hist_chn1 (hist_chn[1 * 2 +: 2]), // input[1:0]
.hist_dvalid1 (hist_dvalid[1]), // input
.hist_data1 (hist_data[1 * 32 +: 32]), // input[31:0]
.frame2 (hist_frame[NUM_FRAME_BITS*2 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request2 (hist_request[2]), // input
.hist_grant2 (hist_grant[2]), // output
.hist_chn2 (hist_chn[2 * 2 +: 2]), // input[1:0]
.hist_dvalid2 (hist_dvalid[2]), // input
.hist_data2 (hist_data[2 * 32 +: 32]), // input[31:0]
.frame3 (hist_frame[NUM_FRAME_BITS*3 +:NUM_FRAME_BITS]), // input[3:0]
.hist_request3 (hist_request[3]), // input
.hist_grant3 (hist_grant[3]), // output
.hist_chn3 (hist_chn[3 * 2 +: 2]), // input[1:0]
.hist_dvalid3 (hist_dvalid[3]), // input
.hist_data3 (hist_data[3 * 32 +: 32]), // input[31:0]
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.saxi_awaddr (saxi_awaddr), // output[31:0]
.saxi_awvalid (saxi_awvalid), // output
.saxi_awready (saxi_awready), // input
.saxi_awid (saxi_awid), // output[5:0]
.saxi_awlock (saxi_awlock), // output[1:0]
.saxi_awcache (saxi_awcache), // output[3:0]
.saxi_awprot (saxi_awprot), // output[2:0]
.saxi_awlen (saxi_awlen), // output[3:0]
.saxi_awsize (saxi_awsize), // output[1:0]
.saxi_awburst (saxi_awburst), // output[1:0]
.saxi_awqos (saxi_awqos), // output[3:0]
.saxi_wdata (saxi_wdata), // output[31:0]
.saxi_wvalid (saxi_wvalid), // output
.saxi_wready (saxi_wready), // input
.saxi_wid (saxi_wid), // output[5:0]
.saxi_wlast (saxi_wlast), // output
.saxi_wstrb (saxi_wstrb), // output[3:0]
.saxi_bvalid (saxi_bvalid), // input
.saxi_bready (saxi_bready), // output
.saxi_bid (saxi_bid), // input[5:0]
.saxi_bresp (saxi_bresp) // input[1:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[4]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[5]) // input
,.debug_do (debug_ring[4]), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[5]) // input
`endif
);
......
simulation_modules/simul_sensor12bits.v
View file @ 659e1009
......@@ -170,8 +170,9 @@ initial begin
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "HIST_TEST") $readmemh({`ROOTPATH,"/input_data/sensor_hist_test.dat"},sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
......
x393_parallel.bit
View file @ 659e1009
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