Commit 64ff56ce authored by Andrey Filippov's avatar Andrey Filippov

adjusting constraint attributes in the source

parent 8b0a0f11
...@@ -62,77 +62,77 @@ ...@@ -62,77 +62,77 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722180528066.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150723174740723.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722180528066.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722181016920.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722180528066.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150723175509485.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722181016920.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150723175509485.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-place.dcp</name> <name>vivado_state/x393-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150722181016920.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-place-20150723175509485.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150722181016920.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20150723175509485.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722180528066.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20150723174740723.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
...@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none ...@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@-> VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@-> com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
This diff is collapsed.
...@@ -436,7 +436,7 @@ module cmd_encod_linear_mux#( ...@@ -436,7 +436,7 @@ module cmd_encod_linear_mux#(
; ;
`ifdef def_scanline_chn0 `ifdef def_scanline_chn0
wire start0=0 | wire start0=0
`ifdef def_read_mem_chn0 `ifdef def_read_mem_chn0
| start0_rd | start0_rd
`endif `endif
...@@ -446,7 +446,7 @@ module cmd_encod_linear_mux#( ...@@ -446,7 +446,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn1 `ifdef def_scanline_chn1
wire start1=0 | wire start1=0
`ifdef def_read_mem_chn1 `ifdef def_read_mem_chn1
| start1_rd | start1_rd
`endif `endif
...@@ -456,7 +456,7 @@ module cmd_encod_linear_mux#( ...@@ -456,7 +456,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn2 `ifdef def_scanline_chn2
wire start2=0 | wire start2=0
`ifdef def_read_mem_chn2 `ifdef def_read_mem_chn2
| start2_rd | start2_rd
`endif `endif
...@@ -466,7 +466,7 @@ module cmd_encod_linear_mux#( ...@@ -466,7 +466,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn3 `ifdef def_scanline_chn3
wire start3=0 | wire start3=0
`ifdef def_read_mem_chn3 `ifdef def_read_mem_chn3
| start3_rd | start3_rd
`endif `endif
...@@ -476,7 +476,7 @@ module cmd_encod_linear_mux#( ...@@ -476,7 +476,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn4 `ifdef def_scanline_chn4
wire start4=0 | wire start4=0
`ifdef def_read_mem_chn4 `ifdef def_read_mem_chn4
| start4_rd | start4_rd
`endif `endif
...@@ -486,7 +486,7 @@ module cmd_encod_linear_mux#( ...@@ -486,7 +486,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn5 `ifdef def_scanline_chn5
wire start5=0 | wire start5=0
`ifdef def_read_mem_chn5 `ifdef def_read_mem_chn5
| start5_rd | start5_rd
`endif `endif
...@@ -496,7 +496,7 @@ module cmd_encod_linear_mux#( ...@@ -496,7 +496,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn6 `ifdef def_scanline_chn6
wire start6=0 | wire start6=0
`ifdef def_read_mem_chn6 `ifdef def_read_mem_chn6
| start6_rd | start6_rd
`endif `endif
...@@ -506,7 +506,7 @@ module cmd_encod_linear_mux#( ...@@ -506,7 +506,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn7 `ifdef def_scanline_chn7
wire start7=0 | wire start7=0
`ifdef def_read_mem_chn7 `ifdef def_read_mem_chn7
| start7_rd | start7_rd
`endif `endif
...@@ -516,7 +516,7 @@ module cmd_encod_linear_mux#( ...@@ -516,7 +516,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn8 `ifdef def_scanline_chn8
wire start8=0 | wire start8=0
`ifdef def_read_mem_chn8 `ifdef def_read_mem_chn8
| start8_rd | start8_rd
`endif `endif
...@@ -526,7 +526,7 @@ module cmd_encod_linear_mux#( ...@@ -526,7 +526,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn9 `ifdef def_scanline_chn9
wire start9=0 | wire start9=0
`ifdef def_read_mem_chn9 `ifdef def_read_mem_chn9
| start9_rd | start9_rd
`endif `endif
...@@ -536,7 +536,7 @@ module cmd_encod_linear_mux#( ...@@ -536,7 +536,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn10 `ifdef def_scanline_chn10
wire start10=0 | wire start10=0
`ifdef def_read_mem_chn10 `ifdef def_read_mem_chn10
| start10_rd | start10_rd
`endif `endif
...@@ -546,7 +546,7 @@ module cmd_encod_linear_mux#( ...@@ -546,7 +546,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn11 `ifdef def_scanline_chn11
wire start11=0 | wire start11=0
`ifdef def_read_mem_chn11 `ifdef def_read_mem_chn11
| start11_rd | start11_rd
`endif `endif
...@@ -556,7 +556,7 @@ module cmd_encod_linear_mux#( ...@@ -556,7 +556,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn12 `ifdef def_scanline_chn12
wire start12=0 | wire start12=0
`ifdef def_read_mem_chn12 `ifdef def_read_mem_chn12
| start12_rd | start12_rd
`endif `endif
...@@ -566,7 +566,7 @@ module cmd_encod_linear_mux#( ...@@ -566,7 +566,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn13 `ifdef def_scanline_chn13
wire start13=0 | wire start13=0
`ifdef def_read_mem_chn13 `ifdef def_read_mem_chn13
| start13_rd | start13_rd
`endif `endif
...@@ -576,7 +576,7 @@ module cmd_encod_linear_mux#( ...@@ -576,7 +576,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn14 `ifdef def_scanline_chn14
wire start14=0 | wire start14=0
`ifdef def_read_mem_chn14 `ifdef def_read_mem_chn14
| start14_rd | start14_rd
`endif `endif
...@@ -586,7 +586,7 @@ module cmd_encod_linear_mux#( ...@@ -586,7 +586,7 @@ module cmd_encod_linear_mux#(
; ;
`endif `endif
`ifdef def_scanline_chn15 `ifdef def_scanline_chn15
wire start15=0 | wire start15=0
`ifdef def_read_mem_chn15 `ifdef def_read_mem_chn15
| start15_rd | start15_rd
`endif `endif
......
...@@ -539,7 +539,7 @@ module cmd_encod_tiled_mux #( ...@@ -539,7 +539,7 @@ module cmd_encod_tiled_mux #(
; ;
`ifdef def_tiled_chn0 `ifdef def_tiled_chn0
wire start0=0 | wire start0=0
`ifdef def_read_mem_chn0 `ifdef def_read_mem_chn0
| start0_rd | start0_rd32 | start0_rd | start0_rd32
`endif `endif
...@@ -549,7 +549,7 @@ module cmd_encod_tiled_mux #( ...@@ -549,7 +549,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn1 `ifdef def_tiled_chn1
wire start1=0 | wire start1=0
`ifdef def_read_mem_chn1 `ifdef def_read_mem_chn1
| start1_rd | start1_rd32 | start1_rd | start1_rd32
`endif `endif
...@@ -559,7 +559,7 @@ module cmd_encod_tiled_mux #( ...@@ -559,7 +559,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn2 `ifdef def_tiled_chn2
wire start2=0 | wire start2=0
`ifdef def_read_mem_chn2 `ifdef def_read_mem_chn2
| start2_rd | start2_rd32 | start2_rd | start2_rd32
`endif `endif
...@@ -569,7 +569,7 @@ module cmd_encod_tiled_mux #( ...@@ -569,7 +569,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn3 `ifdef def_tiled_chn3
wire start3=0 | wire start3=0
`ifdef def_read_mem_chn3 `ifdef def_read_mem_chn3
| start3_rd | start3_rd32 | start3_rd | start3_rd32
`endif `endif
...@@ -579,7 +579,7 @@ module cmd_encod_tiled_mux #( ...@@ -579,7 +579,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn4 `ifdef def_tiled_chn4
wire start4=0 | wire start4=0
`ifdef def_read_mem_chn4 `ifdef def_read_mem_chn4
| start4_rd | start4_rd32 | start4_rd | start4_rd32
`endif `endif
...@@ -589,7 +589,7 @@ module cmd_encod_tiled_mux #( ...@@ -589,7 +589,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn5 `ifdef def_tiled_chn5
wire start5=0 | wire start5=0
`ifdef def_read_mem_chn5 `ifdef def_read_mem_chn5
| start5_rd | start5_rd32 | start5_rd | start5_rd32
`endif `endif
...@@ -599,7 +599,7 @@ module cmd_encod_tiled_mux #( ...@@ -599,7 +599,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn6 `ifdef def_tiled_chn6
wire start6=0 | wire start6=0
`ifdef def_read_mem_chn6 `ifdef def_read_mem_chn6
| start6_rd | start6_rd32 | start6_rd | start6_rd32
`endif `endif
...@@ -609,7 +609,7 @@ module cmd_encod_tiled_mux #( ...@@ -609,7 +609,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn7 `ifdef def_tiled_chn7
wire start7=0 | wire start7=0
`ifdef def_read_mem_chn7 `ifdef def_read_mem_chn7
| start7_rd | start7_rd32 | start7_rd | start7_rd32
`endif `endif
...@@ -619,7 +619,7 @@ module cmd_encod_tiled_mux #( ...@@ -619,7 +619,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn8 `ifdef def_tiled_chn8
wire start8=0 | wire start8=0
`ifdef def_read_mem_chn8 `ifdef def_read_mem_chn8
| start8_rd | start8_rd32 | start8_rd | start8_rd32
`endif `endif
...@@ -629,7 +629,7 @@ module cmd_encod_tiled_mux #( ...@@ -629,7 +629,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn9 `ifdef def_tiled_chn9
wire start9=0 | wire start9=0
`ifdef def_read_mem_chn9 `ifdef def_read_mem_chn9
| start9_rd | start9_rd32 | start9_rd | start9_rd32
`endif `endif
...@@ -639,7 +639,7 @@ module cmd_encod_tiled_mux #( ...@@ -639,7 +639,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn10 `ifdef def_tiled_chn10
wire start10=0 | wire start10=0
`ifdef def_read_mem_chn10 `ifdef def_read_mem_chn10
| start10_rd | start10_rd32 | start10_rd | start10_rd32
`endif `endif
...@@ -649,7 +649,7 @@ module cmd_encod_tiled_mux #( ...@@ -649,7 +649,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn11 `ifdef def_tiled_chn11
wire start11=0 | wire start11=0
`ifdef def_read_mem_chn11 `ifdef def_read_mem_chn11
| start11_rd | start11_rd32 | start11_rd | start11_rd32
`endif `endif
...@@ -659,7 +659,7 @@ module cmd_encod_tiled_mux #( ...@@ -659,7 +659,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn12 `ifdef def_tiled_chn12
wire start12=0 | wire start12=0
`ifdef def_read_mem_chn12 `ifdef def_read_mem_chn12
| start12_rd | start12_rd32 | start12_rd | start12_rd32
`endif `endif
...@@ -669,7 +669,7 @@ module cmd_encod_tiled_mux #( ...@@ -669,7 +669,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn13 `ifdef def_tiled_chn13
wire start13=0 | wire start13=0
`ifdef def_read_mem_chn13 `ifdef def_read_mem_chn13
| start13_rd | start13_rd32 | start13_rd | start13_rd32
`endif `endif
...@@ -679,7 +679,7 @@ module cmd_encod_tiled_mux #( ...@@ -679,7 +679,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn14 `ifdef def_tiled_chn14
wire start14=0 | wire start14=0
`ifdef def_read_mem_chn14 `ifdef def_read_mem_chn14
| start14_rd | start14_rd32 | start14_rd | start14_rd32
`endif `endif
...@@ -689,7 +689,7 @@ module cmd_encod_tiled_mux #( ...@@ -689,7 +689,7 @@ module cmd_encod_tiled_mux #(
; ;
`endif `endif
`ifdef def_tiled_chn15 `ifdef def_tiled_chn15
wire start15=0 | wire start15=0
`ifdef def_read_mem_chn15 `ifdef def_read_mem_chn15
| start15_rd | start15_rd32 | start15_rd | start15_rd32
`endif `endif
......
...@@ -96,7 +96,10 @@ module mcntrl_linear_rw #( ...@@ -96,7 +96,10 @@ module mcntrl_linear_rw #(
// WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_linear_rw.v:268] // WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_linear_rw.v:268]
// Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
// outside of the DSP 48. "dont_touch" seems to work here // outside of the DSP 48. "dont_touch" seems to work here
(* keep = "true" *) reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top `ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler) reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
......
...@@ -110,7 +110,10 @@ module mcntrl_tiled_rw#( ...@@ -110,7 +110,10 @@ module mcntrl_tiled_rw#(
//WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_rw.v:307] //WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_rw.v:307]
// Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
// outside of the DSP 48. "dont_touch" seems to work here // outside of the DSP 48. "dont_touch" seems to work here
(* keep = "true" *) reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top `ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler) reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
......
...@@ -55,15 +55,26 @@ module byte_lane #( ...@@ -55,15 +55,26 @@ module byte_lane #(
input set // clk_div synchronous set all delays from previously loaded values input set // clk_div synchronous set all delays from previously loaded values
); );
//(* CLOCK_DEDICATED_ROUTE = "FALSE" *) // does not seem to work
wire dqs_read; wire dqs_read;
wire iclk; // source-synchronous clock (BUFR from DQS) wire iclk; // source-synchronous clock (BUFR from DQS)
reg [31:0] din_r=0; reg [31:0] din_r=0;
// Preventing register removal of equivalent registers // Preventing register removal of equivalent registers
(* keep = "true" *) reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf; `ifndef IGNORE_ATTR
(* keep = "true" *) reg [7:0] dly_data_r=0; (* keep = "true" *)
(* keep = "true" *) reg set_r=0; `endif
(* keep = "true" *) reg dci_disable_dqs_r, dci_disable_dq_r; reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
`ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg [7:0] dly_data_r=0;
`ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg set_r=0;
`ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg dci_disable_dqs_r, dci_disable_dq_r;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0; reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm; reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
......
...@@ -61,8 +61,14 @@ reg [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2 ...@@ -61,8 +61,14 @@ reg [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2
//reg [1:0] in_tri_r=2'h0; // or tri-state on reset? //reg [1:0] in_tri_r=2'h0; // or tri-state on reset?
reg in_tri_r=1'b1; // or tri-state on reset? reg in_tri_r=1'b1; // or tri-state on reset?
// Preventing register duplication // Preventing register duplication
(* keep = "true" *) reg [7:0] dly_data_r=0; `ifndef IGNORE_ATTR
(* keep = "true" *) reg set_r=0; (* keep = "true" *)
`endif
reg [7:0] dly_data_r=0;
`ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg set_r=0;
reg [7:0] ld_dly_cmd=8'b0; reg [7:0] ld_dly_cmd=8'b0;
reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0; reg [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
//wire [ADDRESS_NUMBER-1:0] decode_addr; //wire [ADDRESS_NUMBER-1:0] decode_addr;
......
...@@ -51,7 +51,6 @@ wire dq_tri; ...@@ -51,7 +51,6 @@ wire dq_tri;
wire dq_data_dly; wire dq_data_dly;
wire dq_dly; wire dq_dly;
// keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same // keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
//(* keep = "true" *)
wire dq_di; wire dq_di;
......
...@@ -5,6 +5,8 @@ ...@@ -5,6 +5,8 @@
`define SHREG_SEQUENTIAL_RESET 1 `define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch // synthesis does to recognize global clock as G input of the primitive latch
`undef INFER_LATCHES `undef INFER_LATCHES
// define when using CDC - it does not support them
`undef IGNORE_ATTR
//`define MEMBRIDGE_DEBUG_READ 1 //`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1 `define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1 `define USE_CMD_ENCOD_TILED_32_RD 1
......
...@@ -28,11 +28,77 @@ module level_cross_clocks#( ...@@ -28,11 +28,77 @@ module level_cross_clocks#(
input [WIDTH-1:0] d_in, input [WIDTH-1:0] d_in,
output [WIDTH-1:0] d_out output [WIDTH-1:0] d_out
); );
generate
genvar i;
for (i = 0; i < WIDTH ; i = i+1) begin: level_cross_clock_block
if (REGISTER <= 1)
level_cross_clocks_ff_bit level_cross_clocks_single_i ( // just a single ff (if metastability is not a problem)
.clk (clk), // input
.d_in (d_in[i]), // input
.d_out (d_out[i]) // output
);
else if (REGISTER == 2)
level_cross_clocks_sync_bit level_cross_clocks_sync_i ( // classic 2-register synchronizer
.clk (clk), // input
.d_in (d_in[i]), // input
.d_out (d_out[i]) // output
);
else
level_cross_clocks_single_bit #( // >2 bits (first two only are synchronizer)
.REGISTER(REGISTER)
) level_cross_clocks_single_i (
.clk (clk), // input
.d_in (d_in[i]), // input
.d_out (d_out[i]) // output
);
end
endgenerate
endmodule
module level_cross_clocks_single_bit#(
parameter REGISTER = 3 // number of registers (>3)
)(
input clk,
input d_in,
output d_out
);
reg [REGISTER - 3 : 0] regs;
wire d_sync; // after a 2-bit synchronizer
assign d_out = regs[REGISTER -3];
always @ (posedge clk) begin
regs <= (regs << 1) + d_sync; // | d_in complains about widths mismatch
end
level_cross_clocks_sync_bit level_cross_clocks_sync_bit_i (
.clk (clk), // input
.d_in (d_in), // input
.d_out (d_sync) // output
);
endmodule
reg [WIDTH * REGISTER -1 : 0] regs; // Classic 2-bit (exactly) synchronizer
assign d_out = regs [WIDTH-1:0];