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Commit 609af175 authored by Andrey Filippov's avatar Andrey Filippov
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merged with lwir

parents 955c964c d6956f19
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cocotb/x393_cocotb_03.sav
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compressor_jp/bit_stuffer_raw_metadata.v 0 → 100644
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compressor_jp/cmprs_buf_average.v
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......@@ -66,7 +66,7 @@ module cmprs_buf_average#(
input [ 7:0] caddrw,
input cwe,
input [ 8:0] signed_c,
output [ 9:0] do, // [9:0] data out (4:2:0) (signed, average=0)
output [ 9:0] dout, // [9:0] data out (4:2:0) (signed, average=0)
// When is it valid?
output [ 8:0] avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!
output dv, // out data valid (will go high for at least 64 cycles)
......@@ -170,7 +170,7 @@ module cmprs_buf_average#(
// assign output signals
assign avr = avr_r; // avermem[avr_ra[3:0]];
assign do = do_r;
assign dout = do_r;
assign tn[2:0] = raddr[8:6];
// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)
assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};
......
compressor_jp/cmprs_cmd_decode.v
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compressor_jp/cmprs_frame_sync.v
View file @ 609af175
......@@ -45,7 +45,6 @@ module cmprs_frame_sync#(
parameter CMPRS_TIMEOUT= 1000 // mclk cycles
)(
// input rst,
input xclk, // global clock input, compressor single clock rate
input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset
......@@ -88,7 +87,7 @@ module cmprs_frame_sync#(
output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk
// stuffer will re-clock and extract 0->1 transition
output stuffer_running_mclk,
output reading_frame,
output reading_frame, // @mclk
output frame_started_mclk // use to store frame number
);
/*
......@@ -101,8 +100,6 @@ module cmprs_frame_sync#(
TODO: Simplify logic: instead of frame_start_pend_r - copy frame_number_srtc @ vsync_late, and start frame if it is not reading,
in "run" mode, and frame_number_differ (in multi-frame mode)
*/
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire frame_started_mclk;
reg bonded_mode;
reg [5:0] frame_start_dst_r;
reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late
......@@ -111,14 +108,12 @@ module cmprs_frame_sync#(
reg line_numbers_sync; // src unfinished line number is > this unfinished line number
reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame
// reg broken_frame;
reg aborted_frame;
reg stuffer_running_mclk_r;
reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0;
reg cmprs_en_d;
reg suspend_end; // suspend at the end of the current frame until frame number changes
// reg cmprs_en_xclk;
wire last_mb_started_mclk;
assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r;
......@@ -126,9 +121,6 @@ module cmprs_frame_sync#(
assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r;
// always @ (posedge xclk) begin
// cmprs_en_xclk <=cmprs_en;
// end
always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1;
......@@ -145,28 +137,18 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en;
// broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
// else if (broken_frame || aborted_frame) force_flush_long <= 1;
else if (aborted_frame) force_flush_long <= 1;
// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
// last_mb_start[2] is used as emergency turn off reading_frame if memory channel did not generate frame_done (i.e. wrong frame height)
// TODO: Consider the opposite - frame_done, but not got the last MB?
if (!cmprs_en || frame_done || last_mb_started_mclk) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1;
// if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0;
if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
else if ((cmprs_run && vsync_late && reading_frame_r) ||
(frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
// else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
// If started frame differs from tghe source one, needs to comrfess next frame after this is done, without vsync_late
// else if (frame_start_dst_r[5] ) frame_start_pend_r <= bonded_mode && frames_numbers_differ;
// if (!cmprs_en) suspend_end <= 0;
if (!cmprs_run) suspend_end <= 0;
else if (frame_done) suspend_end <= 1;
else if (frame_start_dst_r[3]) suspend_end <= 0;
......@@ -176,7 +158,6 @@ module cmprs_frame_sync#(
cmprs_standalone);
// modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed
if (!cmprs_en) frame_start_dst_r[5:1] <=0;
// else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];
else frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf};
if (!cmprs_en) bonded_mode <= 0;
......@@ -188,14 +169,12 @@ module cmprs_frame_sync#(
frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented
/// line_numbers_sync <= (line_unfinished_src > line_unfinished);
line_numbers_sync <= (line_unfinished_src >= line_unfinished);
suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync));
end
// pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy());
......
compressor_jp/cmprs_pixel_buf_iface.v
View file @ 609af175
......@@ -117,7 +117,6 @@ module cmprs_pixel_buf_iface #(
reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
reg [ 5:0] extra_start_addr_r;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign buf_ra = bufa_r;
......@@ -130,7 +129,6 @@ module cmprs_pixel_buf_iface #(
assign mb_pre_end = mb_pre_end_r;
assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0];
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1];
`ifdef DEBUG_COMPRESSOR_SCRAMBLE
......@@ -147,7 +145,6 @@ module cmprs_pixel_buf_iface #(
`endif
always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
extra_start_addr_r <= extra_start_addr_w[5:0];
mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
......@@ -164,10 +161,6 @@ module cmprs_pixel_buf_iface #(
//mb_pre_start
if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if (mb_pre_start) rows_left <= mb_h_m1;
else if (last_col) rows_left <= rows_left - 1;
......@@ -177,17 +170,14 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;
// if (buf_re[0]) last_col <= 0; // ????
if (!buf_re[0]) last_col <= 0;
else last_col <= (cols_left == 1);
// if (buf_re[0]) last_row <= 0;
if (!buf_re[0]) last_row <= 0;
else if (last_col) last_row <= (rows_left == 1);
first_col <= (mb_pre_start || (last_col && !last_row));
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
......@@ -207,7 +197,6 @@ module cmprs_pixel_buf_iface #(
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa;
......
compressor_jp/cmprs_raw_buf_iface.v 0 → 100644
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compressor_jp/compressor393.v
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......@@ -78,6 +78,8 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
......@@ -100,6 +102,7 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
......@@ -107,7 +110,8 @@ module compressor393 # (
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
......@@ -372,6 +376,8 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
......@@ -392,12 +398,14 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_CMODE_RAW (CMPRS_CBIT_CMODE_RAW),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_RAW (CMPRS_RAW),
.CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
......
compressor_jp/encoderDCAC393.v
View file @ 609af175
......@@ -53,7 +53,7 @@ module encoderDCAC393(
input first_blockz, // first block input (@zds)
input zds, // strobe - one ahead of the DC component output
output reg last, //
output reg [15:0] do,
output reg [15:0] dout,
output reg dv,
// just for debug
output comp_lastinmbo,
......@@ -132,7 +132,7 @@ module encoderDCAC393(
(cntr[5:0]==6'h3f),
ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
if (pre_dv) dout <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0;
......
compressor_jp/focus_sharp393.v
View file @ 609af175
......@@ -59,7 +59,7 @@ module focus_sharp393(
input quant_ds, // quantizator ds
input [12:0] quant_d, // [11:0]quantizator data output
input [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)
output reg [12:0] do, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg [12:0] dout, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg ds, // data out strobe (one ahead of the start of dv)
output reg [31:0] hifreq); //[31:0]) // accumulated high frequency components in a frame sub-window
......@@ -248,7 +248,7 @@ module focus_sharp393(
ds <= pre_ds;
pre_do[12:0] <= next_do[12:0];
need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);
do[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
dout[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
{2'b0,quant_dc_tdo[15:5]} :
pre_do[12:0];
end
......
compressor_jp/huffman_stuffer_meta.v
View file @ 609af175
......@@ -4,7 +4,7 @@
* @date 2015-10-26
* @author Andrey Filippov
*
* @brief Wrapper fior several JPEG/JP4 compression modules. It includes
* @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape)
......@@ -66,7 +66,8 @@ module huffman_stuffer_meta(
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
//TODO: Should be generated fro raw also
input color_first, // @fradv_clk only used for timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
......@@ -154,7 +155,8 @@ module huffman_stuffer_meta(
.flush_out (escape_flush_out) // output reg
);
bit_stuffer_metadata bit_stuffer_metadata_i (
// TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
......
compressor_jp/huffman_stuffer_raw_meta.v 0 → 100644
View file @ 609af175
/*!
* <b>Module:</b>huffman_stuffer_raw_meta
* @file huffman_stuffer_raw_meta.v
* @date 2015-10-26
* @author Andrey Filippov
*
* @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape)
* - inserts meta-data (timestamp and data length) (bit_stuffer_metadata)
*
* This is a "new" (made for x393 project) part of the JPEG/JP4 comressor
* that eliminates use of the double frequency clock.
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* huffman_stuffer_raw_meta.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_stuffer_raw_meta.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module huffman_stuffer_raw_meta(
input mclk, // system clock to write tables
input mrst,
input xclk, // pixel clock, sync to incoming data
input en_huffman, // @xclk
input en_stuffer, // @xclk
input abort_stuffer, // @ any, valid ffor raw also
// Interface to program Huffman tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
//TODO: Should be generated for raw also
input color_first, // @fradv_clk only used for timestamp
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
input raw_start, // single-cycle set "running"
input raw_prefb, // 1 cycle before sequence of 4 bytes
input raw_ts_copy, // single-cycle copy timestamp (some time before flush)
input raw_flush, // flush remaining data, length and timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
output [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
wire [26:0] huffman_do27;
wire [4:0] huffman_dl;
wire huffman_dv;
wire huffman_flush;
wire huffman_last_block;
wire [31:0] stuffer_do32;
wire [1:0] stuffer_bytes;
wire stuffer_dv;
wire stuffer_flush_out;
wire [31:0] escape_do32;
wire [1:0] escape_bytes;
wire escape_dv;
wire escape_flush_out;
huffman_snglclk huffman_snglclk_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.mclk (mclk), // input
.tser_we (tser_we), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (di), // input[15:0]
.ds (ds), // input
.do27 (huffman_do27), // output[26:0]
.dl (huffman_dl), // output[4:0]
.dv (huffman_dv), // output
.flush (huffman_flush), // output
.last_block (huffman_last_block), // output
`ifdef DEBUG_RING
.test_lbw (test_lbw),
.gotLastBlock (gotLastBlock), // last block done - flush the rest bits
`else
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
bit_stuffer_27_32 #(
.DIN_LEN(27)
) bit_stuffer_27_32_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (huffman_do27), // input[26:0]
.dlen (huffman_dl), // input[4:0]
.ds (huffman_dv), // input
.flush_in (huffman_flush), // input
.d_out (stuffer_do32), // output[31:0]
.bytes_out (stuffer_bytes), // output[1:0] reg
.dv (stuffer_dv), // output reg
.flush_out (stuffer_flush_out) // output reg
);
bit_stuffer_escape bit_stuffer_escape_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (stuffer_do32), // input[31:0]
.bytes_in (stuffer_bytes), // input[1:0]
.in_stb (stuffer_dv), // input
.flush_in (stuffer_flush_out), // input
.d_out (escape_do32), // output[31:0] reg
.bytes_out (escape_bytes), // output[1:0] reg
.dv (escape_dv), // output reg
.flush_out (escape_flush_out) // output reg
);
// TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.xrst (~en_stuffer), // input
.last_block (huffman_last_block), // input TODO: leading edge is needed for raw (to xfer timestamp) - not anymore
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input
.din (escape_do32), // input[31:0]
.bytes_in (escape_bytes), // input[1:0]
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.compressed_mode(compressed_mode), // input
.raw_mode (raw_mode), // input
.raw_be16 (raw_be16), // input
.raw_bytes (raw_bytes), // input[7:0]
.raw_start (raw_start), // input
.raw_prefb (raw_prefb), // input
.raw_ts_copy (raw_ts_copy), // input
.raw_flush (raw_flush), // input
.data_out (data_out), // output[31:0] reg
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
compressor_jp/jp_channel.v
View file @ 609af175
This diff is collapsed.
compressor_jp/quantizer393.v
View file @ 609af175
......@@ -58,7 +58,7 @@ module quantizer393(
input first_in, // first block in (valid @ start)
output reg first_out, // valid @ ds
input [12:0] di, // [11:0] pixel data in (signed)
output reg [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output reg [12:0] dout, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output dv, // data out valid
output ds, // data out strobe (one ahead of the start of dv)
output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
......@@ -157,13 +157,11 @@ module quantizer393(
assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
// assign do[12:0]=zigzag_q[12:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
// assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin
d1[12:0] <= di[12:0];
//inv_sign
......@@ -218,7 +216,7 @@ module quantizer393(
if (!en) ren[3:1] <= 0;
else ren[3:1] <= ren [2:0];
if (ren[2]) do[12:0] <= zigzag_q[12:0];
if (ren[2]) dout[12:0] <= zigzag_q[12:0];
if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm;
......
fpga_version.vh
View file @ 609af175
......@@ -36,7 +36,8 @@
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
parameter FPGA_VERSION = 32'h03930104; // serial - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
// parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK
......
includes/x393_parameters.vh
View file @ 609af175
......@@ -292,6 +292,7 @@
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
......@@ -712,6 +713,8 @@
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
......@@ -734,6 +737,7 @@
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
......@@ -742,6 +746,7 @@
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
......
memctrl/mcntrl393.v
View file @ 609af175
This diff is collapsed.
memctrl/mcntrl_linear_rw.v
View file @ 609af175
......@@ -101,7 +101,6 @@ module mcntrl_linear_rw #(
input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
output frame_run, // @mclk - enable pixels from sensor to memory buffer
input next_page, // page was read/written from/to 4*1kB on-chip buffer
// output page_ready, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
output frame_finished,// turns on and stays on after frame_done
// optional I/O for channel synchronization
......@@ -154,27 +153,27 @@ module mcntrl_linear_rw #(
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
// reg [2:0] bank_reg [2:0];
reg [3 * 3 - 1:0] bank_reg;
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_xfer; //continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [NUM_XFER_BITS-1:0] leftover; //[MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change)
reg xfer_start_rd_r;
reg xfer_start_wr_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
// SuppressWarnings VEditor unused
......@@ -210,7 +209,6 @@ module mcntrl_linear_rw #(
reg frame_finished_r;
wire last_in_row_w;
wire last_row_w;
// wire last_block_w;
reg last_block;
reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
......@@ -258,7 +256,6 @@ module mcntrl_linear_rw #(
reg [LAST_FRAME_BITS-1:0] frame_number_current;
reg is_last_frame;
// reg [2:0] frame_start_r;
reg [4:0] frame_start_r; // increased length to have time from line_unfinished to suspend (external)
reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line
......@@ -270,6 +267,7 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start_late
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late
reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
reg [MCNTRL_SCANLINE_DLY_WIDTH:0] start_delay_cntr = {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}}; // start delay counter
......@@ -311,12 +309,7 @@ module mcntrl_linear_rw #(
if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w }; // now only at specific command
/*
|
set_start_addr_w |
set_last_frame_w |
set_frame_size_w};
*/
if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
......@@ -331,7 +324,6 @@ module mcntrl_linear_rw #(
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (mrst) is_last_frame <= 0;
// else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
`ifdef REPORT_FRAME_NUMBER
......@@ -342,7 +334,6 @@ module mcntrl_linear_rw #(
// if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
// if (mrst) frame_en <= 0;
if (!chn_en) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start_late) frame_en <= 0;
......@@ -407,9 +398,9 @@ module mcntrl_linear_rw #(
assign xfer_start_rd= xfer_start_rd_r;
assign xfer_start_wr= xfer_start_wr_r;
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page_rst_wr= xfer_page_rst_r;
assign xfer_page_rst_rd= xfer_page_rst_neg;
assign xfer_partial= xfer_limited_by_mem_page_r;
assign frame_done= frame_done_r;
......@@ -430,7 +421,7 @@ module mcntrl_linear_rw #(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished = line_unfinished_r; // [FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS];
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
......@@ -448,7 +439,8 @@ module mcntrl_linear_rw #(
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif
`endif
assign pgm_param_w= cmd_we;
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
......@@ -575,10 +567,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge mclk) begin
// acceletaring pre_want
// pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
//last_block is too late for pre_want_r1, moving upsteram
// pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
......
memctrl/mcntrl_tiled_linear_rw.v 0 → 100644
View file @ 609af175
This diff is collapsed.
memctrl/mcntrl_tiled_rw.v
View file @ 609af175
......@@ -79,7 +79,8 @@ module mcntrl_tiled_rw#(
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
......
py393/x393_export_c.py
View file @ 609af175
......@@ -974,7 +974,7 @@ class X393ExportC(object):
(("X393_CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2","",vrlg.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2,0,None, None, "", "jp4, 4 blocks, differential, hdr,divide by 2")),
(("X393_CMPRS_CBIT_CMODE_MONO1", "", vrlg.CMPRS_CBIT_CMODE_MONO1 , 0, None, None, "", "Mono JPEG (not yet implemented)")),
(("X393_CMPRS_CBIT_CMODE_MONO4", "", vrlg.CMPRS_CBIT_CMODE_MONO4 , 0, None, None, "", "Mono, 4 blocks (2x2 macroblocks)")),
(("X393_CMPRS_CBIT_CMODE_RAW", "", vrlg.CMPRS_CBIT_CMODE_RAW , 0, None, None, "", "Uncompressed (raw), specify width/height in 16x16 byte macroblocks (in 16-bit 8 pixels wide)")),
(("X393_CMPRS_CBIT_FRAMES_SINGLE", "", vrlg.CMPRS_CBIT_FRAMES_SINGLE , 0, None, None, "", "Use single-frame buffer")),
(("X393_CMPRS_CBIT_FRAMES_MULTI", "", 1 , 0, None, None, "", "Use multi-frame buffer"))]
ba = vrlg.CMPRS_GROUP_ADDR
......@@ -1691,6 +1691,7 @@ class X393ExportC(object):
dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer"))
dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)"))
dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode"))
dw.append(("linear", vrlg.MCONTR_LINTILE_LINEAR,1,1, "Use linear mode instead of tiled (for raw image files): extra_pages=0, keep_open=x, byte32=x"))
dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start). NEEDED after initial set up to propagate start address!"))
dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame"))
dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames"))
......@@ -2312,6 +2313,8 @@ class X393ExportC(object):
dw.append(("cmode_set" , vrlg.CMPRS_CBIT_CMODE, 1, 0, "Set 'cmode'"))
dw.append(("multiframe", vrlg.CMPRS_CBIT_FRAMES - vrlg.CMPRS_CBIT_FRAMES_BITS, vrlg.CMPRS_CBIT_FRAMES_BITS, 0, "Multi/single frame mode"))
dw.append(("multiframe_set", vrlg.CMPRS_CBIT_FRAMES, 1, 0, "Set 'multiframe'"))
dw.append(("raw_be16", vrlg.CMPRS_CBIT_BE16 - vrlg.CMPRS_CBIT_BE16_BITS, vrlg.CMPRS_CBIT_BE16_BITS, 0, "Swap bytes in each pair (raw mode only), use with 16-bit data"))
dw.append(("raw_be16_set", vrlg.CMPRS_CBIT_BE16, 1, 0, "Set 'multiframe'"))
dw.append(("bayer", vrlg.CMPRS_CBIT_BAYER - vrlg.CMPRS_CBIT_BAYER_BITS, vrlg.CMPRS_CBIT_BAYER_BITS, 0, "Bayer shift"))
dw.append(("bayer_set", vrlg.CMPRS_CBIT_BAYER, 1, 0, "Set 'bayer'"))
dw.append(("focus", vrlg.CMPRS_CBIT_FOCUS - vrlg.CMPRS_CBIT_FOCUS_BITS, vrlg.CMPRS_CBIT_FOCUS_BITS, 0, "Focus mode"))
......
system_defines.vh
View file @ 609af175
......@@ -46,7 +46,7 @@
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE
`define DEBUG_COMPRESSOR_SCRAMBLE // ======== WTF? ======== is undefined in synthesis mode
`define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT
......@@ -64,7 +64,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
......@@ -188,32 +188,32 @@
`define def_scanline_chn11
`undef def_tiled_chn11
// chn 12 is tiled read (compressor channel 0)
// chn 12 is tiled read + scanline read (for Tiff) (compressor channel 0)
`define def_enable_mem_chn12
`define def_read_mem_chn12
`undef def_write_mem_chn12
`undef def_scanline_chn12
`define def_scanline_chn12
`define def_tiled_chn12
// chn 12 is tiled read (compressor channel 1)
// chn 13 is tiled read + scanline read (for Tiff) (compressor channel 1)
`define def_enable_mem_chn13
`define def_read_mem_chn13
`undef def_write_mem_chn13
`undef def_scanline_chn13
`define def_scanline_chn13
`define def_tiled_chn13
// chn 12 is tiled read (compressor channel 2)
// chn 14 is tiled read + scanline read (for Tiff) (compressor channel 2)
`define def_enable_mem_chn14
`define def_read_mem_chn14
`undef def_write_mem_chn14
`undef def_scanline_chn14
`define def_scanline_chn14
`define def_tiled_chn14
// chn 12 is tiled read (compressor channel 3)
// chn 15 is tiled read + scanline read (for Tiff) (compressor channel 3)
`define def_enable_mem_chn15
`define def_read_mem_chn15
`undef def_write_mem_chn15
`undef def_scanline_chn15
`define def_scanline_chn15
`define def_tiled_chn15
`endif
\ No newline at end of file
x393.v
View file @ 609af175
......@@ -1317,6 +1317,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_LINEAR (MCONTR_LINTILE_LINEAR), // Use linear mode instead of tiled
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
......@@ -2042,6 +2043,8 @@ assign axi_grst = axi_rst_pre;
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
......
x393_parallel.bit
View file @ 609af175
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x393_sata/wrapper/GTXE2_GPL.v
View file @ 609af175
......@@ -258,7 +258,24 @@ end
endmodule
`endif
module gtxe2_chnl_clocking(
module gtxe2_chnl_clocking#(
parameter [23:0] CPLL_CFG = 29'h00BC07DC,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 5,
parameter [23:0] CPLL_INIT_CFG = 24'h00001E,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [1:0] PMA_RSV3 = 1,
parameter TXOUT_DIV = 2,
//parameter TXRATE = 3'b000;
parameter RXOUT_DIV = 2,
//parameter RXRATE = 3'b000;
parameter TX_INT_DATAWIDTH = 0,
parameter TX_DATA_WIDTH = 20,
parameter RX_INT_DATAWIDTH = 0,
parameter RX_DATA_WIDTH = 20
)(
// top-level interfaces
input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0,
......@@ -314,6 +331,7 @@ module gtxe2_chnl_clocking(
input [19:0] TSTIN
);
// CPLL
/*
parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5;
......@@ -332,18 +350,8 @@ parameter TX_INT_DATAWIDTH = 0;
parameter TX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter RX_DATA_WIDTH = 20;
/*
localparam tx_serial_divider = TXRATE == 3'b001 ? 1
: TXRATE == 3'b010 ? 2
: TXRATE == 3'b011 ? 4
: TXRATE == 3'b100 ? 8
: TXRATE == 3'b101 ? 16 : TXOUT_DIV ;
localparam rx_serial_divider = RXRATE == 3'b001 ? 1
: RXRATE == 3'b010 ? 2
: RXRATE == 3'b011 ? 4
: RXRATE == 3'b100 ? 8
: RXRATE == 3'b101 ? 16 : RXOUT_DIV ;
*/
localparam tx_pma_divider1 = TX_INT_DATAWIDTH == 1 ? 4 : 2;
localparam tx_pcs_divider1 = tx_pma_divider1;
localparam tx_pma_divider2 = TX_DATA_WIDTH == 20 | TX_DATA_WIDTH == 40 | TX_DATA_WIDTH == 80 ? 5 : 4;
......@@ -360,6 +368,11 @@ wire TXPLLREFCLK_DIV2;
wire RXPLLREFCLK_DIV1;
wire RXPLLREFCLK_DIV2;
assign GTREFCLKMONITOR = 'bx; // Was not assigned
assign TXOUTCLKFABRIC = 'bx; // Was not assigned
assign RXOUTCLKFABRIC = 'bx; // Was not assigned
assign tx_phy_clk = TXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
assign TXPLLREFCLK_DIV1 = TXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out;
assign rx_phy_clk = RXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
......@@ -2358,6 +2371,8 @@ rx(
.serial_clk (rx_serial_clk)
);
wire tx_piso_clk;
wire rx_sipo_clk;
gtxe2_chnl_clocking #(
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
......@@ -2374,8 +2389,7 @@ gtxe2_chnl_clocking #(
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH)
)
clocking(
) clocking_i ( // was "clocking" w/o "_i" - is it a keyword?
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
......@@ -2410,7 +2424,7 @@ clocking(
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (tx_serial_clk),
.tx_piso_clk (),
.tx_piso_clk (tx_piso_clk),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
......@@ -2425,9 +2439,10 @@ clocking(
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (rx_serial_clk),
.rx_sipo_clk ()
.rx_sipo_clk (rx_sipo_clk)
);
endmodule
module GTXE2_GPL(
......
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