working on sensor channel (6021159e) · Commits · Elphel / x393

memctrl/phy/phy_top.v

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -295,7 +295,6 @@ BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
	//BUFH clk_ref_i (.O(clk_ref), .I(clk_ref_pre));		//BUFH clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
	BUFG clk_ref_i (.O(clk_ref), .I(clk_ref_pre));		BUFG clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
	BUFG mclk_i (.O(mclk),.I(mclk_pre) );		BUFG mclk_i (.O(mclk),.I(mclk_pre) );
	/* Instance template for module mmcm_phase_cntr */
	mmcm_phase_cntr #(		mmcm_phase_cntr #(
	.PHASE_WIDTH (PHASE_WIDTH),		.PHASE_WIDTH (PHASE_WIDTH),
	.CLKIN_PERIOD (CLKIN_PERIOD),		.CLKIN_PERIOD (CLKIN_PERIOD),
	@@ -333,7 +332,9 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
	.SS_MOD_PERIOD (SS_MOD_PERIOD),		.SS_MOD_PERIOD (SS_MOD_PERIOD),
	.STARTUP_WAIT ("FALSE")		.STARTUP_WAIT ("FALSE")
	) mmcm_phase_cntr_i (		) mmcm_phase_cntr_i (
	.clkin (clk_in), // input		.clkin1 (clk_in), // input
			.clkin2 (1'b0), // input
			.clkinsel (1'b0), // input
	.clkfbin (clk_fb), // input		.clkfbin (clk_fb), // input
	// .rst (rst), // input		// .rst (rst), // input
	.rst (rst_in), // input		.rst (rst_in), // input

sensor/pxd_clock.v

0 → 100644

+75 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			* Module: pxd_clock
			* Date:2015-05-16
			* Author: andrey
			* Description: pixel clock line input
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* pxd_clock.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* pxd_clock.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module pxd_clock #(
			parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
			parameter integer IDELAY_VALUE = 0,
			parameter integer PXD_DRIVE = 12,
			parameter PXD_IBUF_LOW_PWR = "TRUE",
			parameter PXD_IOSTANDARD = "DEFAULT",
			parameter PXD_SLEW = "SLOW",
			parameter real REFCLK_FREQUENCY = 300.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE"

			) (
			inout pxclk, // I/O pad
			input pxclk_out, // data to be sent out through the pad (normally not used)
			input pxclk_en, // enable data output (normally not used)
			output pxclk_in, // data output - delayed pad data
			input rst, // reset
			input mclk, // clock for setting delay values
			input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
			input set_idelay, // mclk synchronous load idelay value
			input ld_idelay // mclk synchronous set idealy value
			);
			wire pxclk_iobuf;

			iobuf #(
			.DRIVE (PXD_DRIVE),
			.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
			.IOSTANDARD (PXD_IOSTANDARD),
			.SLEW (PXD_SLEW)
			) iobuf_pxclk_i (
			.O (pxclk_iobuf), // output
			.IO (pxclk), // inout
			.I (pxclk_out), // input
			.T (!pxclk_en) // input
			);

			idelay_fine_pipe # (
			.IODELAY_GRP (IODELAY_GRP),
			.DELAY_VALUE (IDELAY_VALUE),
			.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
			.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
			) pxclk_dly_i(
			.clk (mclk),
			.rst (rst),
			.set (set_idelay),
			.ld (ld_idelay),
			.delay (dly_data[7:0]),
			.data_in (pxclk_iobuf),
			.data_out (pxclk_in)
			);


			endmodule

sensor/pxd_single.v

0 → 100644

+101 −0

Original line number	Original line	Diff line number	Diff line
			/*******************************************************************************
			* Module: pxd_single
			* Date:2015-05-15
			* Author: andrey
			* Description: pixel data line input
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* pxd_single.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* pxd_single.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module pxd_single#(
			parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
			parameter integer IDELAY_VALUE = 0,
			parameter integer PXD_DRIVE = 12,
			parameter PXD_IBUF_LOW_PWR = "TRUE",
			parameter PXD_IOSTANDARD = "DEFAULT",
			parameter PXD_SLEW = "SLOW",
			parameter real REFCLK_FREQUENCY = 300.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE"

			)(
			inout pxd, // I/O pad
			input pxd_out, // data to be sent out through the pad (normally not used)
			input pxd_en, // enable data output (normally not used)
			output pxd_async, // direct ouptut from the pad (maybe change to delayed?), does not depend on clocks - use for TDI
			output pxd_in, // data output (@posedge ipclk?)
			input ipclk, // restored clock from the sensor, phase-shifted
			input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency
			input rst, // reset
			input mclk, // clock for setting delay values
			input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
			input set_idelay, // mclk synchronous load idelay value
			input ld_idelay, // mclk synchronous set idealy value
			input [1:0] quadrant // select one of 4 90-degree shifts for the data (MT9P0xx) have VACT, HACT shifted from PXD
			);
			wire pxd_iobuf;
			wire pxd_delayed;
			wire [3:0] dout;
			reg pxd_r;

			assign pxd_in=pxd_r;
			assign pxd_async = pxd_iobuf;
			always @ (posedge rst or posedge mclk) begin
			if (rst) pxd_r <= 0;
			else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
			end

			iobuf #(
			.DRIVE (PXD_DRIVE),
			.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
			.IOSTANDARD (PXD_IOSTANDARD),
			.SLEW (PXD_SLEW)
			) iobuf_pxd_i (
			.O (pxd_iobuf), // output
			.IO (pxd), // inout
			.I (pxd_out), // input
			.T (!pxd_en) // input
			);

			idelay_fine_pipe # (
			.IODELAY_GRP (IODELAY_GRP),
			.DELAY_VALUE (IDELAY_VALUE),
			.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
			.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
			) pxd_dly_i(
			.clk (mclk),
			.rst (rst),
			.set (set_idelay),
			.ld (ld_idelay),
			.delay (dly_data[7:0]),
			.data_in (pxd_iobuf),
			.data_out (pxd_delayed)
			);

			iserdes_mem #(
			.DYN_CLKDIV_INV_EN("FALSE")
			) iserdes_pxd_i (
			.iclk(ipclk2x), // source-synchronous clock
			.oclk(ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
			.oclk_div(ipclk), // oclk divided by 2, front aligned
			.inv_clk_div(1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
			.rst(rst), // reset
			.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
			.ddly(pxd_delayed), // serial input from idelay
			.dout(dout[3:0]) // parallel data out
			);

			endmodule

sensor/sens_parallel12.v

+582 −8

File changed.

Preview size limit exceeded, changes collapsed.

sensor/sensor_channel.v

+184 −41

Original line number	Original line	Diff line number	Diff line
	@@ -29,13 +29,61 @@ module sensor_channel#(
	parameter SENSI2C_CTRL = 'h0,		parameter SENSI2C_CTRL = 'h0,
	parameter SENSI2C_STATUS = 'h1,		parameter SENSI2C_STATUS = 'h1,
	parameter SENSI2C_STATUS_REG = 'h30,		parameter SENSI2C_STATUS_REG = 'h30,
	parameter integer DRIVE = 12,		parameter integer SENSI2C_DRIVE=12,
	parameter IBUF_LOW_PWR = "TRUE",		parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
	parameter IOSTANDARD = "DEFAULT",		parameter SENSI2C_IOSTANDARD = "DEFAULT",
	`ifdef XIL_TIMING		parameter SENSI2C_SLEW = "SLOW",
	parameter LOC = " UNPLACED",
	`endif		parameter SENSIO_ADDR = 'h330,
	parameter SLEW = "SLOW"		parameter SENSIO_ADDR_MASK = 'h3f8,
			parameter SENSIO_CTRL = 'h0,
			parameter SENSIO_STATUS = 'h1,
			parameter SENSIO_JTAG = 'h2,
			parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
			parameter SENSIO_DELAYS = 'h4,
			parameter SENSIO_STATUS_REG = 'h31,

			parameter SENS_JTAG_PGMEN = 8,
			parameter SENS_JTAG_PROG = 6,
			parameter SENS_JTAG_TCK = 4,
			parameter SENS_JTAG_TMS = 2,
			parameter SENS_JTAG_TDI = 0,

			parameter SENS_CTRL_MRST = 0, // 1: 0
			parameter SENS_CTRL_ARST = 2, // 3: 2
			parameter SENS_CTRL_ARO = 4, // 5: 4
			parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
			parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
			parameter SENS_CTRL_LD_DLY = 10, // 10
			parameter SENS_CTRL_QUADRANTS =12, // 17:12, enable - 20


			parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
			parameter integer IDELAY_VALUE = 0,
			parameter integer PXD_DRIVE = 12,
			parameter PXD_IBUF_LOW_PWR = "TRUE",
			parameter PXD_IOSTANDARD = "DEFAULT",
			parameter PXD_SLEW = "SLOW",
			parameter real REFCLK_FREQUENCY = 300.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE",

			parameter PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
			parameter PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
			parameter BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

			parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
			parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
			parameter IPCLK_PHASE = 0.000,
			parameter IPCLK2X_PHASE = 0.000,


			parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
			parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
			parameter REF_JITTER2 = 0.010,
			parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
			parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
			parameter SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns

	) (		) (
	input rst,		input rst,
	input pclk, // global clock input, pixel rate (96MHz for MT9P006)		input pclk, // global clock input, pixel rate (96MHz for MT9P006)
	@@ -43,6 +91,7 @@ module sensor_channel#(
	inout [7:0] sns_dp,		inout [7:0] sns_dp,
	inout [7:0] sns_dn,		inout [7:0] sns_dn,
	inout sns_clkp,		inout sns_clkp,
			inout sns_clkn,
	inout sns_scl,		inout sns_scl,
	inout sns_sda,		inout sns_sda,
	inout sns_ctl,		inout sns_ctl,
	@@ -57,6 +106,33 @@ module sensor_channel#(
	// (much) more will be added later		// (much) more will be added later

	);		);
			wire [7:0] sens_i2c_status_ad;
			wire sens_i2c_status_rq;
			wire sens_i2c_status_start;
			wire [7:0] sens_par12_status_ad;
			wire sens_par12_status_rq;
			wire sens_par12_status_start;

			wire ipclk; // Use in FIFO
			wire ipclk2x; // Use in FIFO
			wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
			wire vact; // frame active @posedge ipclk
			wire hact; // line active @posedge ipclk

			status_router2 status_router2_sensori (
			.rst (rst), // input
			.clk (mclk), // input
			.db_in0 (sens_i2c_status_ad), // input[7:0]
			.rq_in0 (sens_i2c_status_rq), // input
			.start_in0 (sens_i2c_status_start), // output
			.db_in1 (sens_par12_status_ad), // input[7:0]
			.rq_in1 (sens_par12_status_rq), // input
			.start_in1 (sens_par12_status_start), // output
			.db_out (status_ad), // output[7:0]
			.rq_out (status_rq), // output
			.start_out (status_start) // input
			);

	sensor_i2c_io #(		sensor_i2c_io #(
	.SENSI2C_ABS_ADDR (SENSI2C_ABS_ADDR),		.SENSI2C_ABS_ADDR (SENSI2C_ABS_ADDR),
	.SENSI2C_REL_ADDR (SENSI2C_REL_ADDR),		.SENSI2C_REL_ADDR (SENSI2C_REL_ADDR),
	@@ -71,16 +147,83 @@ module sensor_channel#(
	.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),		.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
	.SENSI2C_SLEW (SENSI2C_SLEW)		.SENSI2C_SLEW (SENSI2C_SLEW)
	) sensor_i2c_io_i (		) sensor_i2c_io_i (
	.rst(), // input		.rst (rst), // input
	.mclk(), // input		.mclk (mclk), // input
	.cmd_ad(), // input[7:0]		.cmd_ad (cmd_ad), // input[7:0]
	.cmd_stb(), // input		.cmd_stb (cmd_stb), // input
	.status_ad(), // output[7:0]		.status_ad (sens_i2c_status_ad), // output[7:0]
	.status_rq(), // output		.status_rq (sens_i2c_status_rq), // output
	.status_start(), // input		.status_start (sens_i2c_status_start), // input
	.frame_sync (), // input		.frame_sync (), // input
	.scl(), // inout		.scl (sns_scl), // inout
	.sda() // inout		.sda (sns_sda) // inout
			);

			sens_parallel12 #(
			.SENSIO_ADDR (SENSIO_ADDR),
			.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
			.SENSIO_CTRL (SENSIO_CTRL),
			.SENSIO_STATUS (SENSIO_STATUS),
			.SENSIO_JTAG (SENSIO_JTAG),
			.SENSIO_WIDTH (SENSIO_WIDTH),
			.SENSIO_DELAYS (SENSIO_DELAYS),
			.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
			.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
			.SENS_JTAG_PROG (SENS_JTAG_PROG),
			.SENS_JTAG_TCK (SENS_JTAG_TCK),
			.SENS_JTAG_TMS (SENS_JTAG_TMS),
			.SENS_JTAG_TDI (SENS_JTAG_TDI),
			.SENS_CTRL_MRST (SENS_CTRL_MRST),
			.SENS_CTRL_ARST (SENS_CTRL_ARST),
			.SENS_CTRL_ARO (SENS_CTRL_ARO),
			.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
			.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
			.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
			.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
			.IODELAY_GRP (IODELAY_GRP),
			.IDELAY_VALUE (IDELAY_VALUE),
			.PXD_DRIVE (PXD_DRIVE),
			.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
			.PXD_IOSTANDARD (PXD_IOSTANDARD),
			.PXD_SLEW (PXD_SLEW),
			.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
			.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
			.PHASE_WIDTH (PHASE_WIDTH),
			.PCLK_PERIOD (PCLK_PERIOD),
			.BANDWIDTH (BANDWIDTH),
			.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
			.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
			.IPCLK_PHASE (IPCLK_PHASE),
			.IPCLK2X_PHASE (IPCLK2X_PHASE),
			.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
			.REF_JITTER1 (REF_JITTER1),
			.REF_JITTER2 (REF_JITTER2),
			.SS_EN (SS_EN),
			.SS_MODE (SS_MODE),
			.SS_MOD_PERIOD (SS_MOD_PERIOD)
			) sens_parallel12_i (
			.rst (rst), // input
			.pclk (pclk), // input
			.ipclk (ipclk), // output
			.ipclk2x (ipclk2x), // output
			.vact (sns_dn[1]), // input
			.hact (sns_dp[1]), // input
			.bpf (sns_dn[0]), // inout
			.pxd ({sns_dn[6],sns_dp[6],sns_dn[5],sns_dp[5],sns_dn[4],sns_dp[4],sns_dn[3],sns_dp[3],sns_dn[2],sns_dp[2],sns_clkp,sns_clkn}), // inout[11:0]
			.mrst (sns_dp[7]), // inout
			.senspgm (sns_pg), // inout
			.arst (sns_dn[7]), // inout
			.aro (sns_ctl), // inout
			.dclk (sns_dp[0]), // output
			.pxd_out (pxd[11:0]), // output[11:0]
			.vact_out (vact), // output
			.hact_out (hact), // output: either delayed input, or regenerated from the leading edge and programmable duration
			.mclk (mclk), // input
			.cmd_ad (cmd_ad), // input[7:0]
			.cmd_stb (cmd_stb), // input
			.status_ad (sens_par12_status_ad), // output[7:0]
			.status_rq (sens_par12_status_rq), // output
			.status_start (sens_par12_status_start) // input
	);		);

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