Working JTAG baord recognition/configuration of the sensor port multiplexer

.project

@@ -62,52 +62,52 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160406001856812.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160330184559950.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -122,12 +122,12 @@
 		<link>
 			<name>vivado_state/x393-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-route-20160405181335960.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160330184559950.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

fpga_version.vh

@@ -32,7 +32,11 @@
  * with at least one of the Free Software programs.
  *******************************************************************************/
  
-      parameter FPGA_VERSION =          32'h03930081;    // re-started parallel
+      parameter FPGA_VERSION =          32'h03930085;    // Adding software control for i2c pins when sequencer is stopped
+//      parameter FPGA_VERSION =          32'h03930084;    // Back to iserdes, inverting xfpgatdo - met
+//      parameter FPGA_VERSION =          32'h03930083;    // Debugging JTAG, using plain IOBUF
+//      parameter FPGA_VERSION =          32'h03930082;    // trying other path to read xfpgatdo
+//      parameter FPGA_VERSION =          32'h03930081;    // re-started parallel - timing met
 //      parameter FPGA_VERSION =          32'h03930080;    // serial, failed timing, >84%
 //      parameter FPGA_VERSION =          32'h0393007f;    // More constraints files tweaking
 //      parameter FPGA_VERSION =          32'h0393007e;    // Trying .tcl constraints instead of xdc - timing met

includes/x393_parameters.vh

@@ -367,6 +367,10 @@
         parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
         parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
         parameter SENSI2C_CMD_RUN_PBITS =    1,
+        
+        parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+        parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+        
         parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1
         parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
         parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1

py393/generated/x393.c

 /*******************************************************************************
  * File: x393.c
- * Date: 2016-04-04  
+ * Date: 2016-04-06  
  * Author: auto-generated file, see x393_export_c.py
  * Description: Functions definitions to access x393 hardware registers
  *******************************************************************************/

py393/generated/x393.h

 /*******************************************************************************
  * File: x393.h
- * Date: 2016-04-04  
+ * Date: 2016-04-06  
  * Author: auto-generated file, see x393_export_c.py
  * Description: Constants definitions and functions declarations to access x393 hardware registers
  *******************************************************************************/

py393/generated/x393_defs.h

 /*******************************************************************************
  * File: x393_defs.h
- * Date: 2016-04-04  
+ * Date: 2016-04-06  
  * Author: auto-generated file, see x393_export_c.py
  * Description: Constants and hardware addresses definitions to access x393 hardware registers
  *******************************************************************************/

py393/generated/x393_map.h

 /*******************************************************************************
  * File: x393_map.h
- * Date: 2016-04-04  
+ * Date: 2016-04-06  
  * Author: auto-generated file, see x393_export_c.py
  * Description: Sorted hardware addresses map
  *******************************************************************************/

py393/generated/x393_types.h

 /*******************************************************************************
  * File: x393_types.h
- * Date: 2016-04-04  
+ * Date: 2016-04-06  
  * Author: auto-generated file, see x393_export_c.py
  * Description: typedef definitions for the x393 hardware registers
  *******************************************************************************/
@@ -411,7 +411,9 @@ typedef union {
           u32     sda_release: 1; // [    1] (0) Release SDA early if next bit ==1 (valid with drive_ctl)
           u32       drive_ctl: 1; // [    2] (0) 0 - nop, 1 - set sda_release and sda_drive_high
           u32    next_fifo_rd: 1; // [    3] (0) Advance I2C read FIFO pointer
-          u32                : 8;
+          u32        soft_scl: 2; // [ 5: 4] (0) Control SCL pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float 
+          u32        soft_sda: 2; // [ 7: 6] (0) Control SDA pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float 
+          u32                : 4;
           u32         cmd_run: 2; // [13:12] (0) Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run 
           u32           reset: 1; // [   14] (0) Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
           u32                :13;

py393/init_jtag.sh

+#!/bin/sh
+#mkdir -p /lib/modules
+#ln -sf /usr/local/lib /lib/modules/4.0.0-xilinx
+insmod /usr/local/lib/fpgajtag.ko
+#mknod  -m 0666 /dev/fjtag              c 132   2
+mknod  -m 0666 /dev/fpgaresetjtag      c 132   0
+mknod  -m 0666 /dev/jtagraw            c 132   0
+mknod  -m 0666 /dev/fpgaconfjtag       c 132   1
+mknod  -m 0666 /dev/sfpgaconfjtag      c 132   2
+mknod  -m 0666 /dev/afpgaconfjtag      c 132   3
+#mknod  -m 0666 /dev/fpgabscan          c 132   5 
+#mknod  -m 0666 /dev/sfpgabscan         c 132   6
+#mknod  -m 0666 /dev/afpgabscan         c 132   7
+
+mknod  -m 0666 /dev/sfpgaconfjtag0     c 132   8
+mknod  -m 0666 /dev/sfpgaconfjtag1     c 132   9
+mknod  -m 0666 /dev/sfpgaconfjtag2     c 132   10
+mknod  -m 0666 /dev/sfpgaconfjtag3     c 132   11
+
+mknod  -m 0666 /dev/sfpgabscan0        c 132   12
+mknod  -m 0666 /dev/sfpgabscan1        c 132   13
+mknod  -m 0666 /dev/sfpgabscan2        c 132   14
+mknod  -m 0666 /dev/sfpgabscan3        c 132   15
+
+
+#	@$(MKNOD) -m 0666           $(DEV)/fpgaresetjtag      c 132   0
+#	@$(MKNOD) -m 0666           $(DEV)/jtagraw            c 132   0
+#	@$(MKNOD) -m 0666           $(DEV)/fpgaconfjtag       c 132   1
+#	@$(MKNOD) -m 0666           $(DEV)/sfpgaconfjtag      c 132   2
+#	@$(MKNOD) -m 0666           $(DEV)/afpgaconfjtag      c 132   3
+#	@$(MKNOD) -m 0666           $(DEV)/fpgabscan          c 132   5
+#	@$(MKNOD) -m 0666           $(DEV)/sfpgabscan         c 132   6
+#	@$(MKNOD) -m 0666           $(DEV)/afpgabscan         c 132   7

py393/vrlg.py

@@ -263,6 +263,7 @@ SENS_PHASE_WIDTH = int
 HIST_SAXI_MODE_ADDR_MASK__TYPE = str
 MCONTR_CMPRS_STATUS_BASE__RAW = str
 SENS_LENS_RADDR__TYPE = str
+SENSI2C_CMD_SOFT_SCL = int
 CAMSYNC_PRE_MAGIC__TYPE = str
 MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
 DEBUG_LOAD = int
@@ -345,6 +346,7 @@ MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
 LAST_FRAME_BITS__RAW = str
 SENS_DIVCLK_DIVIDE = int
 NEWPAR = int
+SENSI2C_CMD_SOFT_SDA__TYPE = str
 SENS_LENS_COEFF__RAW = str
 CMPRS_CONTROL_REG = int
 GPIO_STATUS_REG_ADDR = int
@@ -1393,6 +1395,7 @@ NUM_CYCLES_04 = int
 SENS_LENS_C__TYPE = str
 MCONTR_PHY_16BIT_EXTRA__TYPE = str
 CAMSYNC_TRIGGERED_BIT__RAW = str
+SENSI2C_CMD_SOFT_SCL__RAW = str
 CMPRS_CSAT_CR__TYPE = str
 SENS_LENS_POST_SCALE__RAW = str
 DLY_LANE1_IDELAY = long
@@ -1582,6 +1585,7 @@ CLK_STATUS__TYPE = str
 CMPRS_COLOR20__TYPE = str
 T_REFI__TYPE = str
 MCONTR_CMD_WR_ADDR__TYPE = str
+SENSI2C_CMD_SOFT_SCL__TYPE = str
 CLKFBOUT_MULT_SENSOR__RAW = str
 CMPRS_CSAT_CR_BITS = int
 HIST_SAXI_ADDR_REL__TYPE = str
@@ -1629,6 +1633,7 @@ CMPRS_AFIMUX_MASK__RAW = str
 MCNTRL_TILED_WINDOW_X0Y0__RAW = str
 SENS_GAMMA_MODE_PAGE__TYPE = str
 CMPRS_COLOR_SATURATION__TYPE = str
+SENSI2C_CMD_SOFT_SDA = int
 SENSI2C_CMD_TAND = int
 CMPRS_AFIMUX_SA_LEN = int
 SENS_CTRL_QUADRANTS_EN__TYPE = str
@@ -2040,6 +2045,7 @@ NUM_CYCLES_11__RAW = str
 FFCLK1_CAPACITANCE__RAW = str
 SENSI2C_DRIVE__RAW = str
 CMPRS_CBIT_CMODE_MONO1__TYPE = str
+SENSI2C_CMD_SOFT_SDA__RAW = str
 SENSOR_CTRL_ADDR_MASK__RAW = str
 DFLT_CHN_EN__RAW = str
 NUM_CYCLES_LOW_BIT = int

py393/x393_axi_control_status.py

@@ -355,7 +355,7 @@ class X393AxiControlStatus(object):
                                   3: auto, inc sequence number 
         <seq_number> - 6-bit sequence number of the status message to be sent
         """
-        self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number * 0x3f))
+        self.write_control_register(base_addr + reg_addr, ((mode & 3)<< 6) | (seq_number & 0x3f))
 
 
     def program_status_all( self,

py393/x393_export_c.py

@@ -1750,6 +1750,10 @@ class X393ExportC(object):
         dw.append(("sda_release",      vrlg.SENSI2C_CMD_ACIVE_EARLY0, 1,0,  "Release SDA early if next bit ==1 (valid with drive_ctl)"))
         dw.append(("drive_ctl",        vrlg.SENSI2C_CMD_ACIVE,        1,0,  "0 - nop, 1 - set sda_release and sda_drive_high"))
         dw.append(("next_fifo_rd",     vrlg.SENSI2C_CMD_FIFO_RD,      1,0,  "Advance I2C read FIFO pointer"))
+        
+        dw.append(("soft_scl",         vrlg.SENSI2C_CMD_SOFT_SCL,     2,0,  "Control SCL pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
+        dw.append(("soft_sda",         vrlg.SENSI2C_CMD_SOFT_SDA,     2,0,  "Control SDA pin (when stopped): 0 - nop, 1 - low, 2 - high (driven), 3 - float "))
+        
         dw.append(("cmd_run",          vrlg.SENSI2C_CMD_RUN-1,        2,0,  "Sequencer run/stop control: 0,1 - nop, 2 - stop, 3 - run "))
         dw.append(("reset",            vrlg.SENSI2C_CMD_RESET,        1,0,  "Sequencer reset all FIFO (takes 16 clock pulses), also - stops i2c until run command"))
         dw.append(("tbl_mode",         vrlg.SENSI2C_CMD_TAND,         2,0,  "Should be 0 to select controls"))

sensor/sens_parallel12.v

@@ -190,7 +190,9 @@ module  sens_parallel12 #(
 
 
 
-    wire [17:0] status;
+//    wire [17:0] status;
+//    wire [18:0] status;
+    wire [22:0] status;
     
     wire        cmd_we;
     wire  [2:0] cmd_a;
@@ -228,7 +230,12 @@ module  sens_parallel12 #(
      
     assign set_pxd_delay =   set_idelay[2:0];
     assign set_other_delay = set_idelay[3];
-    assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
+//    assign status = {pxd_out_pre[1],vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
+//                     clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
+//                     ps_rdy, ps_out, xfpgatdo, senspgmin};
+    assign status = {irst, async_prst_with_sens_mrst, imrst, rst_mmcm, pxd_out_pre[1],
+    
+                     vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
                      clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
                      ps_rdy, ps_out, xfpgatdo, senspgmin};
     assign hact_out = hact_r;
@@ -414,14 +421,16 @@ module  sens_parallel12 #(
 
     status_generate #(
         .STATUS_REG_ADDR(SENSIO_STATUS_REG),
-        .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
+//        .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
+        .PAYLOAD_BITS(15+3+STATUS_ALIVE_WIDTH+1) // STATUS_PAYLOAD_BITS)
     ) status_generate_sens_io_i (
         .rst        (1'b0),         // rst), // input
         .clk        (mclk),         // input
         .srst       (mclk_rst),     // input
         .we         (set_status_r), // input
         .wd         (data_r[7:0]),  // input[7:0] 
-        .status     ({status_alive,status}),       // input[25:0] 
+//        .status     ({status_alive,status}),       // input[25:0] 
+        .status     ({status}),       // input[25:0] 
         .ad         (status_ad),    // output[7:0] 
         .rq         (status_rq),    // output
         .start      (status_start)  // input
@@ -456,8 +465,27 @@ module  sens_parallel12 #(
         .ld_idelay      (ld_idelay),       // input
         .quadrant       (quadrants[1:0])   // input[1:0] 
     );
+    
 // debugging implementation
 //assign xfpgatdo = pxd_out[1];
+    /* Instance template for module iobuf */
+//`define DEBUF_JTAG 1
+`ifdef DEBUF_JTAG    
+    iobuf #(
+        .DRIVE        (PXD_DRIVE),
+        .IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
+        .IOSTANDARD   (PXD_IOSTANDARD),
+        .SLEW         (PXD_SLEW)
+    ) pxd_pxd1_i (
+        .O            (pxd_out_pre[1]), // output
+        .IO           (pxd[1]), // inout
+        .I            (1'b0), // input
+        .T            (1'b1) // input
+    );
+    assign xfpgatdo = pxd_out_pre[1];
+`else
+    wire n_xfpgatdo;
+    assign xfpgatdo = !n_xfpgatdo;
     pxd_single #(
         .IODELAY_GRP           (IODELAY_GRP),
         .IDELAY_VALUE          (IDELAY_VALUE),
@@ -471,18 +499,22 @@ module  sens_parallel12 #(
         .pxd            (pxd[1]),          // inout
         .pxd_out        (1'b0),            // input
         .pxd_en         (1'b0),            // input
-        .pxd_async      (xfpgatdo),        // output
+        .pxd_async      (n_xfpgatdo),      // output
         .pxd_in         (pxd_out_pre[1]),  // output
         .ipclk          (ipclk),           // input
         .ipclk2x        (ipclk2x),         // input
         .mrst           (mclk_rst),        // input
         .irst           (irst),            // input
         .mclk           (mclk),            // input
-        .dly_data       (data_r[15:8]),          // input[7:0] 
+        .dly_data       (data_r[15:8]),    // input[7:0] 
         .set_idelay     (set_pxd_delay[0]),// input
         .ld_idelay      (ld_idelay),       // input
         .quadrant       (quadrants[1:0])   // input[1:0] 
     );
+`endif    
+    
+    
+    
     // bits 2..11 are just PXD inputs, instance them all together
     generate
         genvar i;

sensor/sensor_channel.v

@@ -81,6 +81,8 @@ module  sensor_channel#(
         parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
         parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
         parameter SENSI2C_CMD_RUN_PBITS =    1,
+        parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+        parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
         parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1  
         parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
         parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
@@ -614,6 +616,8 @@ module  sensor_channel#(
         .SENSI2C_CMD_RESET       (SENSI2C_CMD_RESET),
         .SENSI2C_CMD_RUN         (SENSI2C_CMD_RUN),
         .SENSI2C_CMD_RUN_PBITS   (SENSI2C_CMD_RUN_PBITS),
+        .SENSI2C_CMD_SOFT_SDA    (SENSI2C_CMD_SOFT_SDA),
+        .SENSI2C_CMD_SOFT_SCL    (SENSI2C_CMD_SOFT_SCL),
         .SENSI2C_CMD_FIFO_RD     (SENSI2C_CMD_FIFO_RD),
         .SENSI2C_CMD_ACIVE       (SENSI2C_CMD_ACIVE),
         .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),

sensor/sensor_i2c.v

@@ -48,7 +48,8 @@ module  sensor_i2c#(
     parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
     parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
     parameter SENSI2C_CMD_RUN_PBITS =    1,
-    
+    parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+    parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
     parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1  
     parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
     parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
@@ -112,16 +113,7 @@ module  sensor_i2c#(
      wire           wen;
      wire    [31:0] di;
      wire     [3:0] wa; 
-//     wire           busy;        // busy (do not use software i2i)
-     
-     
-//    reg    [4:0]  wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
-//     reg    [3:0]  wen_d; // [0] - not just fifo, but any PIO writes, [1] and next - filtered for FIFO only
-//     reg    [3:0]  wad; 
      reg   [31:0]  di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
-//     reg   [15:0]  di_1;
-//     reg   [15:0]  di_2;
-//     reg   [15:0]  di_3;
      reg    [3:0]  wpage0;     // FIFO page where ASAP writes go
      reg    [3:0]  wpage_prev;     // unused page, currently being cleared
      reg    [3:0]  page_r;     // FIFO page where current i2c commands are taken from
@@ -129,21 +121,15 @@ module  sensor_i2c#(
      reg    [3:0]  wpage_wr;    // FIFO page where current write goes (reading from write address) 
      reg    [1:0]  wpage0_inc; // increment wpage0 (after frame sync or during reset)
      reg           reset_cmd;
-//     reg           dly_cmd;
-//     reg           bytes_cmd;
      reg           run_cmd;
      reg           twe;
      reg           active_cmd;
      reg           active_sda;
      reg           early_release_0;
      reg           reset_on;   // reset FIFO in progress
-//     reg    [1:0]  i2c_bytes;
-//     reg    [7:0]  i2c_dly;
      reg           i2c_enrun;     // enable i2c
      reg           we_fifo_wp; // enable writing to fifo write pointer memory
      reg           req_clr;    // request for clearing fifo_wp (delay frame sync if previous is not yet sent out), also used for clearing all
-//     wire          is_ctl= (wad[3:0]==4'hf);
-//     wire          is_abs= (wad[3]==0);
      wire          pre_wpage0_inc; // ready to increment
      
      wire   [3:0]  frame_num=wpage0[3:0];
@@ -165,7 +151,6 @@ module  sensor_i2c#(
      reg           i2c_start; // initiate i2c register write sequence
      wire          i2c_run;   // i2c sequence is in progress (early end)
      reg           i2c_run_d;   // i2c sequence is in progress (early end)
-//     wire          i2c_busy;  // i2c sequence is in progress (until bus is free and stop finished)
      wire   [1:0]  byte_number;  // byte number to send next (3-2-1-0)
      wire   [1:0]  seq_mem_re;
      wire   [7:0]  i2c_data;
@@ -182,8 +167,16 @@ module  sensor_i2c#(
      wire          set_status_w;
 
      reg            [1:0] wen_r;
-//     reg            [1:0] wen_fifo;
      reg            wen_fifo; // [1] was not used - we_fifo_wp was used instead
+     
+     reg           scl_en_soft;  // software i2c control signals (used when i2c controller is disabled)
+     reg           scl_soft;
+     reg           sda_en_soft;
+     reg           sda_soft;
+     
+     wire          sda_hard;
+     wire          sda_en_hard;
+     wire          scl_hard;
 
      
      assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
@@ -196,8 +189,14 @@ module  sensor_i2c#(
 
      assign         wen=set_ctrl_w || we_rel || we_abs; //remove set_ctrl_w?
      
-     assign scl_en = i2c_enrun;
-     
+//     assign scl_en = i2c_enrun;
+     assign scl_out = i2c_enrun?  scl_hard:    scl_soft ;
+     assign scl_en =  i2c_enrun?  1'b1:        scl_en_soft  ;
+     assign sda_out = i2c_enrun?  sda_hard:    sda_soft ;
+     assign sda_en =  i2c_enrun?  sda_en_hard: sda_en_soft ;
+
+
+
      
     reg alive_fs;
     always @ (posedge mclk) begin
@@ -286,6 +285,16 @@ module  sensor_i2c#(
         
         if    (reset_cmd || mrst) i2c_enrun <= 1'b0;
         else if (run_cmd)         i2c_enrun <= di_r[SENSI2C_CMD_RUN - 1 -: SENSI2C_CMD_RUN_PBITS]; // [12];
+
+        if      (i2c_enrun || mrst)                                                     scl_en_soft <= 0;
+        else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_en_soft <= di[SENSI2C_CMD_SOFT_SCL +:2] != 3;
+        
+        if      (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SCL +:2]) scl_soft <=    di[SENSI2C_CMD_SOFT_SCL + 1];
+        
+        if      (i2c_enrun || mrst)                                                     sda_en_soft <= 0;
+        else if (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_en_soft <= di[SENSI2C_CMD_SOFT_SDA +:2] != 3;
+        
+        if      (set_ctrl_w && !di[SENSI2C_CMD_TABLE] && |di[SENSI2C_CMD_SOFT_SDA +:2]) sda_soft <=    di[SENSI2C_CMD_SOFT_SDA + 1];
         
         if (active_cmd) begin
             early_release_0 <= di_r[SENSI2C_CMD_ACIVE_EARLY0];
@@ -377,9 +386,9 @@ module  sensor_i2c#(
         .td              (di_r[SENSI2C_CMD_TAND-1:0]),      // input[27:0] 
         .twe             (twe),             // input
         .sda_in          (sda_in),          // input
-        .sda             (sda_out),         // output
-        .sda_en          (sda_en),          // output
-        .scl             (scl_out),         // output
+        .sda             (sda_hard),        // output
+        .sda_en          (sda_en_hard),     // output
+        .scl             (scl_hard),        // output
         .i2c_run         (i2c_run),         // output reg 
         .i2c_busy        (), //i2c_busy),   // output reg 
         .seq_mem_ra      (byte_number),     // output[1:0] reg 

sensor/sensor_i2c_io.v

@@ -48,7 +48,8 @@ module  sensor_i2c_io#(
     parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
     parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
     parameter SENSI2C_CMD_RUN_PBITS =    1,
-    
+    parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+    parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
     parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1  
     parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
     parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
@@ -108,6 +109,8 @@ module  sensor_i2c_io#(
         .SENSI2C_CMD_RESET       (SENSI2C_CMD_RESET),
         .SENSI2C_CMD_RUN         (SENSI2C_CMD_RUN),
         .SENSI2C_CMD_RUN_PBITS   (SENSI2C_CMD_RUN_PBITS),
+        .SENSI2C_CMD_SOFT_SDA    (SENSI2C_CMD_SOFT_SDA),
+        .SENSI2C_CMD_SOFT_SCL    (SENSI2C_CMD_SOFT_SCL),
         .SENSI2C_CMD_FIFO_RD     (SENSI2C_CMD_FIFO_RD),
         .SENSI2C_CMD_ACIVE       (SENSI2C_CMD_ACIVE),
         .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),

sensor/sensors393.v

@@ -72,6 +72,8 @@ module  sensors393 #(
         parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
         parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
         parameter SENSI2C_CMD_RUN_PBITS =    1,
+        parameter SENSI2C_CMD_SOFT_SDA =     6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float
+        parameter SENSI2C_CMD_SOFT_SCL =     4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float
         parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1  
         parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
         parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
@@ -479,6 +481,8 @@ module  sensors393 #(
                 .SENSI2C_CMD_RESET             (SENSI2C_CMD_RESET),
                 .SENSI2C_CMD_RUN               (SENSI2C_CMD_RUN),
                 .SENSI2C_CMD_RUN_PBITS         (SENSI2C_CMD_RUN_PBITS),
+                .SENSI2C_CMD_SOFT_SDA          (SENSI2C_CMD_SOFT_SDA),
+                .SENSI2C_CMD_SOFT_SCL          (SENSI2C_CMD_SOFT_SCL),
                 .SENSI2C_CMD_FIFO_RD           (SENSI2C_CMD_FIFO_RD),
                 .SENSI2C_CMD_ACIVE             (SENSI2C_CMD_ACIVE),
                 .SENSI2C_CMD_ACIVE_EARLY0      (SENSI2C_CMD_ACIVE_EARLY0),