Loading .project +12 −12 Original line number Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -122,12 +122,12 @@ <link> <name>vivado_state/x393-route.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20160405181335960.dcp</location> </link> <link> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160330184559950.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location> </link> </linkedResources> </projectDescription> fpga_version.vh +5 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,11 @@ * with at least one of the Free Software programs. *******************************************************************************/ parameter FPGA_VERSION = 32'h03930081; // re-started parallel parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met // parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF // parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo // parameter FPGA_VERSION = 32'h03930081; // re-started parallel - timing met // parameter FPGA_VERSION = 32'h03930080; // serial, failed timing, >84% // parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking // parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met Loading includes/x393_parameters.vh +4 −0 Original line number Diff line number Diff line Loading @@ -367,6 +367,10 @@ parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 Loading py393/generated/x393.c +1 −1 Original line number Diff line number Diff line /******************************************************************************* * File: x393.c * Date: 2016-04-04 * Date: 2016-04-06 * Author: auto-generated file, see x393_export_c.py * Description: Functions definitions to access x393 hardware registers *******************************************************************************/ Loading py393/generated/x393.h +1 −1 Original line number Diff line number Diff line /******************************************************************************* * File: x393.h * Date: 2016-04-04 * Date: 2016-04-06 * Author: auto-generated file, see x393_export_c.py * Description: Constants definitions and functions declarations to access x393 hardware registers *******************************************************************************/ Loading Loading
.project +12 −12 Original line number Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160406001856812.log</location> </link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160330184559950.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160406001220877.log</location> </link> <link> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -122,12 +122,12 @@ <link> <name>vivado_state/x393-route.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-route-20150904164653967.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20160405181335960.dcp</location> </link> <link> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160330184559950.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160406001220877.dcp</location> </link> </linkedResources> </projectDescription>
fpga_version.vh +5 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,11 @@ * with at least one of the Free Software programs. *******************************************************************************/ parameter FPGA_VERSION = 32'h03930081; // re-started parallel parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met // parameter FPGA_VERSION = 32'h03930083; // Debugging JTAG, using plain IOBUF // parameter FPGA_VERSION = 32'h03930082; // trying other path to read xfpgatdo // parameter FPGA_VERSION = 32'h03930081; // re-started parallel - timing met // parameter FPGA_VERSION = 32'h03930080; // serial, failed timing, >84% // parameter FPGA_VERSION = 32'h0393007f; // More constraints files tweaking // parameter FPGA_VERSION = 32'h0393007e; // Trying .tcl constraints instead of xdc - timing met Loading
includes/x393_parameters.vh +4 −0 Original line number Diff line number Diff line Loading @@ -367,6 +367,10 @@ parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state parameter SENSI2C_CMD_RUN_PBITS = 1, parameter SENSI2C_CMD_SOFT_SDA = 6, // [7:6] - SDA software control: 0 - nop, 1 - low, 2 - active high, 3 - float parameter SENSI2C_CMD_SOFT_SCL = 4, // [5:4] - SCL software control: 0 - nop, 1 - low, 2 - active high, 3 - float parameter SENSI2C_CMD_FIFO_RD = 3, // advance I2C read data FIFO by 1 parameter SENSI2C_CMD_ACIVE = 2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1 Loading
py393/generated/x393.c +1 −1 Original line number Diff line number Diff line /******************************************************************************* * File: x393.c * Date: 2016-04-04 * Date: 2016-04-06 * Author: auto-generated file, see x393_export_c.py * Description: Functions definitions to access x393 hardware registers *******************************************************************************/ Loading
py393/generated/x393.h +1 −1 Original line number Diff line number Diff line /******************************************************************************* * File: x393.h * Date: 2016-04-04 * Date: 2016-04-06 * Author: auto-generated file, see x393_export_c.py * Description: Constants definitions and functions declarations to access x393 hardware registers *******************************************************************************/ Loading