Added input data, matched 256-cycle Bayer CLT in all modes (5978d4b5) · Commits · Elphel / x393

dsp/mclt16x16.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -550,7 +550,8 @@ D11 - negate for mode 3 (SS)
		// are these shift OK? Will need to be valis only @ dtt_start_out
		.shift_h (x_shft_r4), // input[6:0] signed
		.shift_v (y_shft_r4), // input[6:0] signed
		.inv_checker (1'b0), // input only used for Bayer mosaic data
		// .inv_checker (1'b0), // input only used for Bayer mosaic data
		.inv (3'b0), // input only used for Bayer mosaic data
		.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start
		.fd_out (dout), // output[24:0] reg signed
		.pre_first_out (pre_first_out), // output reg

dsp/mclt16x16_bayer.v

+5 −2

Original line number	Diff line number	Diff line
		@@ -458,7 +458,8 @@ module mclt16x16_bayer#(
		// are these shift OK? Will need to be valis only @ dtt_start_out
		.shift_h (x_shft_r5), // input[6:0] signed
		.shift_v (y_shft_r5), // input[6:0] signed
		.inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
		// .inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
		.inv ({inv_checker_r5,1'b0,inv_checker_r5}),// input only used for Bayer mosaic data
		.fd_din (dtt_rd_data0), // input[24:0] signed. Expected latency = 3 from start
		.fd_out (dout0), // output[24:0] reg signed
		.pre_first_out (pre_first_out), // output reg
		@@ -480,7 +481,9 @@ module mclt16x16_bayer#(
		// are these shift OK? Will need to be valis only @ dtt_start_out
		.shift_h (x_shft_r5), // input[6:0] signed
		.shift_v (y_shft_r5), // input[6:0] signed
		.inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
		// .inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
		.inv ({inv_checker_r5,1'b0,inv_checker_r5}),// input only used for Bayer mosaic data

		.fd_din (dtt_rd_data1), // input[24:0] signed. Expected latency = 3 from start
		.fd_out (dout1), // output[24:0] reg signed
		.pre_first_out (), // output reg

dsp/mclt16x16_bayer3.v

+22 −7

Original line number	Diff line number	Diff line
		@@ -53,7 +53,8 @@ module mclt16x16_bayer3#(
		parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
		parameter DSP_A_WIDTH = 25,
		parameter DSP_P_WIDTH = 48,
		parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
		parameter DEAD_CYCLES = 14, // start next block immedaitely, or with longer pause
		parameter OUTS_AT_ONCE = 1 // 0: outputs with lowest latency, 1: all at once (with green)
		)(
		input clk, //!< system clock, posedge
		input rst, //!< sync reset
		@@ -102,9 +103,11 @@ module mclt16x16_bayer3#(
		localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1
		// localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		// May be tweaked so outputs will appear simultaneously
		localparam DTT_OUT_DELAY_R = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_B = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_G = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?


		localparam DTT_OUT_DELAY_G = 128-17; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_R = OUTS_AT_ONCE ? (DTT_OUT_DELAY_G + 128) : 64-19; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
		localparam DTT_OUT_DELAY_B = OUTS_AT_ONCE ? (DTT_OUT_DELAY_G + 64) : 64-19; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?

		reg [7:0] in_cntr; //
		reg run_r;
		@@ -468,6 +471,18 @@ module mclt16x16_bayer3#(


		// Three of 2 page buffers after dtt (feeding two phase rotators), address MSB is not needed
		reg [8:0] dbg_prerot_bufwr_r, dbg_prerot_bufwr_b, dbg_prerot_bufwr_g;
		always @(posedge clk) begin
		if (dtt_out_we_r) dbg_prerot_bufwr_r <= dtt_out_ram_wa_rb;
		if (dtt_out_we_b) dbg_prerot_bufwr_b <= dtt_out_ram_wa_rb;
		if (dtt_out_we_g) dbg_prerot_bufwr_g <= dtt_out_ram_wa_g;
		end
		// wire [8:0] dbg_prerot_buf_r = dtt_rd_regen_r[0]?(dtt_out_ram_wa_rb - dtt_rd_ra_r):'bz; // SuppressThisWarning VEditor : debug output
		// wire [8:0] dbg_prerot_buf_b = dtt_rd_regen_b[0]?(dtt_out_ram_wa_rb - dtt_rd_ra_b):'bz; // SuppressThisWarning VEditor : debug output
		// wire [8:0] dbg_prerot_buf_g = dtt_rd_regen_g[0]?(dtt_out_ram_wa_g - dtt_rd_ra_g):'bz; // SuppressThisWarning VEditor : debug output
		wire [8:0] dbg_prerot_buf_r = dtt_rd_regen_r[0]?(dbg_prerot_bufwr_r - dtt_rd_ra_r):'bz; // SuppressThisWarning VEditor : debug output
		wire [8:0] dbg_prerot_buf_b = dtt_rd_regen_b[0]?(dbg_prerot_bufwr_b - dtt_rd_ra_b):'bz; // SuppressThisWarning VEditor : debug output
		wire [8:0] dbg_prerot_buf_g = dtt_rd_regen_g[0]?(dbg_prerot_bufwr_g - dtt_rd_ra_g):'bz; // SuppressThisWarning VEditor : debug output
		ram18p_var_w_var_r #(
		.REGISTERS(1),
		.LOG2WIDTH_WR(5),
		@@ -537,7 +552,7 @@ module mclt16x16_bayer3#(
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.odd_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_r), // output[7:0]
		.in_re (dtt_rd_regen_r), // output[1:0]
		.fd_din (dtt_rd_data_r), // input[24:0] signed
		@@ -566,7 +581,7 @@ module mclt16x16_bayer3#(
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.odd_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_b), // output[7:0]
		.in_re (dtt_rd_regen_b), // output[1:0]
		.fd_din (dtt_rd_data_b), // input[24:0] signed
		@@ -594,7 +609,7 @@ module mclt16x16_bayer3#(
		.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
		.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
		.inv_checker (inv_checker_rot_ram_reg), // input
		.inv_rows (valid_odd_rot_ram_reg), // input
		.odd_rows (valid_odd_rot_ram_reg), // input
		.in_addr (dtt_rd_ra_g), // output[7:0]
		.in_re (dtt_rd_regen_g), // output[1:0]
		.fd_din (dtt_rd_data_g), // input[24:0] signed

dsp/mclt_test_05.tf

+32 −21

Original line number	Diff line number	Diff line
		@@ -76,6 +76,8 @@ module mclt_test_05 ();
		parameter DSP_A_WIDTH = 25;
		parameter DSP_P_WIDTH = 48;
		parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause
		// parameter OUTS_AT_ONCE = 0; // 0: outputs with lowest latency, 1: all at once (with green)
		parameter OUTS_AT_ONCE = 1; // 0: outputs with lowest latency, 1: all at once (with green)

		reg RST = 1'b1;
		reg CLK = 1'b0;
		@@ -170,7 +172,8 @@ module mclt_test_05 ();
		reg [1:0] byr_index; // [0:2]; // bayer index of top-left 16x16 tile

		initial begin
		$readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
		// $readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
		$readmemh("input_data/mclt_dtt_all_02_x1489_y951.dat", java_all);

		$display("000c: %h", java_all['h000c]);

		@@ -531,25 +534,32 @@ module mclt_test_05 ();
		);


		reg FIRST_OUT;
		always @(posedge CLK) FIRST_OUT <= mclt16x16_bayer_i.pre_first_out;
		//dout_r, dout_b, dout_g
		integer n7r, n7b, n7g;
		reg [7:0] cntr7r, cntr7b, cntr7g;
		always @ (posedge CLK) begin
		if (RST) n7r <= -1; else if (pre_first_out_r) n7r <= n7r + 1;
		if (pre_first_out_r) cntr7r <= 0; else if (dv_r) cntr7r <= cntr7r + 1;

		integer n7, cntr7, diff70, diff71; // SuppressThisWarning VEditor : assigned in $readmem() system task
		wire [OUT_WIDTH-1:0] java_data_dtt_rot0 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b0}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
		wire [OUT_WIDTH-1:0] java_data_dtt_rot1 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b1}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
		initial begin
		while (RST) @(negedge CLK);
		for (n7 = 0; n7 < 6; n7 = n7+1) begin
		while (!FIRST_OUT) begin
		@(negedge CLK);
		end
		for (cntr7 = 0; cntr7 < 128; cntr7 = cntr7 + 1) begin
		#1;
		diff70 = dout0 - java_data_dtt_rot0;
		diff71 = dout1 - java_data_dtt_rot1;
		@(negedge CLK);
		end
		if (RST) n7b <= -1; else if (pre_first_out_b) n7b <= n7b + 1;
		if (pre_first_out_b) cntr7b <= 0; else if (dv_b) cntr7b <= cntr7b + 1;

		if (RST) n7g <= -1; else if (pre_first_out_g) n7g <= n7g + 1;
		if (pre_first_out_g) cntr7g <= 0; else if (dv_g) cntr7g <= cntr7g + 1;
		end

		integer diff7r, diff7b, diff7g; // SuppressThisWarning VEditor : assigned in $readmem() system task
		/// wire [OUT_WIDTH-1:0] java_dout_r0 = jav_dtt_rot['h300*out_addr_r[8] + 'h000 + {out_addr_r[7:6], out_addr_r[2:0], out_addr_r[5:3]}];
		/// wire [OUT_WIDTH-1:0] java_dout_b0 = jav_dtt_rot['h300*out_addr_b[8] + 'h100 + {out_addr_b[7:6], out_addr_b[2:0], out_addr_b[5:3]}];
		/// wire [OUT_WIDTH-1:0] java_dout_g0 = jav_dtt_rot['h300*out_addr_g[8] + 'h200 + {out_addr_g[7:6], out_addr_g[2:0], out_addr_g[5:3]}];
		wire [OUT_WIDTH-1:0] java_dout_r = jav_dtt_rot['h300*n7r + 'h000 + {cntr7r[1:0], cntr7r[7:2]}];
		wire [OUT_WIDTH-1:0] java_dout_b = jav_dtt_rot['h300*n7b + 'h100 + {cntr7b[1:0], cntr7b[7:2]}];
		wire [OUT_WIDTH-1:0] java_dout_g = jav_dtt_rot['h300*n7g + 'h200 + {cntr7g[1:0], cntr7g[7:2]}];

		always @ (posedge CLK) begin
		diff7r <= dv_r? (dout_r - java_dout_r) : 'bz;
		diff7b <= dv_b? (dout_b - java_dout_b) : 'bz;
		diff7g <= dv_g? (dout_g - java_dout_g) : 'bz;
		end

		reg FIRST_OUTa;
		@@ -641,7 +651,7 @@ module mclt_test_05 ();
		reg page3; // 1/2-nd bayer tile
		reg pre_run;
		reg [1:0] pre_run_cntr;
		wire [2:0] color_page = pre_run_cntr + 3 * page3;
		wire [2:0] color_page = pre_run_cntr + 3 * page3; // SuppressThisWarning VEditor - VDT bug (used as index)
		always @ (posedge CLK) begin
		if (START) page3 <= (SUB_PAGE > 2);

		@@ -673,7 +683,8 @@ module mclt_test_05 ();
		.DSP_B_WIDTH (DSP_B_WIDTH),
		.DSP_A_WIDTH (DSP_A_WIDTH),
		.DSP_P_WIDTH (DSP_P_WIDTH),
		.DEAD_CYCLES (DEAD_CYCLES)
		.DEAD_CYCLES (DEAD_CYCLES),
		.OUTS_AT_ONCE (OUTS_AT_ONCE)
		) mclt16x16_bayer3_i (
		.clk (CLK), // input
		.rst (RST), // input

dsp/phase_rotator.v

+23 −9

Original line number	Diff line number	Diff line
		@@ -53,7 +53,10 @@ module phase_rotator#(
		input start, //!< single-cycle start pulse that goes 1 cycle before first data
		input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
		input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
		input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
		// input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
		// fitst sample is never negated
		input [2:0] inv, //!< bit 0 - invert 2-nd sample, 1 - third, 2 - fourth (for green: 5)

		// input data CC,CS,SC,SS in column scan order (matching DTT)
		input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start
		output reg signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
		@@ -95,8 +98,11 @@ module phase_rotator#(
		reg [SHIFT_WIDTH-1:0] shift_v0;
		reg [SHIFT_WIDTH-1:0] shift_vr;
		reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux;
		reg inv_checker_r;
		reg inv_checker_r2;
		// reg inv_checker_r;
		// reg inv_checker_r2;
		reg [2:0] inv_r;
		reg [2:0] inv_r4;
		reg [2:0] inv_r5;
		reg [4:0] sign_cs; // sign for cos / sin, feed to DSP
		wire sign_cs_d; // sign_cs delayed by 3 clocks
		reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks
		@@ -115,10 +121,12 @@ module phase_rotator#(

		if (start) shift_hr <= shift_h;
		if (start) shift_v0 <= shift_v;
		if (start) inv_checker_r <= inv_checker;
		// if (start) inv_checker_r <= inv_checker;
		if (start) inv_r <= inv;
		if (start_d[3]) shift_vr <= shift_v0;
		if (start_d[4]) inv_checker_r2 <= inv_checker_r;

		// if (start_d[4]) inv_checker_r2 <= inv_checker_r;
		if (start_d[3]) inv_r4 <= inv_r;
		inv_r5 <= inv_r4;
		if (rst) run_h <= 0;
		else if (start) run_h <= 1;
		// else if (&cntr_h_consec[6:0] && (cntr_h[7] \|\| DECIMATE)) run_h <= 0;
		@@ -231,9 +239,15 @@ module phase_rotator#(
		negm_2 <= ((ph[5] & ~sign_cs[3]) \| (ph[6] & sign_cs[4])) ^
		(inv_checker_r2 & (ph[5] \| ph[7])); // invert negation when using Bayer patterns
		*/
		negm_1 <= (ph[4] & ~sign_cs[2]) \| (ph[5] & sign_cs[3]);
		negm_2 <= ((ph[5] & ~sign_cs[3]) \| (ph[6] & sign_cs[4])) ^ inv_checker_r2;
		// (inv_checker_r2 & (\|ph[7:4])); // invert negation when using Bayer patterns
		// negm_1 <= (ph[4] & ~sign_cs[2]) \| (ph[5] & sign_cs[3]);
		// negm_2 <= ((ph[5] & ~sign_cs[3]) \| (ph[6] & sign_cs[4])) ^ inv_checker_r2;

		negm_1 <= ((ph[4] & ~sign_cs[2]) \| (ph[5] & sign_cs[3])) ^
		(inv_r4[1] & (ph[4] \| ph[6])); // invert negation when using Bayer patterns
		negm_2 <= ((ph[5] & ~sign_cs[3]) \| (ph[6] & sign_cs[4])) ^
		((inv_r5[0] & (ph[4] \| ph[6])) \|
		(inv_r5[2] & (ph[5] \| ph[7]))); // invert negation when using Bayer patterns



		accum_1 <= ph[4] \| ph[6]; accum_2 <= ph[5] \| ph[7];

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