Continue debugging 256-cycle Bayer MCLT

    output reg                       out_we,        //!< output data valid (write to external buffer 

    output reg                       sub16,         //!< Subtract 16 from the full output address when true

    output reg                       inc16,         //!< increment full output address by 16

    output reg                       start16,       //!< reset/copy page address

    output reg                       start_out);    //!< may start output readout, 1 entry per clock, vertically

// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock

        inc16 <= out_cntr[3:0] == 'he;

        out_we <= dctv_out_we[1];

        start_out <= start_out_w;

        start16 <= dctv_phin [6:0] == 'h11;

    end

    always @ (posedge clk) begin

    always @(posedge clk) begin

        if      (rst)        dtt_out_ram_cntr <= 0;

        else if (dtt_inc16)  dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;

        else if (dtt_inc16)  dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; // make it copy input page?

        dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;

        dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;

        .data_in  ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] 

    );

    dtt_iv_8x8_ad #(

        .INPUT_WIDTH     (DTT_IN_WIDTH),

        .OUT_WIDTH       (OUT_WIDTH),

        .out_we         (dtt_out_we),       // output reg 

        .sub16          (dtt_sub16),        // output reg 

        .inc16          (dtt_inc16),        // output reg

        .start16        (),                 // output reg 

        .start_out      (dtt_start_fill)    // output[24:0] signed

    );

    //[DTT_IN_WIDTH-1:0

    reg  [1:0] ced2;

    wire neg_m1, neg_m2, en_a2;

    wire accum1= !var_pre2_first;

    wire accum2= !var_pre_first && green_r[2];

//    wire accum2= !var_pre_first && green_r[2];

    wire accum2= !var_pre_first && green_r[3];

    wire [DSP_P_WIDTH-1:0] pout1;

    wire [DSP_P_WIDTH-1:0] pout2;

    wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ?

        .rst  (rst),           // input

        .dly  (4'h1),          // input[3:0] 

//        .din  (pix_sgn[1]),    // input[0:0] 

        .din  (green_r[0]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 

//        .din  (green_r[0]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 

        .din  (green_r[1]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 

        .dout (neg_m2)         // output[0:0] 

    );