Commit 5978d4b5 authored by Andrey Filippov's avatar Andrey Filippov

Added input data, matched 256-cycle Bayer CLT in all modes

parent 46f1a6c9
......@@ -550,7 +550,8 @@ D11 - negate for mode 3 (SS)
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed
.inv_checker (1'b0), // input only used for Bayer mosaic data
// .inv_checker (1'b0), // input only used for Bayer mosaic data
.inv (3'b0), // input only used for Bayer mosaic data
.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
......
......@@ -458,7 +458,8 @@ module mclt16x16_bayer#(
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r5), // input[6:0] signed
.shift_v (y_shft_r5), // input[6:0] signed
.inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
// .inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
.inv ({inv_checker_r5,1'b0,inv_checker_r5}),// input only used for Bayer mosaic data
.fd_din (dtt_rd_data0), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout0), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
......@@ -480,7 +481,9 @@ module mclt16x16_bayer#(
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r5), // input[6:0] signed
.shift_v (y_shft_r5), // input[6:0] signed
.inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
// .inv_checker (inv_checker_r5),// input only used for Bayer mosaic data
.inv ({inv_checker_r5,1'b0,inv_checker_r5}),// input only used for Bayer mosaic data
.fd_din (dtt_rd_data1), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout1), // output[24:0] reg signed
.pre_first_out (), // output reg
......
......@@ -53,7 +53,8 @@ module mclt16x16_bayer3#(
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter DEAD_CYCLES = 14 // start next block immedaitely, or with longer pause
parameter DEAD_CYCLES = 14, // start next block immedaitely, or with longer pause
parameter OUTS_AT_ONCE = 1 // 0: outputs with lowest latency, 1: all at once (with green)
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
......@@ -102,9 +103,11 @@ module mclt16x16_bayer3#(
localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1
// localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
// May be tweaked so outputs will appear simultaneously
localparam DTT_OUT_DELAY_R = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_B = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_G = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_G = 128-17; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_R = OUTS_AT_ONCE ? (DTT_OUT_DELAY_G + 128) : 64-19; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_B = OUTS_AT_ONCE ? (DTT_OUT_DELAY_G + 64) : 64-19; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
reg [7:0] in_cntr; //
reg run_r;
......@@ -468,6 +471,18 @@ module mclt16x16_bayer3#(
// Three of 2 page buffers after dtt (feeding two phase rotators), address MSB is not needed
reg [8:0] dbg_prerot_bufwr_r, dbg_prerot_bufwr_b, dbg_prerot_bufwr_g;
always @(posedge clk) begin
if (dtt_out_we_r) dbg_prerot_bufwr_r <= dtt_out_ram_wa_rb;
if (dtt_out_we_b) dbg_prerot_bufwr_b <= dtt_out_ram_wa_rb;
if (dtt_out_we_g) dbg_prerot_bufwr_g <= dtt_out_ram_wa_g;
end
// wire [8:0] dbg_prerot_buf_r = dtt_rd_regen_r[0]?(dtt_out_ram_wa_rb - dtt_rd_ra_r):'bz; // SuppressThisWarning VEditor : debug output
// wire [8:0] dbg_prerot_buf_b = dtt_rd_regen_b[0]?(dtt_out_ram_wa_rb - dtt_rd_ra_b):'bz; // SuppressThisWarning VEditor : debug output
// wire [8:0] dbg_prerot_buf_g = dtt_rd_regen_g[0]?(dtt_out_ram_wa_g - dtt_rd_ra_g):'bz; // SuppressThisWarning VEditor : debug output
wire [8:0] dbg_prerot_buf_r = dtt_rd_regen_r[0]?(dbg_prerot_bufwr_r - dtt_rd_ra_r):'bz; // SuppressThisWarning VEditor : debug output
wire [8:0] dbg_prerot_buf_b = dtt_rd_regen_b[0]?(dbg_prerot_bufwr_b - dtt_rd_ra_b):'bz; // SuppressThisWarning VEditor : debug output
wire [8:0] dbg_prerot_buf_g = dtt_rd_regen_g[0]?(dbg_prerot_bufwr_g - dtt_rd_ra_g):'bz; // SuppressThisWarning VEditor : debug output
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
......@@ -537,7 +552,7 @@ module mclt16x16_bayer3#(
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.odd_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_r), // output[7:0]
.in_re (dtt_rd_regen_r), // output[1:0]
.fd_din (dtt_rd_data_r), // input[24:0] signed
......@@ -566,7 +581,7 @@ module mclt16x16_bayer3#(
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.odd_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_b), // output[7:0]
.in_re (dtt_rd_regen_b), // output[1:0]
.fd_din (dtt_rd_data_b), // input[24:0] signed
......@@ -594,7 +609,7 @@ module mclt16x16_bayer3#(
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.odd_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_g), // output[7:0]
.in_re (dtt_rd_regen_g), // output[1:0]
.fd_din (dtt_rd_data_g), // input[24:0] signed
......
......@@ -76,6 +76,8 @@ module mclt_test_05 ();
parameter DSP_A_WIDTH = 25;
parameter DSP_P_WIDTH = 48;
parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause
// parameter OUTS_AT_ONCE = 0; // 0: outputs with lowest latency, 1: all at once (with green)
parameter OUTS_AT_ONCE = 1; // 0: outputs with lowest latency, 1: all at once (with green)
reg RST = 1'b1;
reg CLK = 1'b0;
......@@ -170,7 +172,8 @@ module mclt_test_05 ();
reg [1:0] byr_index; // [0:2]; // bayer index of top-left 16x16 tile
initial begin
$readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
// $readmemh("input_data/mclt_dtt_all_00_x1489_y951.dat", java_all);
$readmemh("input_data/mclt_dtt_all_02_x1489_y951.dat", java_all);
$display("000c: %h", java_all['h000c]);
......@@ -531,25 +534,32 @@ module mclt_test_05 ();
);
reg FIRST_OUT;
always @(posedge CLK) FIRST_OUT <= mclt16x16_bayer_i.pre_first_out;
//dout_r, dout_b, dout_g
integer n7r, n7b, n7g;
reg [7:0] cntr7r, cntr7b, cntr7g;
always @ (posedge CLK) begin
if (RST) n7r <= -1; else if (pre_first_out_r) n7r <= n7r + 1;
if (pre_first_out_r) cntr7r <= 0; else if (dv_r) cntr7r <= cntr7r + 1;
if (RST) n7b <= -1; else if (pre_first_out_b) n7b <= n7b + 1;
if (pre_first_out_b) cntr7b <= 0; else if (dv_b) cntr7b <= cntr7b + 1;
if (RST) n7g <= -1; else if (pre_first_out_g) n7g <= n7g + 1;
if (pre_first_out_g) cntr7g <= 0; else if (dv_g) cntr7g <= cntr7g + 1;
end
integer diff7r, diff7b, diff7g; // SuppressThisWarning VEditor : assigned in $readmem() system task
/// wire [OUT_WIDTH-1:0] java_dout_r0 = jav_dtt_rot['h300*out_addr_r[8] + 'h000 + {out_addr_r[7:6], out_addr_r[2:0], out_addr_r[5:3]}];
/// wire [OUT_WIDTH-1:0] java_dout_b0 = jav_dtt_rot['h300*out_addr_b[8] + 'h100 + {out_addr_b[7:6], out_addr_b[2:0], out_addr_b[5:3]}];
/// wire [OUT_WIDTH-1:0] java_dout_g0 = jav_dtt_rot['h300*out_addr_g[8] + 'h200 + {out_addr_g[7:6], out_addr_g[2:0], out_addr_g[5:3]}];
wire [OUT_WIDTH-1:0] java_dout_r = jav_dtt_rot['h300*n7r + 'h000 + {cntr7r[1:0], cntr7r[7:2]}];
wire [OUT_WIDTH-1:0] java_dout_b = jav_dtt_rot['h300*n7b + 'h100 + {cntr7b[1:0], cntr7b[7:2]}];
wire [OUT_WIDTH-1:0] java_dout_g = jav_dtt_rot['h300*n7g + 'h200 + {cntr7g[1:0], cntr7g[7:2]}];
integer n7, cntr7, diff70, diff71; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [OUT_WIDTH-1:0] java_data_dtt_rot0 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b0}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
wire [OUT_WIDTH-1:0] java_data_dtt_rot1 = jav_dtt_rot[{n7[2:0], cntr7[1],cntr7[0],cntr7[6:2],1'b1}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
initial begin
while (RST) @(negedge CLK);
for (n7 = 0; n7 < 6; n7 = n7+1) begin
while (!FIRST_OUT) begin
@(negedge CLK);
end
for (cntr7 = 0; cntr7 < 128; cntr7 = cntr7 + 1) begin
#1;
diff70 = dout0 - java_data_dtt_rot0;
diff71 = dout1 - java_data_dtt_rot1;
@(negedge CLK);
end
end
always @ (posedge CLK) begin
diff7r <= dv_r? (dout_r - java_dout_r) : 'bz;
diff7b <= dv_b? (dout_b - java_dout_b) : 'bz;
diff7g <= dv_g? (dout_g - java_dout_g) : 'bz;
end
reg FIRST_OUTa;
......@@ -641,7 +651,7 @@ module mclt_test_05 ();
reg page3; // 1/2-nd bayer tile
reg pre_run;
reg [1:0] pre_run_cntr;
wire [2:0] color_page = pre_run_cntr + 3 * page3;
wire [2:0] color_page = pre_run_cntr + 3 * page3; // SuppressThisWarning VEditor - VDT bug (used as index)
always @ (posedge CLK) begin
if (START) page3 <= (SUB_PAGE > 2);
......@@ -673,7 +683,8 @@ module mclt_test_05 ();
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES)
.DEAD_CYCLES (DEAD_CYCLES),
.OUTS_AT_ONCE (OUTS_AT_ONCE)
) mclt16x16_bayer3_i (
.clk (CLK), // input
.rst (RST), // input
......
......@@ -53,7 +53,10 @@ module phase_rotator#(
input start, //!< single-cycle start pulse that goes 1 cycle before first data
input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
// input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
// fitst sample is never negated
input [2:0] inv, //!< bit 0 - invert 2-nd sample, 1 - third, 2 - fourth (for green: 5)
// input data CC,CS,SC,SS in column scan order (matching DTT)
input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start
output reg signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
......@@ -95,8 +98,11 @@ module phase_rotator#(
reg [SHIFT_WIDTH-1:0] shift_v0;
reg [SHIFT_WIDTH-1:0] shift_vr;
reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux;
reg inv_checker_r;
reg inv_checker_r2;
// reg inv_checker_r;
// reg inv_checker_r2;
reg [2:0] inv_r;
reg [2:0] inv_r4;
reg [2:0] inv_r5;
reg [4:0] sign_cs; // sign for cos / sin, feed to DSP
wire sign_cs_d; // sign_cs delayed by 3 clocks
reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks
......@@ -115,10 +121,12 @@ module phase_rotator#(
if (start) shift_hr <= shift_h;
if (start) shift_v0 <= shift_v;
if (start) inv_checker_r <= inv_checker;
// if (start) inv_checker_r <= inv_checker;
if (start) inv_r <= inv;
if (start_d[3]) shift_vr <= shift_v0;
if (start_d[4]) inv_checker_r2 <= inv_checker_r;
// if (start_d[4]) inv_checker_r2 <= inv_checker_r;
if (start_d[3]) inv_r4 <= inv_r;
inv_r5 <= inv_r4;
if (rst) run_h <= 0;
else if (start) run_h <= 1;
// else if (&cntr_h_consec[6:0] && (cntr_h[7] || DECIMATE)) run_h <= 0;
......@@ -231,10 +239,16 @@ module phase_rotator#(
negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^
(inv_checker_r2 & (ph[5] | ph[7])); // invert negation when using Bayer patterns
*/
negm_1 <= (ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3]);
negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^ inv_checker_r2;
// (inv_checker_r2 & (|ph[7:4])); // invert negation when using Bayer patterns
// negm_1 <= (ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3]);
// negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^ inv_checker_r2;
negm_1 <= ((ph[4] & ~sign_cs[2]) | (ph[5] & sign_cs[3])) ^
(inv_r4[1] & (ph[4] | ph[6])); // invert negation when using Bayer patterns
negm_2 <= ((ph[5] & ~sign_cs[3]) | (ph[6] & sign_cs[4])) ^
((inv_r5[0] & (ph[4] | ph[6])) |
(inv_r5[2] & (ph[5] | ph[7]))); // invert negation when using Bayer patterns
accum_1 <= ph[4] | ph[6]; accum_2 <= ph[5] | ph[7];
// vertical shift DSPs
......
......@@ -55,7 +55,7 @@ module phase_rotator_rgb#(
input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
input inv_rows, //!< 0 : use first row, 1 - second row (when GREEN=0)
input odd_rows, //!< when not GEEN (R or B) 0: even (first) rows non-zero, 1: odd (second)
// input data CC,CS,SC,SS in column scan order (matching DTT)
output [GREEN + 6:0] in_addr, //!< input buffer address
output [1:0] in_re, //!< input buffer re/regen
......@@ -69,10 +69,8 @@ module phase_rotator_rgb#(
reg signed [SHIFT_WIDTH-1:0] shift_h_r;
reg signed [SHIFT_WIDTH-1:0] shift_v_r;
reg inv_checker_r;
reg inv_rows_r;
reg wpage_r;
wire negate = inv_checker_r ^ inv_rows_r; // FIXME: put real
reg [2:0] inv;
reg [1:0] dtt_start_out;
reg [7:0] dtt_dly_cntr;
reg [4:0] dtt_rd_regen_dv;
......@@ -81,14 +79,16 @@ module phase_rotator_rgb#(
reg [8:0] out_addr_r;
assign in_addr = in_addr_r[GREEN + 6:0];
assign in_re = dtt_rd_regen_dv[2:1];
assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
// assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
assign fd_wa = {out_addr_r[8], out_addr_r[1],out_addr_r[0],out_addr_r[4:2],out_addr_r[7:5]};
always @ (posedge clk) begin
if (start) begin
shift_h_r <= shift_h;
shift_v_r <= shift_v;
inv_checker_r <= inv_checker;
inv_rows_r <= inv_rows;
inv <= inv_checker ?
(( GREEN || odd_rows) ? 5 : 6):
((!GREEN && odd_rows) ? 3 : 0);
wpage_r <= wpage;
end
......@@ -110,11 +110,11 @@ module phase_rotator_rgb#(
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
if (GREEN) in_addr_r <= {dtt_rd_cntr_pre[8],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : dtt_rd_cntr_pre[7:2]};
else in_addr_r <= {1'b0,
dtt_rd_cntr_pre[8],
// dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
// dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[1] ?
(dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : {~dtt_rd_cntr_pre[7:5],dtt_rd_cntr_pre[4:2]}):
(dtt_rd_cntr_pre[0] ? {dtt_rd_cntr_pre[7:5],~dtt_rd_cntr_pre[4:2]} : dtt_rd_cntr_pre[7:2])};
......@@ -139,10 +139,10 @@ module phase_rotator_rgb#(
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_out[1]), // input
// are these shift OK? Will need to be valis only @ dtt_start_out
// are these shift OK? Will need to be valid only @ dtt_start_out
.shift_h (shift_h_r), // input[6:0] signed
.shift_v (shift_v_r), // input[6:0] signed
.inv_checker (negate), // input only used for Bayer mosaic data
.inv (inv), // input [2:0]
.fd_din (fd_din), // input[24:0] signed. Expected latency = 3 from start
.fd_out (fd_out), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
......
// Debugging FPGA implementation
// residual_shift[0][0]=0.4609375, residual_shift[0][1]=-0.21875
3b // color 0 shift_x, 7 bits
64 // color 0 shift_y, 7 bits
5d4 // color 0 ctile_left
3b4 // color 0 ctile_top
// residual_shift[1][0]=0.0625, residual_shift[1][1]=0.375
8 // color 1 shift_x, 7 bits
30 // color 1 shift_y, 7 bits
5d1 // color 1 ctile_left
3ba // color 1 ctile_top
// residual_shift[2][0]=-0.234375, residual_shift[2][1]=0.078125
62 // color 2 shift_x, 7 bits
a // color 2 shift_y, 7 bits
5d1 // color 2 ctile_left
3b7 // color 2 ctile_top
// Full Bayer fpga tile data
177d 2fbe 19b7 2941 16c6 288f 1899 3143 1d9d 3c50 1e6e 4236 1c09 3fa9 2155 493c 23e9 3ed5 1cd6 39e8 19bd 294b
379e 18f8 3370 150d 3443 1618 36c9 15bf 36c9 1ba0 3ea6 1f33 4248 1c68 4337 1e66 4603 21b1 3dc6 2008 3b20 1842
1a79 2aa7 14ab 2527 1453 25d2 1351 2529 13fd 2944 1a1b 3dfb 1d9f 4082 1c6f 377c 1ba6 3b85 1da2 3b88 2157 3e03
3879 14b4 3443 14b5 35ef 1565 3372 13b3 30ff 14b6 395d 1d97 4334 1b3f 3ce0 16d0 3520 1787 3c01 18a0 3eab 2008
12fa 1ff6 13fc 2941 1503 2c17 14ab 247e 14ab 2730 1a1b 3844 1ed6 4235 16c9 252d 166e 2ab0 1457 27e7 17e0 314b
329b 145d 3958 16cc 37a0 18f9 35f2 195a 3dbe 1b3d 415d 1d97 638a 5ce5 4cbc 195c 3883 16d0 32a7 1676 3962 161c
1721 2e43 166a 2b5f 13a5 29f5 1c6c 3775 1e04 3452 195a 35e4 261c 6e90 1e07 3ab3 1e07 36b0 183e 2cda 1507 2333
3879 150c 329e 14b5 3518 189b 3a39 1b3d 3bf8 195a 5c00 1e64 4334 189d 4424 26e6 5e26 1ecd 3dc6 18a0 37aa 1361
134f 2329 13a5 288e 1a18 313f 19b8 3082 1454 2c19 6194 6a51 1a7c 2893 1a7e 4856 5216 4dc4 1ed9 2d94 13a9 29fe
31cb 12b4 35ef 1727 3958 17e0 3cda 189c 37a3 16cd 46f2 183f 3cdd 1ba1 4161 1ecd 4fb2 2006 4516 1c07 3b20 1adf
1669 293e 177e 29f4 1503 288e 1351 21e1 14ab 2528 1505 2d8f 1a1b 3d25 1ae0 3087 1a1c 3914 1da2 3b87 17e0 314a
31cb 1616 36c7 14b5 329e 1408 30ff 1409 35f2 150e 3881 18fc 3ea6 1add 3b1d 1ade 36cf 1ade 3ce3 1cd0 3962 19bd
13fb 21dd 14aa 21df 166a 313f 183b 2942 1504 25d3 155e 2945 183c 3206 16c9 2f09 183d 35e6 195c 3394 19bc 35e9
336e 150c 3519 1671 36c7 183d 387e 14b6 3446 1566 3448 13b4 351d 189d 35f7 15c1 3960 18fd 3a41 17e5 3886 16d1
15b4 27db 177e 2ccf 160f 2f01 14ab 247d 13fd 2cd2 1780 2945 17de 2fc5 13ff 252c 1725 3087 1457 21e6 13a9 2332
36c5 1616 329e 150d 302f 1408 3446 15bf 395b 15bf 37a5 140a 3375 19ba 344b 14b8 35f7 1568 31d6 13b6 3522 1676
160e 288b 15b5 27dc 1252 2098 1504 2d8b 1a19 2aaa 1352 1ffa 1455 2e49 1255 252b 14ad 2733 1457 27e5 12fe 228b
30fb 14b4 3030 1565 37a1 135d 2dd1 14b6 3446 1409 2e9d 1619 3449 189d 31d4 130b 32a5 161b 337a 1462 3039 116f
13fb 1e1b 13fc 213b 13a5 288d 177f 2e47 1351 25d3 12fc 1ffa 12fc 2944 1613 21e4 12fd 2733 13a9 20a0 1256 20a0
302e 120d 31cd 12b4 30fe 1b9f 4245 1c03 3372 13b3 31d2 13b4 351e 183f 3520 12b7 32a5 1461 2f6d 12b8 2d10 1361
134f 2281 12a6 25d1 1957 272d 1958 2d8b 166b 1f59 1352 27e1 189a 2fc4 1506 1f5d 115d 1e21 1256 1e23 12aa 23da
329c 111a 329e 135d 3030 145e 351c 15bf 31d0 120f 3034 12b6 3449 1674 32a5 1510 2b82 111d 2f6d 1212 31d7 11c0
// Color # 0: Pixels input range: 0.000000 ... 442.242462
//3b // shift_x, 7 bits
//64 // shift_y, 7 bits
0 3143 0 3c50 0 4236 0 3fa9 0 493c 0 3ed5 0 39e8 0 294b
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 2529 0 2944 0 3dfb 0 4082 0 377c 0 3b85 0 3b88 0 3e03
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 247e 0 2730 0 3844 0 4235 0 252d 0 2ab0 0 27e7 0 314b
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 3775 0 3452 0 35e4 0 6e90 0 3ab3 0 36b0 0 2cda 0 2333
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 3082 0 2c19 0 6a51 0 2893 0 4856 0 4dc4 0 2d94 0 29fe
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 21e1 0 2528 0 2d8f 0 3d25 0 3087 0 3914 0 3b87 0 314a
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 2942 0 25d3 0 2945 0 3206 0 2f09 0 35e6 0 3394 0 35e9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 247d 0 2cd2 0 2945 0 2fc5 0 252c 0 3087 0 21e6 0 2332
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
// Color # 1: Pixels input range: 0.000000 ... 376.589752
//8 // shift_x, 7 bits
//30 // shift_y, 7 bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 3518 0 3a39 0 3bf8 0 5c00 0 4334 0 4424 0 5e26 0 3dc6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 3958 0 3cda 0 37a3 0 46f2 0 3cdd 0 4161 0 4fb2 0 4516
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 329e 0 30ff 0 35f2 0 3881 0 3ea6 0 3b1d 0 36cf 0 3ce3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 36c7 0 387e 0 3446 0 3448 0 351d 0 35f7 0 3960 0 3a41
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 302f 0 3446 0 395b 0 37a5 0 3375 0 344b 0 35f7 0 31d6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 37a1 0 2dd1 0 3446 0 2e9d 0 3449 0 31d4 0 32a5 0 337a
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 30fe 0 4245 0 3372 0 31d2 0 351e 0 3520 0 32a5 0 2f6d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 3030 0 351c 0 31d0 0 3034 0 3449 0 32a5 0 2b82 0 2f6d
// Color # 2: Pixels input range: 0.000000 ... 390.304718
//62 // shift_x, 7 bits
//a // shift_y, 7 bits
14b5 0 1565 0 13b3 0 14b6 0 1d97 0 1b3f 0 16d0 0 1787 0
0 1503 0 14ab 0 14ab 0 1a1b 0 1ed6 0 16c9 0 166e 0 1457
16cc 0 18f9 0 195a 0 1b3d 0 1d97 0 5ce5 0 195c 0 16d0 0
0 13a5 0 1c6c 0 1e04 0 195a 0 261c 0 1e07 0 1e07 0 183e
14b5 0 189b 0 1b3d 0 195a 0 1e64 0 189d 0 26e6 0 1ecd 0
0 1a18 0 19b8 0 1454 0 6194 0 1a7c 0 1a7e 0 5216 0 1ed9
1727 0 17e0 0 189c 0 16cd 0 183f 0 1ba1 0 1ecd 0 2006 0
0 1503 0 1351 0 14ab 0 1505 0 1a1b 0 1ae0 0 1a1c 0 1da2
14b5 0 1408 0 1409 0 150e 0 18fc 0 1add 0 1ade 0 1ade 0
0 166a 0 183b 0 1504 0 155e 0 183c 0 16c9 0 183d 0 195c
1671 0 183d 0 14b6 0 1566 0 13b4 0 189d 0 15c1 0 18fd 0
0 160f 0 14ab 0 13fd 0 1780 0 17de 0 13ff 0 1725 0 1457
150d 0 1408 0 15bf 0 15bf 0 140a 0 19ba 0 14b8 0 1568 0
0 1252 0 1504 0 1a19 0 1352 0 1455 0 1255 0 14ad 0 1457
1565 0 135d 0 14b6 0 1409 0 1619 0 189d 0 130b 0 161b 0
0 13a5 0 177f 0 1351 0 12fc 0 12fc 0 1613 0 12fd 0 13a9
// Color=0, signs table (per mode, per index - bitstring of variants, 0 - positive, 1 - negative)
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
5 5 5 5 f f f f 5 5 5 5 f f f f
5 5 5 5 f f f f 5 5 5 5 f f f f
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
f f f f a a a a f f f f a a a a
f f f f a a a a f f f f a a a a
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
a a a a 0 0 0 0 a a a a 0 0 0 0
a a a a 0 0 0 0 a a a a 0 0 0 0
// Color=1, signs table (per mode, per index - bitstring of variants, 0 - positive, 1 - negative)
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
5 5 5 5 f f f f 5 5 5 5 f f f f
5 5 5 5 f f f f 5 5 5 5 f f f f
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
f f f f a a a a f f f f a a a a
f f f f a a a a f f f f a a a a
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
a a a a 0 0 0 0 a a a a 0 0 0 0
a a a a 0 0 0 0 a a a a 0 0 0 0
// Color=2, signs table (per mode, per index - bitstring of variants, 0 - positive, 1 - negative)
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
0 0 0 0 5 5 5 5 0 0 0 0 5 5 5 5
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
5 5 5 5 f f f f 5 5 5 5 f f f f
5 5 5 5 f f f f 5 5 5 5 f f f f
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
3 3 3 3 6 6 6 6 3 3 3 3 6 6 6 6
f f f f a a a a f f f f a a a a
f f f f a a a a f f f f a a a a
6 6 6 6 c c c c 6 6 6 6 c c c c
6 6 6 6 c c c c 6 6 6 6 c c c c
a a a a 0 0 0 0 a a a a 0 0 0 0
a a a a 0 0 0 0 a a a a 0 0 0 0
// Color = 0, absolute values, mode0 (CC), others are the same
123ac e608 f353 bfe6 1561b 9f8d 11d65 851a 17b64 52f0 13c80 4531 19218 324 14f71 29f
4cc8 19959 400d 1557e 99c0 190df 8043 14e6b e0d0 178fd bb8b 13a7f 11f3c 1529e ef9e 11a7c
148d0 10353 b99f 9265 181ab b3de d9b8 658a 1abb3 5d80 f172 34c8 1c54c 38a ffe5 200
568f 1cd79 30dd 10483 ad54 1c3ea 61d9 ff1e fd70 1a8fe 8f12 efeb 143cf 17dbc b6cc d77f
16152 116a6 78ca 5f43 19e69 c146 8dac 4213 1cb93 6478 9d1d 2259 1e714 3ce a684 14d
5d02 1efdd 1fcc a985 ba3f 1e598 3fac a602 11053 1c8aa 5d19 9c1e 15bf1 19a2f 76f3 8c3a
16c3f 11f45 3350 2878 1ab3a c740 3c2f 1c12 1d9ca 6793 42be e97 1f625 3ec 46bd 8d
5fe2 1ff33 d82 4804 c001 1f49d 1b0c 4686 118bf 1d6ca 278d 4252 166b3 1a6df 3288 3b92
1423 fe1 1692d 11cd9 179e b04 1a7a0 c592 1a31 5ba 1d5cb 66b4 1bc2 37 1f1e9 3e3
54d 1c42 5f14 1fae4 a9d 1bac be63 1f065 f85 1a06 11662 1d2d2 13d4 1760 163ad 1a34e
5acf 479e 1583a 10f7a 6a83 31ad 193be bc4c 761e 19d2 1bfbf 61e2 7d30 fa 1da8b 3b5
17e8 7f72 5a9d 1e31a 2fde 7ccf b574 1d919 45fe 755f 10951 1bce9 596d 696d 152fc 18fa0
9dfe 7c9b 13a0c f7ad b950 566d 17059 abca cd82 2ced 1987e 594d d9cf 1b3 1b0f0 361
2997 ddbc 52ac 1b8bf 5349 d925 a58b 1af9f 79c7 cc35 f20e 195e7 9b97 b76c 13544 16c97
db1b accd 10fcc d65c 100fe 77db 13ecb 94ae 11d00 3e4e 1618a 4d4a 12e0e 25c 176b2 2ed
39ae 13381 478c 17d75 737f 12d23 8f46 1758e a8e1 11b32 d17e 15f4d d7c5 fe5f 10ba9 13b8b
// Color = 1, absolute values, mode0 (CC), others are the same
11bbc e7b5 e195 b837 144db aac6 10247 87c6 1617f 6747 1190c 521c 1708d 1fd1 12504 194b
28df 17172 207f 125b9 6ffd 16424 5909 11b25 b2cd 14926 8e27 105b0 eebe 12182 bdcf e62c
14afb 10e4a 9ec2 81a6 17af4 c736 b5c5 5f8e 19c5d 787a c5cb 39ca 1aded 251d ce38 11cd
2fae 1aef7 16de ceb8 82a3 19f72 3ea9 c746 d093 17ff5 640b b82b 1167f 151b8 8595 a1fd
16d83 12a7d 55d6 4619 1a27d dbfe 6247 33aa 1c762 850c 6af1 1f3e 1dac7 28fc 6f7f 9a0
34a7 1dbed c5d 6fc4 9044 1cac9 21e1 6bbd e655 1a804 3617 6393 1338d 174f3 4839 5795
181ff 13b37 99d 7da 1b9f1 e853 b02 5c9 1e0e7 8c80 bfa 380 1f562 2b48 c7d 114
379a 1f699 163 c85 9859 1e47f 3cb c11 f33e 1bfc7 60f b27 144c9 189d9 817 9cf
42fa 36b2 187a5 13fd4 4caf 2850 1c069 ebb9 5372 1861 1e7f1 8e8f 5700 783 1fcb9 2bea
9a6 5736 386b 1fdf4 1a6f 5411 9a94 1eb97 2a35 4db2 f6cd 1c655 385b 4457 1498a 18f9d
8cfe 7324 17e3e 13827 a16e 54dc 1b5a5 e611 afa9 3352 1dc3b 8b23 b724 fcf 1f083 2adc
144f b796 3710 1f1b7 37a6 b0f9 96de 1dfca 58d9 a390 f0e1 1bb6d 76a3 8fdd 141a1 18606
d198 ab29 16627 1247b eff8 7e26 19a10 d791 10520 4c4b 1be37 825e 1103f 1780 1d138 2829
1e31 110e8 3398 1d259 52b9 10714 8d5c 1c18d 8414 f324 e1b2 19f7b b05b d5db 12d5c 16d71
10e23 dc9a 1404d 10591 1354a a297 16eb9 c0c8 1508f 6254 18f0e 7497 15ee4 1e4a 1a00d 23ea
26ea 15fbe 2e24 1a10f 6a9f 15313 7e6b 19209 aa3b 13960 c9d8 17391 e34d 113a2 10d82 146d1
// Color = 2, absolute values, mode0 (CC), others are the same
13923 10586 ff66 d54d 160b8 c7db 11fae a301 17abf 8283 134e8 6a72 18638 3826 13e44 2dcc
145f 182b2 109d 13b64 601b 1704f 4e63 12c65 a826 14fc6 8925 111dc e9bb 12254 bea2 eccc
166d8 12bb2 bbd7 9ce1 19434 e507 d396 77e3 1b208 958f e333 4e4a 1bf2d 4058 ea14 21af
1758 1bb23 c38 e7f7 6e23 1a612 39a7 dcf0 c0b2 180c8 64de c96b 10bd9 14cb5 8c35 ae29
186c3 1465a 7111 5e6e 1b828 f966 7f5c 482a 1d8a2 a2dd 88c2 2f20 1e6f3 4611 8ce6 1446
196c 1e28d 75b 8ba1 77ee 1cb9c 22b4 84fd d1d5 1a302 3cb7 793e 123ac 16a4d 5465 68d5
197a9 15477 21f3 1c5a 1cb31 1042f 263d 15ab 1ed13 a9e8 2910 e26 1fc02 4919 2a4e 616
1a85 1f76c 235 29ec 7d1e 1df7d a6b 27ee dae8 1b521 123b 2467 13049 179f8 1957 1f7a
2e7a 26d1 198e5 1557f 345a 1daa 1cc95 104f9 3836 135f 1ee91 aa6c 39ea 855 1fd8c 4952
306 3964 1a9a 1f8f2 e44 36aa 7d7f 1e0f0 18f5 31d6 db92 1b673 22b1 2b17 13135 17b1d
7d1d 687d 18a6a 14967 8ced 4fda 1bc45 fbbb 9754 3425 1dd0e a463 9be9 166f 1eb81 46b9
824 9a81 19a8 1e710 2666 9328 790d 1cfe8 432f 8628 d3cb 1a6ed 5d63 7400 12666 16db0
c6f1 a626 16cc7 130a6 e017 7ef9 19ae3 e8d1 f0a0 52ea 1b935 9808 f7ea 23ac 1c692 4169
cf1 f5ad 17bb 1c277 3d0f e9ff 6ff5 1ad0d 6ad4 d553 c3e1 18725 947e b874 11047 15236
10921 dd6d 1411f 10c31 12aa4 a937 169b7 ccf4 140ad 6e80 18468 85d7 14a64 2f8a 1902b 3995
113f 14768 14e4 18c8e 515f 137d7 628f 179b4 8e5e 11c4b ac70 15856 c5e5 f5d1 efb1 129bc
// Color= 0, DTT input range: -834.569640 ... 834.569640
// Color=0 fpga_clt_data_out[chn][dct_mode] = dtt.dttt_iv(..., scale=16383.750000953674
333a90 1ad141 3a26b1 8d34 42bb14 1eb53f1 32b2ad 1dc988e
495056 29d2f4 511327 ae76 6e3928 1e90ffd 4ba150 1d100b1
16e551 8bfdd 16d009 2dc3 1fa1c0 1f6ecaf 192ac3 1eb2ccd
6ea520 237954 85dfdd a4a4 51047c 1db9e9a c384cf 1c235b7
1fb0edb 1fd8237 1f881f1 1fff70d 1f8f910 20adb 1f944eb 4abf0
49894c 20fda2 66aa53 826e d0a3a4 1d8b13f 5da81c 1bab837
1db4488 1ebe6ec 1d3759d 1ff968a 1c820cf c16b3 1ce8eef 191438
2d52a7 172c5b 335648 9038 62a6b9 1eb93ad 4d3620 1d7072b
1ccc570 1ad141 1c5d94f 8d34 1bd44ec 1eb53f1 1cd4d53 1dc988e
1b6afaa 29d2f4 1aeecd9 ae76 191c6d8 1e90ffd 1b45eb0 1d100b1
1e91aaf 8bfdd 1e92ff7 2dc3 1e05e40 1f6ecaf 1e6d53d 1eb2ccd
1915ae0 237954 17a2023 a4a4 1aefb84 1db9e9a 13c7b31 1c235b7
4f125 1fd8237 77e0f 1fff70d 706f0 20adb 6bb15 4abf0
1b676b4 20fda2 19955ad 826e 12f5c5c 1d8b13f 1a257e4 1bab837
24bb78 1ebe6ec 2c8a63 1ff968a 37df31 c16b3 317111 191438
1d2ad59 172c5b 1cca9b8 9038 19d5947 1eb93ad 1b2c9e0 1d7072b
333a90 1ad141 3a26b1 8d34 42bb14 1eb53f1 32b2ad 1dc988e
1b6afaa 1d62d0c 1aeecd9 1ff518a 191c6d8 16f003 1b45eb0 2eff4f
16e551 8bfdd 16d009 2dc3 1fa1c0 1f6ecaf 192ac3 1eb2ccd
1915ae0 1dc86ac 17a2023 1ff5b5c 1aefb84 246166 13c7b31 3dca49
1fb0edb 1fd8237 1f881f1 1fff70d 1f8f910 20adb 1f944eb 4abf0
1b676b4 1df025e 19955ad 1ff7d92 12f5c5c 274ec1 1a257e4 4547c9
1db4488 1ebe6ec 1d3759d 1ff968a 1c820cf c16b3 1ce8eef 191438
1d2ad59 1e8d3a5 1cca9b8 1ff6fc8 19d5947 146c53 1b2c9e0 28f8d5
1ccc570 1ad141 1c5d94f 8d34 1bd44ec 1eb53f1 1cd4d53 1dc988e
495056 1d62d0c 511327 1ff518a 6e3928 16f003 4ba150 2eff4f
1e91aaf 8bfdd 1e92ff7 2dc3 1e05e40 1f6ecaf 1e6d53d 1eb2ccd
6ea520 1dc86ac 85dfdd 1ff5b5c 51047c 246166 c384cf 3dca49
4f125 1fd8237 77e0f 1fff70d 706f0 20adb 6bb15 4abf0
49894c 1df025e 66aa53 1ff7d92 d0a3a4 274ec1 5da81c 4547c9
24bb78 1ebe6ec 2c8a63 1ff968a 37df31 c16b3 317111 191438
2d52a7 1e8d3a5 335648 1ff6fc8 62a6b9 146c53 4d3620 28f8d5
// Color= 1, DTT input range: -436.787688 ... 436.787688
// Color=1 fpga_clt_data_out[chn][dct_mode] = dtt.dttt_iv(..., scale=16383.750000953674
373a1d 21c8b8 4831dc 665a8 434523 1e7aa79 4335aa 1d54594
20f225 12e742 2909ff 34c35 283a98 1f40239 2502df 1dd6b60
4aa91c 2e5fe1 5b87a9 7fa8b 677368 1e4d898 5efea7 1c1338d
1e6ed fbc1 27247 3320 25b75 1ff4925 22b91 1fe525f
528eec 34d45e 653cf0 9fe2c 68255e 1deec78 5cc502 1b7474a
1da7881 1e0ca9b 1d1e35f 1fc2f64 1be05f6 b8aaf 1d9af39 1afafe
52b3f6 2e2665 6d31fc 98d1d 66eda7 1e40cf9 578cbe 1c6521f
1bb0365 1cd6251 1affc10 1f7d362 19e864a 17e1e5 1bbe55e 3607b5
1c8c5e3 21c8b8 1b7ce24 665a8 1bcbadd 1e7aa79 1bcca56 1d54594
1df0ddb 12e742 1d6f601 34c35 1d7c568 1f40239 1dafd21 1dd6b60
1b556e4 2e5fe1 1a47857 7fa8b 1988c98 1e4d898 1a10159 1c1338d
1fe1913 fbc1 1fd8db9 3320 1fda48b 1ff4925 1fdd46f 1fe525f
1ad7114 34d45e 19ac310 9fe2c 197daa2 1deec78 1a33afe 1b7474a
25877f 1e0ca9b 2e1ca1 1fc2f64 41fa0a b8aaf 2650c7 1afafe
1ad4c0a 2e2665 192ce04 98d1d 1991259 1e40cf9 1a87342 1c6521f
44fc9b 1cd6251 5003f0 1f7d362 6179b6 17e1e5 441aa2 3607b5
1c8c5e3 1de3748 1b7ce24 1f99a58 1bcbadd 185587 1bcca56 2aba6c
20f225 12e742 2909ff 34c35 283a98 1f40239 2502df 1dd6b60
1b556e4 1d1a01f 1a47857 1f80575 1988c98 1b2768 1a10159 3ecc73
1e6ed fbc1 27247 3320 25b75 1ff4925 22b91 1fe525f
1ad7114 1cb2ba2 19ac310 1f601d4 197daa2 211388 1a33afe 48b8b6
1da7881 1e0ca9b 1d1e35f 1fc2f64 1be05f6 b8aaf 1d9af39 1afafe
1ad4c0a 1d1d99b 192ce04 1f672e3 1991259 1bf307 1a87342 39ade1
1bb0365 1cd6251 1affc10 1f7d362 19e864a 17e1e5 1bbe55e 3607b5
373a1d 1de3748 4831dc 1f99a58 434523 185587 4335aa 2aba6c
1df0ddb 12e742 1d6f601 34c35 1d7c568 1f40239 1dafd21 1dd6b60
4aa91c 1d1a01f 5b87a9 1f80575 677368 1b2768 5efea7 3ecc73
1fe1913 fbc1 1fd8db9 3320 1fda48b 1ff4925 1fdd46f 1fe525f
528eec 1cb2ba2 653cf0 1f601d4 68255e 211388 5cc502 48b8b6
25877f 1e0ca9b 2e1ca1 1fc2f64 41fa0a b8aaf 2650c7 1afafe
52b3f6 1d1d99b 6d31fc 1f672e3 66eda7 1bf307 578cbe 39ade1
44fc9b 1cd6251 5003f0 1f7d362 6179b6 17e1e5 441aa2 3607b5
// Color= 2, DTT input range: -341.093520 ... 345.703701
// Color=2 fpga_clt_data_out[chn][dct_mode] = dtt.dttt_iv(..., scale=16383.750000953674
14dc5b 177d66 161ad7 eafb3 11111f 89e16 7be19 9f1c
137570 184615 105239 128be3 7baa8 f93c6 1251b 7b42e
14e6d2 11edeb 186789 98d53 13d485 1fff415 ee6b9 1f6703a
13544a 18e501 a7038 1905be 7b67 135145 1f8cf29 da06f
13bba3 a85b7 18532a e56d 14d9e3 1f8a38d 12be30 1f2d412
e3f74 147a29 12b09 1662b6 1f6f663 163c70 1f0b547 1558dc
aa4c3 1fcab68 1320f2 1f59d04 566cb3 1edd85c 14bd73 1e9308c
4d35a 77725 1f02f16 158059 1eef1ed 15d2a9 1e70bd2 1ad35d
1fc670b 1fa9443 1f2cbd9 1f5c658 1ed9127 1ef19da 1ed86e5 1ec81e7
6022b 1f168de 1fe4706 1f02130 1f63973 1ec4c10 1ec9c6a 1ecc97c
1f21f78 5af0c 1ebaa18 1fd638a 1eb8e1e 1f58bca 1ec81b1 1edf50e
1066f6 1e8b673 764a3 1e771f1 1fd5f75 1ebe209 1f61011 1f00c29
1e8ceec 101806 1e5e51d 79727 1eb64b9 1fd0fbe 1ef57c4 1f624f2
19622c 1e486ef 136534 1e7d4fb 6b78a 1ecea5a 1fb8a3a 1f23165
1e4e5ad 4dfbba 1e57b9d 1244a8 1aaba59 6be4f 1f5ae81 1fb7462
23ecc4 1e4af93 1feb36 1e5ff1b f5d7f 1f06bfb 86149 1fb252f
1fc670b 56bbd 1f2cbd9 a39a8 1ed9127 10e626 1ed86e5 137e19
1f9fdd5 1f168de 1b8fa 1f02130 9c68d 1ec4c10 136396 1ecc97c
1f21f78 1fa50f4 1ebaa18 29c76 1eb8e1e a7436 1ec81b1 120af2
1ef990a 1e8b673 1f89b5d 1e771f1 2a08b 1ebe209 9efef 1f00c29
1e8ceec 1efe7fa 1e5e51d 1f868d9 1eb64b9 2f042 1ef57c4 9db0e
1e69dd4 1e486ef 1ec9acc 1e7d4fb 1f94876 1ecea5a 475c6 1f23165
1e4e5ad 1b20446 1e57b9d 1edbb58 1aaba59 1f941b1 1f5ae81 48b9e
1dc133c 1e4af93 1e014ca 1e5ff1b 1f0a281 1f06bfb 1f79eb7 1fb252f
14dc5b 1e8829a 161ad7 1f1504d 11111f 1f761ea 7be19 1ff60e4
1ec8a90 184615 1efadc7 128be3 1f84558 f93c6 1fedae5 7b42e
14e6d2 1ee1215 186789 1f672ad 13d485 beb ee6b9 98fc6
1ecabb6 18e501 1f58fc8 1905be 1ff8499 135145 730d7 da06f
13bba3 1f57a49 18532a 1ff1a93 14d9e3 75c73 12be30 d2bee
1f1c08c 147a29 1fed4f7 1662b6 9099d 163c70 f4ab9 1558dc
aa4c3 35498 1320f2 a62fc 566cb3 1227a4 14bd73 16cf74
1fb2ca6 77725 fd0ea 158059 110e13 15d2a9 18f42e 1ad35d
// Color = 0: DTT output range: -1011.350890 ... 1011.350890
6d7ef1 1f5561e 1fa4600 6ecd8 1fbf19a 81ea5 1f38692 193cef1
1f6325e d0fb2 1fb1d84 3b2d 6203e 1fd6529 1fbb191 15a134
b0d4a 1ffc55f 1eedf90 1ff53a3 12996e 1fd823f 1f56123 1f6e51f
1fffff4 1fd0959 1837dd 1fe6540 1e49ea4 ab72 112e8d 1fb5d8f
6e2a5 1fc4655 1f73d37 9f1c a7ea7 1d04b 1f9df6c 1f99065
1fc781f 46018 1ee1c0c 1ffe7b6 1386ca edc4 1f49b09 b2998
76e8c 1fd2a27 79339 2c577 1f4b11b 387d9 10c2b 1f76562
794dfc 1e9028a 1f9c6dd 6058e 1ff437a e3b7c 1f654e2 1819544
186b204 16fd76 63923 1f9fa72 bc86 1f1c484 9ab1e 7e6abc
1f89174 2d5d9 1f86cc7 1fd3a89 b4ee5 1fc7827 1fef3d5 89a9e
387e1 1fb9fe8 11e3f4 184a 1ec7936 1ff123c b64f7 1f4d668
1f91d5b 3b9ab 8c2c9 1ff60e4 1f58159 1fe2fb5 62094 66f9b
c 2f6a7 1e7c823 19ac0 1b615c 1ff548e 1eed173 4a271
1f4f2b6 3aa1 112070 ac5d 1ed6692 27dc1 a9edd 91ae1
9cda2 1f2f04e 4e27c 1ffc4d3 1f9dfc2 29ad7 44e6f 1ea5ecc
192810f aa9e2 5ba00 1f91328 40e66 1f7e15b c796e 6c310f
193cef1 1f38692 81ea5 1fbf19a 6ecd8 1fa4600 1f5561e 6d7ef1
15a134 1fbb191 1fd6529 6203e 3b2d 1fb1d84 d0fb2 1f6325e
1f6e51f 1f56123 1fd823f 12996e 1ff53a3 1eedf90 1ffc55f b0d4a
1fb5d8f 112e8d ab72 1e49ea4 1fe6540 1837dd 1fd0959 1fffff4
1f99065 1f9df6c 1d04b a7ea7 9f1c 1f73d37 1fc4655 6e2a5
b2998 1f49b09 edc4 1386ca 1ffe7b6 1ee1c0c 46018 1fc781f
1f76562 10c2b 387d9 1f4b11b 2c577 79339 1fd2a27 76e8c
1819544 1f654e2 e3b7c 1ff437a 6058e 1f9c6dd 1e9028a 794dfc
7e6abc 9ab1e 1f1c484 bc86 1f9fa72 63923 16fd76 186b204
89a9e 1fef3d5 1fc7827 b4ee5 1fd3a89 1f86cc7 2d5d9 1f89174
1f4d668 b64f7 1ff123c 1ec7936 184a 11e3f4 1fb9fe8 387e1
66f9b 62094 1fe2fb5 1f58159 1ff60e4 8c2c9 3b9ab 1f91d5b
4a271 1eed173 1ff548e 1b615c 19ac0 1e7c823 2f6a7 c
91ae1 a9edd 27dc1 1ed6692 ac5d 112070 3aa1 1f4f2b6
1ea5ecc 44e6f 29ad7 1f9dfc2 1ffc4d3 4e27c 1f2f04e 9cda2
6c310f c796e 1f7e15b 40e66 1f91328 5ba00 aa9e2 192810f
// Color = 0 Testing symmetry of checkerboard patterns
// dafde2 1eaac3c 1f48c00 dd9b0 1f7e334 103d4a 1e70d24 1279de2
// 1ec64bc 1a1f64 1f63b08 765a c407c 1faca52 1f76322 2b4268
// 161a94 1ff8abe 1ddbf20 1fea746 2532dc 1fb047e 1eac246 1edca3e
// 1ffffe8 1fa12b2 306fba 1fcca80 1c93d48 156e4 225d1a 1f6bb1e
// dc54a 1f88caa 1ee7a6e 13e38 14fd4e 3a096 1f3bed8 1f320ca
// 1f8f03e 8c030 1dc3818 1ffcf6c 270d94 1db88 1e93612 165330
// edd18 1fa544e f2672 58aee 1e96236 70fb2 21856 1eecac4
// f29bf8 1d20514 1f38dba c0b1c 1fe86f4 1c76f8 1eca9c4 1032a88
// 10d6408 2dfaec c7246 1f3f4e4 1790c 1e38908 13563c fcd578
// 1f122e8 5abb2 1f0d98e 1fa7512 169dca 1f8f04e 1fde7aa 11353c
// 70fc2 1f73fd0 23c7e8 3094 1d8f26c 1fe2478 16c9ee 1e9acd0
// 1f23ab6 77356 118592 1fec1c8 1eb02b2 1fc5f6a c4128 cdf36
// 18 5ed4e 1cf9046 33580 36c2b8 1fea91c 1dda2e6 944e2
// 1e9e56c 7542 2240e0 158ba 1dacd24 4fb82 153dba 1235c2
// 139b44 1e5e09c 9c4f8 1ff89a6 1f3bf84 535ae 89cde 1d4bd98
// 125021e 1553c4 b7400 1f22650 81ccc 1efc2b6 18f2dc d8621e
// Color = 0 Testing antisymmetry of checkerboard patterns
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// 0 0 0 0 0 0 0 0
// Color = 1: DTT output range: -1029.602364 ... 1029.602364
5d0f47 305dd 1faf9a2 1fe3384 19496 126e7 1f6f3a2 80b2c6
af9f 1fe7705 22782 34337 1feceaa 1ff012c 1fe4aaf 1ff4134
e676 1ee6 1ff8430 1fefa42 1ffe286 16160 250ce 1fedf1a