fixed axi simulation modules, added IRQ support (500cf616) · Commits · Elphel / x393

.project

+11 −11

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		@@ -62,52 +62,52 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160313162251081.log</location>
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		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160316003619053.log</location>
		</link>
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		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160313162251081.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160316003619053.log</location>
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		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160316003619053.log</location>
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		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160313162251081.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160316003619053.log</location>
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		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160313161825094.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160316003135844.log</location>
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		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313162251081.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160316003619053.log</location>
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		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
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		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160316003135844.log</location>
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		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
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		<name>vivado_state/x393-opt-phys.dcp</name>
		@@ -127,7 +127,7 @@
		<link>
		<name>vivado_state/x393-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160313161825094.dcp</location>
		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160316003135844.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

axi/cmprs_afi_mux_ptr_wresp.v

+2 −14

Original line number	Diff line number	Diff line
		@@ -67,7 +67,6 @@ module cmprs_afi_mux_ptr_wresp(
		reg [26:0] len_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
		reg [26:0] chunk_ptr_inc; // incremented by 1..4 chunk pointer
		reg [27:0] chunk_ptr_rovr; // incremented chunk pointer, decremented by length (MSB - sign)
		/// reg [ 3:0] busy; // one-hot busy stages (usually end with [3]
		reg [ 4:0] busy; // one-hot busy stages (usually end with [4]

		reg [ 4:0] id_r; // registered ID data - MSB is unused
		@@ -88,14 +87,9 @@ module cmprs_afi_mux_ptr_wresp(
		assign ptr_wa = {eof,chn}; // valid @busy[2]
		assign afi_bready = afi_bready_r;

		/// assign pre_we= resetting[0] \|\| // a pair of cycles to reset chunk pointer and frame chunk pointer
		/// busy[2] \|\| // always update chunk pointer
		/// (busy[3] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
		assign pre_we= resetting[0] \|\| // a pair of cycles to reset chunk pointer and frame chunk pointer
		busy[3] \|\| // always update chunk pointer
		(busy[4] && last_burst_in_frame); // optionally update frame chunk pointer (same value)
		/// assign pre_busy= afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we;
		/// assign start_resetting_w = !afi_bvalid_r && en && !(\|busy[1:0]) && !pre_we && (\|reset_rq);
		assign pre_busy= afi_bvalid_r && en && !(\|busy[2:0]) && !pre_we;
		assign start_resetting_w = !afi_bvalid_r && en && !(\|busy[2:0]) && !pre_we && (\|reset_rq);

		@@ -108,11 +102,10 @@ module cmprs_afi_mux_ptr_wresp(
		afi_bvalid_r <= afi_bvalid;

		afi_bready_r <= !en \|\| pre_busy; // (!busy[0] && !pre_busy && !resetting[0] && !start_resetting_w);
		// busy <= {busy[2:0], pre_busy}; // adjust bits
		busy <= {busy[3:0], pre_busy}; // adjust bits

		// id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
		if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
		// if (afi_bready && afi_bvalid) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved
		if (afi_bvalid && pre_busy) id_r <= afi_bid[4:0]; // id_r[5] is never used - revoved

		if (start_resetting_w) reset_rq_pri <= {reset_rq[3] & ~(\|reset_rq[2:0]),
		reset_rq[2] & ~(\|reset_rq[1:0]),
		@@ -126,10 +119,8 @@ module cmprs_afi_mux_ptr_wresp(
		else resetting <= {resetting[0], start_resetting_w \| (resetting[0] & ~resetting[1])};

		if (resetting == 2'b01) chn <= reset_rq_enc;
		/// else if (busy[0]) chn <= id_r[0 +: 2];
		else if (busy[1]) chn <= id_r[0 +: 2];

		/// if (busy[0]) begin // first busy cycle
		if (busy[1]) begin // first busy cycle
		last_burst_in_frame <= id_r[2];
		chunk_inc <= {1'b0,id_r[3 +:2]} + 1;
		@@ -140,9 +131,6 @@ module cmprs_afi_mux_ptr_wresp(
		if ((resetting == 2'b01) \|\| busy[0]) eof <= 0;
		else if (ptr_we) eof <= 1; // always second write cycle

		// @@@ delay by 1 clk
		/// if (busy[1]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
		/// if (busy[2]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy
		if (busy[2]) chunk_ptr_inc <= ptr_ram[ptr_wa] + chunk_inc; // second clock of busy
		if (busy[3]) chunk_ptr_rovr <={1'b0,chunk_ptr_inc} - {1'b0,len_ram[chn]}; // third clock of busy

compressor_jp/cmprs_status.v

+20 −3

Original line number	Diff line number	Diff line
		@@ -34,25 +34,42 @@
		`timescale 1ns/1ps

		module cmprs_status(
		input mrst,
		input mclk, // system clock
		input eof_written,
		input stuffer_running,
		input reading_frame,
		output [2:0] status
		input set_interrupts,
		input [1:0] data_in,
		output [4:0] status,
		output irq
		);

		reg stuffer_running_r;
		reg flushing_fifo;
		reg is_r; // interrupt status (not masked)
		reg im_r; // interrupt mask

		assign status = {flushing_fifo, stuffer_running_r, reading_frame};

		assign status = {flushing_fifo,
		stuffer_running_r,
		reading_frame,
		im_r, is_r};
		assign irq = is_r && im_r;

		always @(posedge mclk) begin
		if (mrst) im_r <= 0;
		else if (set_interrupts && data_in[1]) im_r <= data_in[0];

		if (mrst) is_r <= 0;
		else if (eof_written) is_r <= 1;
		else if (set_interrupts && (data_in == 1)) is_r <= 0;

		stuffer_running_r <= stuffer_running;

		if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;
		else if (eof_written) flushing_fifo <= 0;
		end


		endmodule

compressor_jp/compressor393.v

+10 −7

Original line number	Diff line number	Diff line
		@@ -54,6 +54,7 @@ module compressor393 # (
		parameter CMPRS_FORMAT= 2,
		parameter CMPRS_COLOR_SATURATION= 3,
		parameter CMPRS_CORING_MODE= 4,
		parameter CMPRS_INTERRUPTS= 5,
		parameter CMPRS_TABLES= 6, // 6..7
		parameter TABLE_QUANTIZATION_INDEX = 0,
		parameter TABLE_CORING_INDEX = 1,
		@@ -147,6 +148,7 @@ module compressor393 # (
		output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
		output status_rq, // input request to send status downstream
		input status_start, // Acknowledge of the first status packet byte (address)
		output [3:0] cmprs_irq, // Compressor done interruupt

		// Buffer interfaces, combined for 4 channels
		input [3:0] xfer_reset_page_rd, // from mcntrl_tiled_rw (
		@@ -280,7 +282,6 @@ module compressor393 # (
		wire [3:0] flush_hclk; // before last data was written
		wire [31:0] fifo_count;

		/* Instance template for module status_router8 */
		status_router8 status_router8_i (
		.rst (1'b0), //rst), // input
		.clk (mclk), // input
		@@ -339,6 +340,7 @@ module compressor393 # (
		.CMPRS_FORMAT (CMPRS_FORMAT),
		.CMPRS_COLOR_SATURATION (CMPRS_COLOR_SATURATION),
		.CMPRS_CORING_MODE (CMPRS_CORING_MODE),
		.CMPRS_INTERRUPTS (CMPRS_INTERRUPTS),
		.CMPRS_TABLES (CMPRS_TABLES),
		.TABLE_QUANTIZATION_INDEX (TABLE_QUANTIZATION_INDEX),
		.TABLE_CORING_INDEX (TABLE_CORING_INDEX),
		@@ -414,6 +416,7 @@ module compressor393 # (
		.status_ad (status_ad_mux[8 * i +: 8]), // output[7:0]
		.status_rq (status_rq_mux[i]), // output
		.status_start (status_start_mux[i]), // input
		.irq (cmprs_irq[i]), // output
		.xfer_reset_page_rd (xfer_reset_page_rd[i]), // input
		.buf_wpage_nxt (buf_wpage_nxt[i]), // input
		.buf_we (buf_we[i]), // input

compressor_jp/jp_channel.v

+42 −43

Original line number	Diff line number	Diff line
		@@ -47,6 +47,7 @@ module jp_channel#(
		parameter CMPRS_FORMAT= 2,
		parameter CMPRS_COLOR_SATURATION= 3,
		parameter CMPRS_CORING_MODE= 4,
		parameter CMPRS_INTERRUPTS= 5,
		parameter CMPRS_TABLES= 6, // 6(data)..7(address)
		parameter TABLE_QUANTIZATION_INDEX = 0,
		parameter TABLE_CORING_INDEX = 1,
		@@ -116,7 +117,6 @@ module jp_channel#(
		`endif

		)(
		// input rst, // global reset
		input xclk, // global clock input, compressor single clock rate
		`ifdef USE_XCLK2X
		input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
		@@ -132,6 +132,7 @@ module jp_channel#(
		output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
		output status_rq, // input request to send status downstream
		input status_start, // Acknowledge of the first status packet byte (address)
		output irq, // processor interrupt

		// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
		input xfer_reset_page_rd, // from mcntrl_tiled_rw (
		@@ -140,10 +141,6 @@ module jp_channel#(
		input buf_we, // @!mclk write buffer from memory, increment write
		input [63:0] buf_din, // data out

		// output [11:0] buf_ra,
		// output buf_ren,
		// output buf_regen,
		// input [ 7:0] buf_di,

		input page_ready_chn, // single mclk (posedge)
		output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
		@@ -186,8 +183,8 @@ module jp_channel#(
		input fifo_rst, // reset FIFO (set read address to write, reset count)
		input fifo_ren,
		output [63:0] fifo_rdata,
		output fifo_eof, // single rclk pulse signalling EOF
		input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
		output fifo_eof, // single rclk pulse signaling EOF
		input eof_written, // confirm frame written over AFI to the system memory (single rclk pulse)
		output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
		output flush_hclk, // output before writing last chunk - use it to suspend AFI to have
		// last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks)
		@@ -313,16 +310,9 @@ module jp_channel#(
		wire enc_dv;

		//TODO: use next signals for status
		// wire eof_written_mclk;
		// wire stuffer_done_mclk;
		wire stuffer_running_mclk;
		wire reading_frame;

		/// wire last_block; //huffman393
		/// wire test_lbw;



		`ifdef USE_XCLK2X
		wire [15:0] huff_do; // output[15:0] reg
		wire [3:0] huff_dl; // output[3:0] reg
		@@ -342,6 +332,7 @@ module jp_channel#(
		wire set_format_w;
		wire set_color_saturation_w;
		wire set_coring_w;
		wire set_interrupts_w;
		wire set_tables_w;

		wire stuffer_running; // @negedge xclk2x from registering timestamp until done
		@@ -353,6 +344,7 @@ module jp_channel#(
		wire [ 2:0] coring_num;
		reg dcc_en;


		wire [15:0] dccdata; // was not used in late nc353
		wire dccvld; // was not used in late nc353

		@@ -361,8 +353,10 @@ module jp_channel#(
		assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT);
		assign set_color_saturation_w = cmd_we && (cmd_a== CMPRS_COLOR_SATURATION);
		assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
		assign set_interrupts_w = cmd_we && (cmd_a== CMPRS_INTERRUPTS);
		assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);


		`ifdef USE_XCLK2X
		// re-sync to posedge xclk2x
		reg xrst2xn;
		@@ -586,18 +580,23 @@ module jp_channel#(
		.data (cmd_data), // output[31:0]
		.we (cmd_we) // output
		);
		wire [2:0] status_data;

		wire [4:0] status_data;
		cmprs_status cmprs_status_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		.eof_written (eof_written_mclk), // input
		.stuffer_running (stuffer_running_mclk), // input
		.reading_frame (reading_frame), // input
		.status (status_data) // output[2:0]
		.set_interrupts (set_interrupts_w), // input
		.data_in (cmd_data[1:0]), // input[1:0]
		.status (status_data), // output[2:0]
		.irq (irq) // output
		);

		status_generate #(
		.STATUS_REG_ADDR (CMPRS_STATUS_REG_ADDR),
		.PAYLOAD_BITS (3),
		.PAYLOAD_BITS (7),
		.EXTRA_WORDS (1),
		.EXTRA_REG_ADDR (CMPRS_HIFREQ_REG_ADDR)

		@@ -607,7 +606,7 @@ module jp_channel#(
		.srst (mrst), // input
		.we (set_status_w), // input
		.wd (cmd_data[7:0]), // input[7:0]
		.status ({hifreq,status_data}), // input[2:0]
		.status ({hifreq,status_data,2'b0}), // input[2:0]
		.ad (status_ad), // output[7:0]
		.rq (status_rq), // output
		.start (status_start) // input

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