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Commit 023b0015 authored by Andrey Filippov's avatar Andrey Filippov
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removing accidentally committed unisims library

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unisims/AND2B1L.v deleted 100644 → 0
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.i (L.40)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Latch used as 2-input AND Gate
// /___/ /\ Filename : AND2B1L.v
// \ \ / \ Timestamp : Wed Apr 22 17:10:55 PDT 2009
// \___\/\___\
//
// Revision:
// 04/01/08 - Initial version.
// 04/14/09 - Invert SRI not DI (CR517897)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AND2B1L #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_SRI_INVERTED = 1'b0
)(
output O,
input DI,
input SRI
);
tri0 GSR = glbl.GSR;
wire o_out, sri_b;
wire SRI_in;
assign O = (GSR) ? 0 : o_out;
not A0 (sri_b, SRI_in);
and A1 (o_out, sri_b, DI);
assign SRI_in = IS_SRI_INVERTED ^ SRI;
`ifdef XIL_TIMING
specify
(DI => O) = (0:0:0, 0:0:0);
(SRI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/AUTOBUF.v deleted 100644 → 0
View file @ b8763e26
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AUTOBUF.v,v 1.2 2008/09/04 22:14:49 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BIBUF.v deleted 100644 → 0
View file @ b8763e26
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.1
// \ \ Description : Xilinx Simulation Library Component
// / / Bi-Directional IO
// /___/ /\ Filename : BIBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BIBUF (PAD, IO);
inout PAD;
inout IO;
wire PAD_io;
wire IO_io;
assign #10 PAD_io = PAD;
assign #10 IO_io = IO;
assign (weak1, weak0) IO = PAD_io;
assign (weak1, weak0) PAD = IO_io;
endmodule
`endcelldefine
unisims/BITSLICE_CONTROL.v deleted 100644 → 0
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unisims/BSCANE2.v deleted 100644 → 0
View file @ b8763e26
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Boundary Scan Logic Control Circuit for VIRTEX7
// /___/ /\ Filename : BSCANE2.v
// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010
// \___\/\___\
//
// Revision:
// 02/08/10 - Initial version.
// 06/10/11 - CR 613789.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 11/13/13 - Update default value of JTAG_CHAIN to 1 (CR 759814).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BSCANE2 (
CAPTURE,
DRCK,
RESET,
RUNTEST,
SEL,
SHIFT,
TCK,
TDI,
TMS,
UPDATE,
TDO
);
parameter DISABLE_JTAG = "FALSE";
parameter integer JTAG_CHAIN = 1;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CAPTURE;
output DRCK;
output RESET;
output RUNTEST;
output SEL;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO;
reg SEL_zd;
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
//--####################################################################
//--##### Initialization ###
//--####################################################################
initial begin
//-------- JTAG_CHAIN
if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin
$display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN);
$finish;
end
end
//--####################################################################
//--##### Jtag_select ###
//--####################################################################
always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin
if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL;
else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL;
else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL;
else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL;
end
//--####################################################################
//--####################################################################
//--##### USER_TDO ###
//--####################################################################
always@(TDO) begin
if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO;
else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO;
else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO;
else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO;
end
//--####################################################################
//--##### Output ###
//--####################################################################
assign CAPTURE = glbl.JTAG_CAPTURE_GLBL;
assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL)
||
(SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL)
||
(SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL));
assign RESET = glbl.JTAG_RESET_GLBL;
assign RUNTEST = glbl.JTAG_RUNTEST_GLBL;
assign SEL = SEL_zd;
assign SHIFT = glbl.JTAG_SHIFT_GLBL;
assign TDI = glbl.JTAG_TDI_GLBL;
assign TCK = glbl.JTAG_TCK_GLBL;
assign TMS = glbl.JTAG_TMS_GLBL;
assign UPDATE = glbl.JTAG_UPDATE_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUF.v deleted 100644 → 0
View file @ b8763e26
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / General Purpose Buffer
// /___/ /\ Filename : BUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUF (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
unisims/BUFCE_LEAF.v deleted 100644 → 0
View file @ b8763e26
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_LEAF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_LEAF #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_LEAF_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_I_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
specify
`ifdef XIL_TIMING // Simprim
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
unisims/BUFCE_ROW.v deleted 100644 → 0
View file @ b8763e26
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_ROW.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_ROW #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_ROW";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
`ifndef XIL_DR
localparam CE_TYPE_REG = CE_TYPE;
localparam IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_ROW_dr.v"
`endif
wire O_out;
wire O_delay;
wire CE_in;
wire I_in;
wire CE_delay;
wire I_delay;
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
// input output assignments
assign #(out_delay) O = O_delay;
assign #(in_delay) CE_delay = CE;
assign #(in_delay) I_delay = I;
assign O_delay = O_out;
assign CE_in = IS_CE_INVERTED_BIN ? ~CE_delay : CE_delay;
assign I_in = IS_I_INVERTED_BIN ? ~I_delay : I_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
always @ (trig_attr) begin
#1;
case (CE_TYPE_REG) // string
"SYNC" : /* */;
"ASYNC" : /* */;
default : begin
$display("Attribute Syntax Error : The attribute CE_TYPE on %s instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
endcase
if ((IS_CE_INVERTED_REG >= 1'b0) && (IS_CE_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin
$display("Attribute Syntax Error : The attribute IS_CE_INVERTED on %s instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((IS_I_INVERTED_REG >= 1'b0) && (IS_I_INVERTED_REG <= 1'b1)) // binary
/* */;
else begin