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Elphel
x393
Commits
49288bf2
Commit
49288bf2
authored
Mar 12, 2015
by
Andrey Filippov
Browse files
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debugging hardware, added re filters for parameters and macros
parent
9326e242
Changes
4
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Side-by-side
Showing
4 changed files
with
58 additions
and
37 deletions
+58
-37
test_mcntrl.py
py393/test_mcntrl.py
+32
-21
verilog_utils.py
py393/verilog_utils.py
+1
-1
x393_mcntrl_tests.py
py393/x393_mcntrl_tests.py
+13
-5
x393_mem.py
py393/x393_mem.py
+12
-10
No files found.
py393/test_mcntrl.py
View file @
49288bf2
...
@@ -351,6 +351,7 @@ USAGE
...
@@ -351,6 +351,7 @@ USAGE
line
=
""
line
=
""
while
True
:
while
True
:
line
=
raw_input
(
'x393
%
s--> '
%
(
''
,
'(simulated)'
)[
args
.
simulated
])
.
strip
()
line
=
raw_input
(
'x393
%
s--> '
%
(
''
,
'(simulated)'
)[
args
.
simulated
])
.
strip
()
lineList
=
line
.
split
()
if
not
line
:
if
not
line
:
print
(
'Use "quit" to exit, "help" - for help'
)
print
(
'Use "quit" to exit, "help" - for help'
)
elif
(
line
==
'quit'
)
or
(
line
==
'exit'
):
elif
(
line
==
'quit'
)
or
(
line
==
'exit'
):
...
@@ -363,8 +364,10 @@ USAGE
...
@@ -363,8 +364,10 @@ USAGE
print
(
'
\n
"parameters" and "defines" list known defined parameters and macros'
)
print
(
'
\n
"parameters" and "defines" list known defined parameters and macros'
)
print
(
"args.exception=
%
d, QUIET=
%
d"
%
(
args
.
exceptions
,
QUIET
))
print
(
"args.exception=
%
d, QUIET=
%
d"
%
(
args
.
exceptions
,
QUIET
))
elif
(
len
(
line
)
>
len
(
"help"
))
and
(
line
[:
len
(
"help"
)]
==
'help'
):
# elif (len(line) > len("help")) and (line[:len("help")]=='help'):
helpFilter
=
line
[
len
(
'help'
):]
.
strip
()
elif
lineList
[
0
]
==
'help'
:
# helpFilter=line[len('help'):].strip()
helpFilter
=
lineList
[
1
]
# should not fail
try
:
try
:
re
.
match
(
helpFilter
,
""
)
re
.
match
(
helpFilter
,
""
)
except
:
except
:
...
@@ -373,11 +376,9 @@ USAGE
...
@@ -373,11 +376,9 @@ USAGE
if
helpFilter
:
if
helpFilter
:
print
print
for
name
,
val
in
sorted
(
callableTasks
.
items
()):
for
name
,
val
in
sorted
(
callableTasks
.
items
()):
# if re.findall(helpFilter,name):
if
re
.
match
(
helpFilter
,
name
):
if
re
.
match
(
helpFilter
,
name
):
print
(
'===
%
s ==='
%
name
)
print
(
'===
%
s ==='
%
name
)
sFuncArgs
=
getFuncArgsString
(
name
)
sFuncArgs
=
getFuncArgsString
(
name
)
# print ("Usage: %s %s"%(name,sFuncArgs))
docs
=
callableTasks
[
name
][
'docs'
]
docs
=
callableTasks
[
name
][
'docs'
]
if
docs
:
if
docs
:
docsl
=
docs
.
split
(
"
\n
"
)
docsl
=
docs
.
split
(
"
\n
"
)
...
@@ -386,29 +387,39 @@ USAGE
...
@@ -386,29 +387,39 @@ USAGE
print
(
'
%
s'
%
l
)
print
(
'
%
s'
%
l
)
#print(docs)
#print(docs)
print
(
" Usage:
%
s
%
s
\n
"
%
(
name
,
sFuncArgs
))
print
(
" Usage:
%
s
%
s
\n
"
%
(
name
,
sFuncArgs
))
elif
line
==
'parameters'
:
elif
lineList
[
0
]
==
'parameters'
:
nameFilter
=
None
if
len
(
lineList
)
>
1
:
nameFilter
=
lineList
[
1
]
try
:
re
.
match
(
nameFilter
,
""
)
except
:
print
(
"Invalid search expression:
%
s"
%
nameFilter
)
nameFilter
=
None
parameters
=
ivp
.
getParameters
()
parameters
=
ivp
.
getParameters
()
for
par
,
val
in
sorted
(
parameters
.
items
()):
for
par
,
val
in
sorted
(
parameters
.
items
()):
if
(
not
nameFilter
)
or
re
.
match
(
nameFilter
,
par
):
try
:
try
:
print
(
par
+
" = "
+
hex
(
val
[
0
])
+
" (type = "
+
val
[
1
]
+
" raw = "
+
val
[
2
]
+
")"
)
print
(
par
+
" = "
+
hex
(
val
[
0
])
+
" (type = "
+
val
[
1
]
+
" raw = "
+
val
[
2
]
+
")"
)
except
:
except
:
print
(
par
+
" = "
+
str
(
val
[
0
])
+
" (type = "
+
val
[
1
]
+
" raw = "
+
val
[
2
]
+
")"
)
print
(
par
+
" = "
+
str
(
val
[
0
])
+
" (type = "
+
val
[
1
]
+
" raw = "
+
val
[
2
]
+
")"
)
if
nameFilter
is
None
:
'''
print
(
" 'parameters' command accepts regular expression as a second parameter to filter the list"
)
for par in parameters:
elif
(
lineList
[
0
]
==
'defines'
)
or
(
lineList
[
0
]
==
'macros'
):
nameFilter
=
None
if
len
(
lineList
)
>
1
:
nameFilter
=
lineList
[
1
]
try
:
try
:
print (par+" = "+hex(parameters[par][0])+" (type = "+parameters[par][1]+" raw = "+parameters[par][2]+")")
re
.
match
(
nameFilter
,
""
)
except
:
except
:
print (par+" = "+str(parameters[par][0])+" (type = "+parameters[par][1]+" raw = "+parameters[par][2]+")")
print
(
"Invalid search expression:
%
s"
%
nameFilter
)
'''
nameFilter
=
None
elif
(
line
==
'defines'
)
or
(
line
==
'macros'
):
defines
=
ivp
.
getDefines
()
defines
=
ivp
.
getDefines
()
for
macro
,
val
in
sorted
(
defines
.
items
()):
for
macro
,
val
in
sorted
(
defines
.
items
()):
if
(
not
nameFilter
)
or
re
.
match
(
nameFilter
,
macro
):
print
(
"`"
+
macro
+
": "
+
str
(
val
))
print
(
"`"
+
macro
+
": "
+
str
(
val
))
if
nameFilter
is
None
:
# for macro in defines:
print
(
" 'defines' command accepts regular expression as a second parameter to filter the list"
)
# print ("`"+macro+": "+defines[macro])
else
:
else
:
cmdLine
=
line
.
split
()
cmdLine
=
line
.
split
()
rslt
=
execTask
(
cmdLine
)
rslt
=
execTask
(
cmdLine
)
...
...
py393/verilog_utils.py
View file @
49288bf2
...
@@ -97,7 +97,7 @@ def getParWidthLo(bitRange):
...
@@ -97,7 +97,7 @@ def getParWidthLo(bitRange):
def
getParWidth
(
bitRange
):
def
getParWidth
(
bitRange
):
wl
=
getParWidthLo
(
bitRange
)
wl
=
getParWidthLo
(
bitRange
)
print
(
"
\n
***wl=
%
s, bitRange=
%
s"
%
(
str
(
wl
),
str
(
bitRange
)))
#
print("\n***wl=%s, bitRange=%s"%(str(wl),str(bitRange)))
# print("bitRange=%s wl=%s"%(bitRange,str(wl)))
# print("bitRange=%s wl=%s"%(bitRange,str(wl)))
if
not
wl
:
if
not
wl
:
return
None
return
None
...
...
py393/x393_mcntrl_tests.py
View file @
49288bf2
...
@@ -41,6 +41,7 @@ from x393_mcntrl_buffers import X393McntrlBuffers
...
@@ -41,6 +41,7 @@ from x393_mcntrl_buffers import X393McntrlBuffers
#from verilog_utils import hx, concat, bits, getParWidth
#from verilog_utils import hx, concat, bits, getParWidth
from
verilog_utils
import
concat
#, getParWidth
from
verilog_utils
import
concat
#, getParWidth
#from x393_axi_control_status import concat, bits
#from x393_axi_control_status import concat, bits
#from time import sleep
class
X393McntrlTests
(
object
):
class
X393McntrlTests
(
object
):
DRY_MODE
=
True
# True
DRY_MODE
=
True
# True
DEBUG_MODE
=
1
DEBUG_MODE
=
1
...
@@ -55,9 +56,9 @@ class X393McntrlTests(object):
...
@@ -55,9 +56,9 @@ class X393McntrlTests(object):
self
.
DRY_MODE
=
dry_mode
self
.
DRY_MODE
=
dry_mode
self
.
x393_mem
=
X393Mem
(
debug_mode
,
dry_mode
)
self
.
x393_mem
=
X393Mem
(
debug_mode
,
dry_mode
)
self
.
x393_axi_tasks
=
X393AxiControlStatus
(
debug_mode
,
dry_mode
)
self
.
x393_axi_tasks
=
X393AxiControlStatus
(
debug_mode
,
dry_mode
)
self
.
x393_pio_sequences
=
X393PIOSequences
(
debug_mode
,
Tru
e
)
self
.
x393_pio_sequences
=
X393PIOSequences
(
debug_mode
,
dry_mod
e
)
self
.
x393_mcntrl_timing
=
X393McntrlTiming
(
debug_mode
,
Tru
e
)
self
.
x393_mcntrl_timing
=
X393McntrlTiming
(
debug_mode
,
dry_mod
e
)
self
.
x393_mcntrl_buffers
=
X393McntrlBuffers
(
debug_mode
,
Tru
e
)
self
.
x393_mcntrl_buffers
=
X393McntrlBuffers
(
debug_mode
,
dry_mod
e
)
self
.
__dict__
.
update
(
VerilogParameters
.
__dict__
[
"_VerilogParameters__shared_state"
])
# Add verilog parameters to the class namespace
self
.
__dict__
.
update
(
VerilogParameters
.
__dict__
[
"_VerilogParameters__shared_state"
])
# Add verilog parameters to the class namespace
try
:
try
:
self
.
verbose
=
self
.
VERBOSE
self
.
verbose
=
self
.
VERBOSE
...
@@ -121,6 +122,7 @@ class X393McntrlTests(object):
...
@@ -121,6 +122,7 @@ class X393McntrlTests(object):
channel 0 buffer data
channel 0 buffer data
I/O delays
I/O delays
clock phase
clock phase
status generation
<set_per_pin_delays> - 1 - set individual (per-pin) I/O delays, 0 - use common for the whole class
<set_per_pin_delays> - 1 - set individual (per-pin) I/O delays, 0 - use common for the whole class
"""
"""
...
@@ -145,7 +147,13 @@ class X393McntrlTests(object):
...
@@ -145,7 +147,13 @@ class X393McntrlTests(object):
self
.
DLY_DM_ODELAY
,
self
.
DLY_DM_ODELAY
,
self
.
DLY_CMDA_ODELAY
)
self
.
DLY_CMDA_ODELAY
)
# set clock phase relative to DDR clk
# set clock phase relative to DDR clk
# print("Debugging: sleeping for 1 second")
# sleep(1)
self
.
x393_mcntrl_timing
.
axi_set_phase
(
self
.
DLY_PHASE
);
self
.
x393_mcntrl_timing
.
axi_set_phase
(
self
.
DLY_PHASE
);
# self.x393_axi_tasks.read_all_status()
#program status for all used modules to refresh at any bit change
self
.
x393_axi_tasks
.
program_status_all
(
3
,
0
)
def
set_all_sequences
(
self
):
def
set_all_sequences
(
self
):
"""
"""
...
...
py393/x393_mem.py
View file @
49288bf2
...
@@ -52,7 +52,7 @@ class X393Mem(object):
...
@@ -52,7 +52,7 @@ class X393Mem(object):
<data> - 32-bit data to write
<data> - 32-bit data to write
"""
"""
if
self
.
DRY_MODE
:
if
self
.
DRY_MODE
:
print
(
"write_mem(0x
%
x,0x
%
x)"
%
(
addr
,
data
))
print
(
"
simulated:
write_mem(0x
%
x,0x
%
x)"
%
(
addr
,
data
))
return
return
with
open
(
"/dev/mem"
,
"r+b"
)
as
f
:
with
open
(
"/dev/mem"
,
"r+b"
)
as
f
:
page_addr
=
addr
&
(
~
(
self
.
PAGE_SIZE
-
1
))
page_addr
=
addr
&
(
~
(
self
.
PAGE_SIZE
-
1
))
...
@@ -65,7 +65,6 @@ class X393Mem(object):
...
@@ -65,7 +65,6 @@ class X393Mem(object):
mm
[
page_offs
:
page_offs
+
4
]
=
packedData
mm
[
page_offs
:
page_offs
+
4
]
=
packedData
if
self
.
DEBUG_MODE
>
2
:
if
self
.
DEBUG_MODE
>
2
:
print
(
"0x
%08
x <== 0x
%08
x (
%
d)"
%
(
addr
,
d
,
d
))
print
(
"0x
%08
x <== 0x
%08
x (
%
d)"
%
(
addr
,
d
,
d
))
mm
.
close
()
'''
'''
if MONITOR_EMIO and VEBOSE:
if MONITOR_EMIO and VEBOSE:
gpio0=read_mem (0xe000a068)
gpio0=read_mem (0xe000a068)
...
@@ -82,7 +81,7 @@ class X393Mem(object):
...
@@ -82,7 +81,7 @@ class X393Mem(object):
<addr> - physical byte address
<addr> - physical byte address
'''
'''
if
self
.
DRY_MODE
:
if
self
.
DRY_MODE
:
print
(
"read_mem(0x
%
x)"
%
(
addr
))
print
(
"
simulated:
read_mem(0x
%
x)"
%
(
addr
))
return
addr
# just some data
return
addr
# just some data
with
open
(
"/dev/mem"
,
"r+b"
)
as
f
:
with
open
(
"/dev/mem"
,
"r+b"
)
as
f
:
page_addr
=
addr
&
(
~
(
self
.
PAGE_SIZE
-
1
))
page_addr
=
addr
&
(
~
(
self
.
PAGE_SIZE
-
1
))
...
@@ -123,7 +122,10 @@ class X393Mem(object):
...
@@ -123,7 +122,10 @@ class X393Mem(object):
for
addr
in
range
(
start_addr
,
end_addr
+
4
,
4
):
for
addr
in
range
(
start_addr
,
end_addr
+
4
,
4
):
if
(
addr
==
start_addr
)
or
((
addr
&
0x3f
)
==
0
):
if
(
addr
==
start_addr
)
or
((
addr
&
0x3f
)
==
0
):
print
(
"
\n
0x
%08
x:"
%
addr
,
end
=
""
),
if
self
.
DRY_MODE
:
print
(
"
\n
simulated: 0x
%08
x:"
%
addr
,
end
=
""
)
else
:
print
(
"
\n
0x
%08
x:"
%
addr
,
end
=
""
)
d
=
rslt
[(
addr
-
start_addr
)
>>
2
]
d
=
rslt
[(
addr
-
start_addr
)
>>
2
]
print
(
"
%08
x "
%
d
,
end
=
""
),
print
(
"
%08
x "
%
d
,
end
=
""
),
print
(
""
)
print
(
""
)
...
...
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