Continue debugging 256-cycle Bayer MCLT

dsp/dtt_iv_8x8_ad.v

@@ -76,6 +76,7 @@ module  dtt_iv_8x8_ad#(
     output reg                       out_we,        //!< output data valid (write to external buffer 
     output reg                       sub16,         //!< Subtract 16 from the full output address when true
     output reg                       inc16,         //!< increment full output address by 16
+    output reg                       start16,       //!< reset/copy page address
     output reg                       start_out);    //!< may start output readout, 1 entry per clock, vertically
 
 // 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
@@ -383,7 +384,8 @@ module  dtt_iv_8x8_ad#(
         sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run;
         inc16 <= out_cntr[3:0] == 'he;
         out_we <= dctv_out_we[1];
-        start_out <= start_out_w;         
+        start_out <= start_out_w;
+        start16 <= dctv_phin [6:0] == 'h11;
     end
     
     always @ (posedge clk) begin

dsp/mclt16x16_bayer.v

@@ -292,7 +292,8 @@ module  mclt16x16_bayer#(
     
     always @(posedge clk) begin
         if      (rst)        dtt_out_ram_cntr <= 0;
-        else if (dtt_inc16)  dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
+        else if (dtt_inc16)  dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; // make it copy input page?
+        
         dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
         
         dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
@@ -368,8 +369,6 @@ module  mclt16x16_bayer#(
         .data_in  ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] 
     );
    
-    
-    
     dtt_iv_8x8_ad #(
         .INPUT_WIDTH     (DTT_IN_WIDTH),
         .OUT_WIDTH       (OUT_WIDTH),
@@ -393,7 +392,8 @@ module  mclt16x16_bayer#(
         .out_wa         (dtt_out_wa16),     // output[3:0] reg 
         .out_we         (dtt_out_we),       // output reg 
         .sub16          (dtt_sub16),        // output reg 
-        .inc16          (dtt_inc16),        // output reg 
+        .inc16          (dtt_inc16),        // output reg
+        .start16        (),                 // output reg 
         .start_out      (dtt_start_fill)    // output[24:0] signed
     );
     //[DTT_IN_WIDTH-1:0

dsp/mclt_baeyer_fold_accum_rgb.v

@@ -108,7 +108,8 @@ module  mclt_baeyer_fold_accum_rgb # (
     reg  [1:0] ced2;
     wire neg_m1, neg_m2, en_a2;
     wire accum1= !var_pre2_first;
-    wire accum2= !var_pre_first && green_r[2];
+//    wire accum2= !var_pre_first && green_r[2];
+    wire accum2= !var_pre_first && green_r[3];
     wire [DSP_P_WIDTH-1:0] pout1;
     wire [DSP_P_WIDTH-1:0] pout2;
     wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ?
@@ -205,7 +206,8 @@ module  mclt_baeyer_fold_accum_rgb # (
         .rst  (rst),           // input
         .dly  (4'h1),          // input[3:0] 
 //        .din  (pix_sgn[1]),    // input[0:0] 
-        .din  (green_r[0]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 
+//        .din  (green_r[0]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 
+        .din  (green_r[1]? pix_sgn[1]:pix_sgn[0]),    // input[0:0] 
         .dout (neg_m2)         // output[0:0] 
     );
 

dsp/phase_rotator_rgb.v

+/*!
+ * <b>Module:</b> phase_rotator_rgb
+ * @file phase_rotator_rgb.v
+ * @date 2017-12-11  
+ * @author eyesis
+ *     
+ * @brief 2-d phase rotator in frequency domain (subpixel shift)
+ *
+ * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ *
+ * <b>License </b>
+ *
+ * phase_rotator_rgb.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * phase_rotator_rgb.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+
+module  phase_rotator_rgb#(
+    parameter FD_WIDTH =        25, // input/output data width, signed
+    parameter SHIFT_WIDTH =      7, // x/y subpixel shift, signed -0.5<=shift<0.5
+    parameter DSP_B_WIDTH =     18, // signed, output from sin/cos ROM
+    parameter DSP_A_WIDTH =     25,
+    parameter DSP_P_WIDTH =     48,
+    parameter COEFF_WIDTH =     17, // = DSP_B_WIDTH - 1 or positive numbers,
+    parameter GREEN       =      1, // 0: use 1 DTT block (R,B), 1: use two DTT blocks (G) 
+    parameter START_DELAY =     128 // delay start of input memory readout 
+)(
+    input                            clk,           //!< system clock, posedge
+    input                            rst,           //!< sync reset
+    input                            start,         //!< start of delay
+    input                            wpage,         //!< page (64 for R,B, 128 for G) last being written (may need delay?)
+    input signed   [SHIFT_WIDTH-1:0] shift_h,       //!< subpixel shift horizontal
+    input signed   [SHIFT_WIDTH-1:0] shift_v,       //!< subpixel shift vertical
+    input                            inv_checker,   //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
+    input                            inv_rows,      //!< 0 : use first row, 1 - second row (when GREEN=0) 
+    // input data CC,CS,SC,SS in column scan order (matching DTT)
+    output             [GREEN + 6:0] in_addr,       //!< input buffer address
+    output                     [1:0] in_re,         //!< input buffer re/regen      
+    input signed      [FD_WIDTH-1:0] fd_din,        //!< frequency domain data in, LATENCY=3 from start
+    output signed     [FD_WIDTH-1:0] fd_out,        //!< frequency domain data in
+    output                           pre_first_out, //!< 1 cycle before output data valid 
+    output reg                       pre_last_out,  //!< 2 cycle before last data valid 
+    output                           fd_dv,         //!< output data valid
+    output                     [8:0] fd_wa          // output address including page
+);
+
+    reg signed   [SHIFT_WIDTH-1:0] shift_h_r;
+    reg signed   [SHIFT_WIDTH-1:0] shift_v_r;
+    reg                            inv_checker_r;
+    reg                            inv_rows_r;
+    reg                            wpage_r;
+    wire                           negate = inv_checker_r ^ inv_rows_r; // FIXME: put real
+    reg                      [1:0] dtt_start_out;
+    reg                      [7:0] dtt_dly_cntr;
+    reg                      [4:0] dtt_rd_regen_dv;
+    reg                      [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
+    reg                      [7:0] in_addr_r;       //!< input buffer address
+    reg                      [8:0] out_addr_r;
+    assign  in_addr = in_addr_r[GREEN + 6:0];
+    assign  in_re = dtt_rd_regen_dv[2:1];
+    assign  fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
+    
+    always @ (posedge clk) begin
+        if (start) begin
+            shift_h_r <=     shift_h;
+            shift_v_r <=     shift_v;
+            inv_checker_r <= inv_checker;
+            inv_rows_r <=    inv_rows;
+            wpage_r <=       wpage;
+        end
+        
+
+        if      (rst)                   dtt_dly_cntr <= 0;
+        else if (start)                 dtt_dly_cntr <= START_DELAY;
+        else if (|dtt_dly_cntr)         dtt_dly_cntr <= dtt_dly_cntr - 1;
+        
+        dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0};
+        
+        if      (rst)                   dtt_rd_regen_dv[0] <= 0;
+        else if (dtt_start_out[0])      dtt_rd_regen_dv[0] <= 1;
+        else if (&dtt_rd_cntr_pre[7:0]) dtt_rd_regen_dv[0] <= 0;
+        
+        if      (rst)                   dtt_rd_regen_dv[3:1] <= 0;
+        else                            dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
+        
+        if (dtt_start_out[0])           dtt_rd_cntr_pre <= {wpage_r, 8'b0}; //copy page number
+        else if (dtt_rd_regen_dv[0])    dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
+        
+        if (GREEN) in_addr_r <= {dtt_rd_cntr_pre[8],
+                                 dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
+                                 dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : dtt_rd_cntr_pre[7:2]};
+        else       in_addr_r <= {1'b0, 
+                                 dtt_rd_cntr_pre[8],
+//                               dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
+                                 dtt_rd_cntr_pre[1] ?
+                                 (dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : {~dtt_rd_cntr_pre[7:5],dtt_rd_cntr_pre[4:2]}):
+                                 (dtt_rd_cntr_pre[0] ? {dtt_rd_cntr_pre[7:5],~dtt_rd_cntr_pre[4:2]} : dtt_rd_cntr_pre[7:2])};
+
+        if (pre_first_out) out_addr_r <= {wpage_r,8'b0};
+        else if (fd_dv)    out_addr_r <= out_addr_r + 1;
+        
+        pre_last_out <=  out_addr_r[7:0] == 8'hfe;
+        
+    end
+
+    phase_rotator #(
+        .FD_WIDTH   (FD_WIDTH),
+        .SHIFT_WIDTH(SHIFT_WIDTH), // should be exactly 7
+        .DSP_B_WIDTH(DSP_B_WIDTH),
+        .DSP_A_WIDTH(DSP_A_WIDTH),
+        .DSP_P_WIDTH(DSP_P_WIDTH),
+        .COEFF_WIDTH(COEFF_WIDTH),
+        .DECIMATE   (1'b0),
+        .ODD        (1'b0)
+    ) phase_rotator0_i (
+        .clk           (clk),            // input
+        .rst           (rst),            // input
+        .start         (dtt_start_out[1]), // input
+        // are these shift OK? Will need to be valis only @ dtt_start_out
+        .shift_h       (shift_h_r),      // input[6:0] signed 
+        .shift_v       (shift_v_r),      // input[6:0] signed
+        .inv_checker   (negate),         // input only used for Bayer mosaic data 
+        .fd_din        (fd_din),         // input[24:0] signed. Expected latency = 3 from start  
+        .fd_out        (fd_out),         // output[24:0] reg signed 
+        .pre_first_out (pre_first_out),  // output reg 
+        .fd_dv         (fd_dv)           // output reg 
+    );
+
+    
+endmodule

mclt_test_04.sav

 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Thu Dec 28 00:31:10 2017
+[*] Thu Dec 28 22:34:50 2017
 [*]
 [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226220814551.fst"
 [dumpfile_mtime] "Wed Dec 27 05:08:17 2017"
 [dumpfile_size] 843036
 [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav"
 [timestart] 0
-[size] 1824 1171
-[pos] 0 0
-*-21.266958 10681000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 1920 1171
+[pos] -1920 0
+*-21.266958 1585000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] mclt_test_04.
 [treeopen] mclt_test_04.mclt16x16_bayer_i.
 [treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.
@@ -299,7 +299,7 @@ mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
 @20000
 -
 -
-@8022
+@8023
 mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
 @20000
 -
@@ -367,6 +367,8 @@ mclt_test_04.mclt16x16_bayer_i.window_w[17:0]
 mclt_test_04.mclt16x16_bayer_i.start
 @800200
 -fold
+@28
+mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.start
 @22
 mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
 @c00022
@@ -576,7 +578,6 @@ mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0
 mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0]
 mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0]
 mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0]
-@23
 mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0]
 @200
 -