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Commit 39faa79b authored by Andrey Filippov's avatar Andrey Filippov
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debugging by comparing with Java generated data

parent f1b486b4
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Showing with 257 additions and 133 deletions
dsp/create_wnd_mul_rom.py
View file @ 39faa79b
......@@ -98,15 +98,24 @@ def print_params(data,
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def create_wnd_1d (N=1024, bits=18): # N=32, bits=18, all data is positive
rom = []
sin = []
for i in range(N):
rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count
return rom
def create_wnd_1d (N=1024, bits=17): # N=32, bits=18, all data is positive
rom = [0.0]*N
scale = (1 << bits) - 1 # loosing 1 count
# sin = []
for i in range(1,N+1):
rom[i % N]=int(round(math.sin(math.pi*i/(2*N))* scale)) # loosing 1 count
# rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count
print_rom(rom)
return rom
def print_rom(rom):
for i,d in enumerate(rom):
print("%5x "%(d),end="")
if (i % 16) == 15:
print()
print_params(
create_with_parity(create_wnd_1d (N=1024, bits=18), 18, False),
create_with_parity(create_wnd_1d (N=1024, bits=17), 18, False),
os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),
"// MCLT 1d 16 count window with 128:1 super resolution data")
print ("MCLT 1d 16 count window with 128:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))
......
dsp/mclt16x16.v
View file @ 39faa79b
......@@ -152,12 +152,14 @@ module mclt16x16#(
y_shft_r <= y_shft;
bayer_r <= bayer;
end
if (in_busy[2]) begin // same latency as mpix_a_w
// if (in_busy[2]) begin // same latency as mpix_a_w
if (in_busy[1]) begin // same latency as mpix_a_w
x_shft_r2 <= x_shft_r;
y_shft_r2 <= y_shft_r;
end
if (in_busy[2]) bayer_d <= bayer_r;
/// if (in_busy[2]) bayer_d <= bayer_r;
if (in_busy[1]) bayer_d <= bayer_r;
if (rst) in_busy <= 0;
else in_busy <= {in_busy[15:0], start | (in_busy[0] & ~(&in_cntr))};
......@@ -251,8 +253,10 @@ D11 - negate for mode 3 (SS)
.clk_a (clk), // input
.addr_a ({2'b0,in_cntr[1:0],in_cntr[7:2]}), // input[9:0]
.en_a (in_busy[1]), // input
.regen_a (in_busy[2]), // input
/// .en_a (in_busy[1]), // input
/// .regen_a (in_busy[2]), // input
.en_a (in_busy[0]), // input
.regen_a (in_busy[1]), // input
.we_a (1'b0), // input
.data_out_a(fold_rom_out), // output[17:0]
.data_in_a (18'b0), // input[17:0]
......@@ -273,7 +277,8 @@ D11 - negate for mode 3 (SS)
.OUT_WIDTH (WND_WIDTH)
) mclt_wnd_i (
.clk (clk), // input
.en (in_busy[3]), // input
// .en (in_busy[3]), // input
.en (in_busy[2]), // input
.x_in (mpix_a_w[3:0]), // input[3:0]
.y_in (mpix_a_w[7:4]), // input[3:0]
.x_shft (x_shft_r2), // input[7:0]
......
dsp/mclt_full_shift.v
View file @ 39faa79b
......@@ -6,7 +6,7 @@
*
* @brief 1d index for window with fractional shift
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* @copyright Copyright (c) 2017
*
* <b>License </b>
*
......@@ -39,8 +39,8 @@
`timescale 1ns/1ps
module mclt_full_shift#(
parameter COORD_WIDTH = 5, //
parameter SHIFT_WIDTH = 3 // bits in shift
parameter COORD_WIDTH = 10, //
parameter SHIFT_WIDTH = 7 // bits in shift
)(
input clk, //!< system clock, posedge
......@@ -49,12 +49,18 @@ module mclt_full_shift#(
output reg [COORD_WIDTH-1:0] coord_out, //!< pixel coordinate in window ROM (latency 2)
output reg zero //!< window is zero (on or out of the boundary) (latency 2)
);
wire [COORD_WIDTH+1:0] mod_coord_w = {1'b0, coord,1'b0, {(COORD_WIDTH-4){1'b1}}} - {{(COORD_WIDTH-SHIFT_WIDTH + 2){shift[SHIFT_WIDTH-1]}}, shift};
// wire [COORD_WIDTH+1:0] mod_coord_w = {1'b0, coord,1'b0, {(COORD_WIDTH-4){1'b1}}} - {{(COORD_WIDTH-SHIFT_WIDTH + 2){shift[SHIFT_WIDTH-1]}}, shift};
wire [5:0] shift_high_w = {{(COORD_WIDTH-SHIFT_WIDTH+2){shift[SHIFT_WIDTH-1]}} , shift[SHIFT_WIDTH-1:COORD_WIDTH-4]};
wire [5:0] coord_high_w = {1'b0,coord,1'b1} + shift_high_w;
wire [COORD_WIDTH+1:0] mod_coord_w = {coord_high_w,shift[COORD_WIDTH-5:0]};
reg [COORD_WIDTH+1:0] mod_coord_r;
always @ (posedge clk) begin
coord_out <= mod_coord_r[COORD_WIDTH] ? ~mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
// coord_out <= mod_coord_r[COORD_WIDTH] ? ~mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
coord_out <= mod_coord_r[COORD_WIDTH] ? -mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
mod_coord_r <= mod_coord_w;
zero <= mod_coord_r[COORD_WIDTH + 1];
zero <= mod_coord_r[COORD_WIDTH + 1] || (mod_coord_r == 0);
end
endmodule
......
dsp/mclt_test_01.tf
View file @ 39faa79b
......@@ -87,15 +87,29 @@ module mclt_test_01 ();
reg [SHIFT_WIDTH-1 : 0] shifts_x[0:3];
reg [SHIFT_WIDTH-1 : 0] shifts_y[0:3];
reg [3 : 0] bayer[0:3];
reg [3:0] java_wnd_signs[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [7:0] java_fold_index[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [WND_WIDTH - 1:0] java_tiles_wnd[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
reg [WND_WIDTH - 1:0] tiles_wnd[0:1023];
integer i, n, n_out;
initial begin
$readmemh("input_data/tile_01.dat",tile_shift);
$readmemh("input_data/clt_wnd_signs.dat", java_wnd_signs);
$readmemh("input_data/clt_fold_index.dat", java_fold_index);
// $readmemh("input_data/tile_01.dat",tile_shift);
$readmemh("input_data/tile_00_2_x1489_y951.dat",tile_shift);
shifts_x[0] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[0] = tile_shift[1][SHIFT_WIDTH-1:0];
bayer[0] = tile_shift[2][3:0];
for (i=0; i<256; i=i+1) begin
tiles['h000 + i] = tile_shift[i+3];
end
$readmemh("input_data/clt_wnd_00_2_x1489_y951.dat",java_tiles_wnd);
for (i=0; i<256; i=i+1) begin
tiles_wnd['h000 + i] = java_tiles_wnd[i];
end
$readmemh("input_data/tile_02.dat",tile_shift);
shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
shifts_y[1] = tile_shift[1][SHIFT_WIDTH-1:0];
......@@ -214,6 +228,41 @@ module mclt_test_01 ();
end
integer n1, cntr1, diff1;
wire [7:0] mpix_a_w = mclt16x16_i.mpix_a_w;
wire [7:0] java_fi_w = java_fold_index[cntr1];
initial begin
while (RST) @(negedge CLK);
for (n1 = 0; n1 < 4; n1 = n1+1) begin
while (mclt16x16_i.in_cntr != 2) begin
@(negedge CLK);
end
for (cntr1 = 0; cntr1 < 256; cntr1 = cntr1 + 1) begin
diff1 = mpix_a_w - java_fi_w; // java_fold_index[cntr1];
@(negedge CLK);
end
end
end
integer n2, cntr2, diff2, diff2a;
wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r;
// reg [7:0] java_fi_r;
wire [WND_WIDTH-1:0] java_window_w = java_tiles_wnd[cntr2]; // tiles_wnd[n2 * 256 + cntr2];
initial begin
while (RST) @(negedge CLK);
for (n2 = 0; n2 < 4; n2 = n2+1) begin
while (mclt16x16_i.in_cntr != 9) begin
@(negedge CLK);
end
for (cntr2 = 0; cntr2 < 256; cntr2 = cntr2 + 1) begin
diff2 = window_r - java_window_w;
if (n2 < 1) diff2a = window_r - java_window_w; // TEMPORARY, while no other data
@(negedge CLK);
end
end
end
mclt16x16 #(
.SHIFT_WIDTH (SHIFT_WIDTH),
......
dsp/mclt_wnd_mul.v
View file @ 39faa79b
......@@ -39,33 +39,39 @@
`timescale 1ns/1ps
// Latency = 5
module mclt_wnd_mul#(
parameter SHIFT_WIDTH = 8, // bits in shift (1 bit - integer, 7 bits - fractional
parameter SHIFT_WIDTH = 7, // bits in shift (0 bits - integer, 7 bits - fractional
parameter COORD_WIDTH = 10, // bits in full coordinate 10 for 18K RAM
parameter OUT_WIDTH = 18 // bits in window value (positive)
)(
input clk, //!< system clock, posedge
input en, //!< re (both re and ren - just for power)
input [3:0] x_in, //!< tile pixel X
input [3:0] y_in, //!< tile pixel Y
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y
output [OUT_WIDTH - 1 : 0] wnd_out
input clk, //!< system clock, posedge
input en, //!< re (both re and ren - just for power)
input [3:0] x_in, //!< tile pixel X
input [3:0] y_in, //!< tile pixel Y
input [SHIFT_WIDTH-1:0] x_shft, //!< tile pixel X
input [SHIFT_WIDTH-1:0] y_shft, //!< tile pixel Y
output signed [OUT_WIDTH - 1 : 0] wnd_out
);
wire [COORD_WIDTH - 1 : 0] x_full;
wire [COORD_WIDTH - 1 : 0] y_full;
wire x_zero;
wire y_zero;
reg [1:0] zero; // x_zero | y_zero;
reg [2:0] regen; //
wire [OUT_WIDTH - 1 : 0] wnd_out_x;
wire [OUT_WIDTH - 1 : 0] wnd_out_y;
reg [2*OUT_WIDTH - 1 : 0] wnd_out_r;
assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 1: OUT_WIDTH];
wire [COORD_WIDTH - 1 : 0] x_full;
wire [COORD_WIDTH - 1 : 0] y_full;
wire x_zero;
wire y_zero;
// reg [1:0] zero; // x_zero | y_zero;
reg zero; // x_zero | y_zero;
reg [2:0] regen; //
wire signed [OUT_WIDTH - 1 : 0] wnd_out_x; // should be all positive
wire signed [OUT_WIDTH - 1 : 0] wnd_out_y; // should be all positive
reg signed [OUT_WIDTH - 1 : 0] wnd_out_x_r; // to be absorbed in DSP
reg signed [OUT_WIDTH - 1 : 0] wnd_out_y_r; // to be absorbed in DSP
reg signed [2*OUT_WIDTH - 1 : 0] wnd_out_r; // should be all positive
assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 2: OUT_WIDTH-1];
always @ (posedge clk) begin
regen <= {regen[1:0],en};
zero <= {1'b0, x_zero | y_zero};
wnd_out_r <= wnd_out_x * wnd_out_y;
wnd_out_x_r <= wnd_out_x;
wnd_out_y_r <= wnd_out_y;
// zero <= {zero[0], x_zero | y_zero};
zero <= x_zero | y_zero;
wnd_out_r <= wnd_out_x_r * wnd_out_y_r;
end
mclt_full_shift #(
......@@ -106,7 +112,7 @@ module mclt_wnd_mul#(
.regen_a (regen[2]), // input
.we_a (1'b0), // input
.rrst_a (1'b0), // input
.regrst_a (zero[1]), // input
.regrst_a (zero), // input
.data_out_a(wnd_out_x), // output[17:0]
.data_in_a (18'b0), // input[17:0]
.clk_b (clk), // input
......@@ -115,7 +121,7 @@ module mclt_wnd_mul#(
.regen_b (regen[2]), // input
.we_b (1'b0), // input
.rrst_b (1'b0), // input
.regrst_b (zero[1]), // input
.regrst_b (zero), // input
.data_out_b(wnd_out_y), // output[17:0]
.data_in_b (18'b0) // input[17:0]
);
......
includes/mclt_wnd_mul.vh
View file @ 39faa79b
This diff is collapsed.
mclt_test_01.sav
View file @ 39faa79b
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Dec 14 06:19:18 2017
[*] Sat Dec 16 19:54:45 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171213195034071.fst"
[dumpfile_mtime] "Thu Dec 14 02:50:36 2017"
[dumpfile_size] 935652
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171215180909701.fst"
[dumpfile_mtime] "Sat Dec 16 01:09:12 2017"
[dumpfile_size] 940154
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
[timestart] 365600
[size] 1920 1171
[pos] -1921 -1
*-15.459125 415000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 394400
[size] 1814 1171
[pos] -1 -1
*-15.197140 538600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_01.
[treeopen] mclt_test_01.mclt16x16_i.
[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.
[sst_width] 242
[signals_width] 275
[signals_width] 251
[sst_expanded] 1
[sst_vpaned_height] 344
@800200
......@@ -45,11 +46,29 @@ mclt_test_01.dv
mclt_test_01.dout[24:0]
@28
mclt_test_01.pre_last_out
@420
mclt_test_01.n1
mclt_test_01.cntr1
@22
mclt_test_01.java_fi_w[7:0]
@420
[color] 2
mclt_test_01.diff1
mclt_test_01.n2
mclt_test_01.cntr2
@22
mclt_test_01.window_r[17:0]
mclt_test_01.java_window_w[17:0]
@420
mclt_test_01.diff2
mclt_test_01.diff2a
@8420
mclt_test_01.diff2a
@1000200
-top
@800200
-mclt16x16
@800022
@c00022
mclt_test_01.mclt16x16_i.in_busy[16:0]
@28
(0)mclt_test_01.mclt16x16_i.in_busy[16:0]
......@@ -69,7 +88,7 @@ mclt_test_01.mclt16x16_i.in_busy[16:0]
(14)mclt_test_01.mclt16x16_i.in_busy[16:0]
(15)mclt_test_01.mclt16x16_i.in_busy[16:0]
(16)mclt_test_01.mclt16x16_i.in_busy[16:0]
@1001200
@1401200
-group_end
@22
mclt_test_01.mclt16x16_i.in_cntr[7:0]
......@@ -84,7 +103,6 @@ mclt_test_01.mclt16x16_i.mpixel_a[7:0]
mclt_test_01.mclt16x16_i.mpixel_d[15:0]
mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]
mclt_test_01.mclt16x16_i.pix_wnd_r[33:0]
@23
mclt_test_01.mclt16x16_i.pix_wnd_r2[24:0]
@28
mclt_test_01.mclt16x16_i.mpix_use_d
......@@ -115,25 +133,31 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0]
-
@1401200
-fold_rom
@c00200
@800200
-mclt_wnd_mul
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.en
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_shft[6:0]
@8022
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_in[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.x_zero
@8022
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_full[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.y_zero
mclt_test_01.mclt16x16_i.mclt_wnd_i.zero
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@c08022
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
@1401200
-group_end
@c00022
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@28
(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
......@@ -156,11 +180,36 @@ mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
(17)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@1401200
-group_end
@8022
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out[17:0]
@c00200
-wnd_rom
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.addr_a[9:0]
@28
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regrst_a
@200
-
@1401200
-wnd_rom
@c00200
-mclt_full_shift_x
@22
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord[3:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.shift[6:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_w[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_r[11:0]
mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0]
@200
-
@1401200
-mclt_full_shift_x
@1000200
-mclt_wnd_mul
@c08022
@c08023
mclt_test_01.mclt16x16_i.window_r[17:0]
@28
(0)mclt_test_01.mclt16x16_i.window_r[17:0]
......@@ -181,7 +230,7 @@ mclt_test_01.mclt16x16_i.window_r[17:0]
(15)mclt_test_01.mclt16x16_i.window_r[17:0]
(16)mclt_test_01.mclt16x16_i.window_r[17:0]
(17)mclt_test_01.mclt16x16_i.window_r[17:0]
@1401200
@1401201
-group_end
@8022
mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]
......
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