debugging by comparing with Java generated data

39faa79b · Andrey Filippov · f1b486b4 · 39faa79b · 39faa79b · 39faa79b
Commit 39faa79b authored Dec 16, 2017 by Andrey Filippov
7 changed files
--- a/dsp/create_wnd_mul_rom.py
+++ b/dsp/create_wnd_mul_rom.py
@@ -98,15 +98,24 @@ def print_params(data,
            if v:
                print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
                        
-def create_wnd_1d (N=1024, bits=18): # N=32, bits=18, all data is positive
-    rom = []
-    sin = []
-    for i in range(N):
-        rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count
-    return rom                        
+def create_wnd_1d (N=1024, bits=17): # N=32, bits=18, all data is positive
+    rom = [0.0]*N
+    scale = (1 << bits) - 1  # loosing 1 count
+#    sin = []
+    for i in range(1,N+1):
+        rom[i % N]=int(round(math.sin(math.pi*i/(2*N))* scale)) # loosing 1 count
+#        rom.append(int(round(math.sin(math.pi*(i+1)/(2*N))* ((1 << bits) - 1)))) # loosing 1 count
+    print_rom(rom)  
+    return rom
+                        
+def print_rom(rom):
+    for i,d in enumerate(rom):
+        print("%5x "%(d),end="")
+        if (i % 16) == 15:
+            print()
                        
 print_params(
-    create_with_parity(create_wnd_1d (N=1024, bits=18), 18, False),
+    create_with_parity(create_wnd_1d (N=1024, bits=17), 18, False),
    os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path)),
    "// MCLT 1d 16 count window with 128:1 super resolution data")
 print ("MCLT 1d 16 count window with 128:1 super resolution data is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), mclt_wnd_rom_path))))

--- a/dsp/mclt16x16.v
+++ b/dsp/mclt16x16.v
@@ -152,12 +152,14 @@ module  mclt16x16#(
            y_shft_r <= y_shft;
            bayer_r <= bayer;
        end
-        if (in_busy[2]) begin      // same latency as mpix_a_w
+//        if (in_busy[2]) begin      // same latency as mpix_a_w
+        if (in_busy[1]) begin      // same latency as mpix_a_w
            x_shft_r2 <= x_shft_r;
            y_shft_r2 <= y_shft_r;
        end
        
-        if (in_busy[2]) bayer_d <= bayer_r; 
+///        if (in_busy[2]) bayer_d <= bayer_r; 
+        if (in_busy[1]) bayer_d <= bayer_r; 
        
        if      (rst)      in_busy <= 0;
        else               in_busy <= {in_busy[15:0], start | (in_busy[0] & ~(&in_cntr))};
@@ -251,8 +253,10 @@ D11 - negate for mode 3 (SS)
    
        .clk_a     (clk),       // input
        .addr_a    ({2'b0,in_cntr[1:0],in_cntr[7:2]}),    // input[9:0] 
-        .en_a      (in_busy[1]),   // input
-        .regen_a   (in_busy[2]),   // input
+///        .en_a      (in_busy[1]),   // input
+///        .regen_a   (in_busy[2]),   // input
+        .en_a      (in_busy[0]),   // input
+        .regen_a   (in_busy[1]),   // input
        .we_a      (1'b0),         // input
        .data_out_a(fold_rom_out), // output[17:0] 
        .data_in_a (18'b0),        // input[17:0]
@@ -273,7 +277,8 @@ D11 - negate for mode 3 (SS)
        .OUT_WIDTH   (WND_WIDTH)
    ) mclt_wnd_i (
        .clk       (clk), // input
-        .en        (in_busy[3]), // input
+//        .en        (in_busy[3]), // input
+        .en        (in_busy[2]), // input
        .x_in      (mpix_a_w[3:0]), // input[3:0] 
        .y_in      (mpix_a_w[7:4]), // input[3:0] 
        .x_shft    (x_shft_r2),     // input[7:0] 

--- a/dsp/mclt_full_shift.v
+++ b/dsp/mclt_full_shift.v
@@ -6,7 +6,7 @@
 *     
 * @brief 1d index for window with fractional shift
 *
- * @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * @copyright Copyright (c) 2017
 *
 * <b>License </b>
 *
@@ -39,8 +39,8 @@
 `timescale 1ns/1ps

 module  mclt_full_shift#(
-    parameter COORD_WIDTH =     5,  //
-    parameter SHIFT_WIDTH =     3   // bits in shift  
+    parameter COORD_WIDTH =     10,  //
+    parameter SHIFT_WIDTH =      7   // bits in shift  
    
    )(
    input                          clk,           //!< system clock, posedge
@@ -49,12 +49,18 @@ module  mclt_full_shift#(
    output reg   [COORD_WIDTH-1:0] coord_out,     //!< pixel coordinate in window ROM (latency 2)
    output reg                     zero           //!< window is zero (on or out of the boundary)  (latency 2)     
 );
-    wire [COORD_WIDTH+1:0] mod_coord_w = {1'b0, coord,1'b0, {(COORD_WIDTH-4){1'b1}}} - {{(COORD_WIDTH-SHIFT_WIDTH + 2){shift[SHIFT_WIDTH-1]}}, shift};
+//    wire [COORD_WIDTH+1:0] mod_coord_w = {1'b0, coord,1'b0, {(COORD_WIDTH-4){1'b1}}} - {{(COORD_WIDTH-SHIFT_WIDTH + 2){shift[SHIFT_WIDTH-1]}}, shift};
+    wire             [5:0] shift_high_w = {{(COORD_WIDTH-SHIFT_WIDTH+2){shift[SHIFT_WIDTH-1]}} , shift[SHIFT_WIDTH-1:COORD_WIDTH-4]};
+    wire             [5:0] coord_high_w = {1'b0,coord,1'b1} + shift_high_w;
+    
+    wire [COORD_WIDTH+1:0] mod_coord_w = {coord_high_w,shift[COORD_WIDTH-5:0]};
+    
    reg [COORD_WIDTH+1:0] mod_coord_r;
    always @ (posedge clk) begin
-    coord_out <= mod_coord_r[COORD_WIDTH] ? ~mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
+//        coord_out <= mod_coord_r[COORD_WIDTH] ? ~mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
+        coord_out <= mod_coord_r[COORD_WIDTH] ? -mod_coord_r[COORD_WIDTH-1:0] : mod_coord_r[COORD_WIDTH-1:0];
        mod_coord_r <= mod_coord_w;
-        zero <= mod_coord_r[COORD_WIDTH + 1];
+        zero <= mod_coord_r[COORD_WIDTH + 1] || (mod_coord_r == 0);
    end 

 endmodule

--- a/dsp/mclt_test_01.tf
+++ b/dsp/mclt_test_01.tf
@@ -87,15 +87,29 @@ module  mclt_test_01 ();
    reg   [SHIFT_WIDTH-1 : 0]   shifts_x[0:3]; 
    reg   [SHIFT_WIDTH-1 : 0]   shifts_y[0:3]; 
    reg               [3 : 0]   bayer[0:3]; 
+    
+    reg                 [3:0]   java_wnd_signs[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg                 [7:0]   java_fold_index[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg     [WND_WIDTH - 1:0]   java_tiles_wnd[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
+    reg     [WND_WIDTH - 1:0]   tiles_wnd[0:1023];
    integer   i, n, n_out;
    initial begin
-        $readmemh("input_data/tile_01.dat",tile_shift);
+        $readmemh("input_data/clt_wnd_signs.dat",  java_wnd_signs);
+        $readmemh("input_data/clt_fold_index.dat", java_fold_index);
+    
+//        $readmemh("input_data/tile_01.dat",tile_shift);
+        $readmemh("input_data/tile_00_2_x1489_y951.dat",tile_shift);
        shifts_x[0] = tile_shift[0][SHIFT_WIDTH-1:0];
        shifts_y[0] = tile_shift[1][SHIFT_WIDTH-1:0];
        bayer[0] =    tile_shift[2][3:0];
        for (i=0; i<256; i=i+1) begin
            tiles['h000 + i] = tile_shift[i+3]; 
        end
+        $readmemh("input_data/clt_wnd_00_2_x1489_y951.dat",java_tiles_wnd);
+        for (i=0; i<256; i=i+1) begin
+            tiles_wnd['h000 + i] = java_tiles_wnd[i]; 
+        end
+        
        $readmemh("input_data/tile_02.dat",tile_shift);
        shifts_x[1] = tile_shift[0][SHIFT_WIDTH-1:0];
        shifts_y[1] = tile_shift[1][SHIFT_WIDTH-1:0];
@@ -214,6 +228,41 @@ module  mclt_test_01 ();
    
    end

+    integer n1, cntr1, diff1;
+    wire           [7:0] mpix_a_w = mclt16x16_i.mpix_a_w;
+    wire           [7:0] java_fi_w = java_fold_index[cntr1];  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n1 = 0; n1 < 4; n1 = n1+1) begin
+            while (mclt16x16_i.in_cntr != 2) begin
+                @(negedge CLK);
+            end
+            for (cntr1 = 0; cntr1 < 256; cntr1 = cntr1 + 1) begin
+                diff1 = mpix_a_w - java_fi_w; // java_fold_index[cntr1];
+                @(negedge CLK);
+            end
+        end
+    end
+
+    integer n2, cntr2, diff2, diff2a;
+    wire [WND_WIDTH-1:0] window_r = mclt16x16_i.window_r;
+//    reg            [7:0] java_fi_r;  
+    wire [WND_WIDTH-1:0] java_window_w = java_tiles_wnd[cntr2]; // tiles_wnd[n2 * 256 + cntr2];  
+    initial begin
+        while (RST) @(negedge CLK);
+        for (n2 = 0; n2 < 4; n2 = n2+1) begin
+            while (mclt16x16_i.in_cntr != 9) begin
+                @(negedge CLK);
+            end
+            for (cntr2 = 0; cntr2 < 256; cntr2 = cntr2 + 1) begin
+                diff2 = window_r - java_window_w;
+                if (n2 < 1) diff2a = window_r - java_window_w; // TEMPORARY, while no other data
+                @(negedge CLK);
+            end
+        end
+    end
+
+
    
    mclt16x16 #(
        .SHIFT_WIDTH     (SHIFT_WIDTH),

--- a/dsp/mclt_wnd_mul.v
+++ b/dsp/mclt_wnd_mul.v
@@ -39,33 +39,39 @@
 `timescale 1ns/1ps
 // Latency = 5
 module  mclt_wnd_mul#(
-    parameter SHIFT_WIDTH =  8,  // bits in shift (1 bit - integer, 7 bits - fractional
+    parameter SHIFT_WIDTH =  7,  // bits in shift (0 bits - integer, 7 bits - fractional
    parameter COORD_WIDTH = 10,  // bits in full coordinate 10 for 18K RAM 
    parameter OUT_WIDTH =   18   // bits in window value (positive) 
 )(
-    input                          clk,   //!< system clock, posedge
-    input                          en,    //!< re (both re and ren - just for power)
-    input                    [3:0] x_in,  //!< tile pixel X
-    input                    [3:0] y_in,  //!< tile pixel Y
-    input        [SHIFT_WIDTH-1:0] x_shft,  //!< tile pixel X
-    input        [SHIFT_WIDTH-1:0] y_shft,  //!< tile pixel Y
-    output       [OUT_WIDTH - 1 : 0] wnd_out            
+    input                           clk,   //!< system clock, posedge
+    input                           en,    //!< re (both re and ren - just for power)
+    input                     [3:0] x_in,  //!< tile pixel X
+    input                     [3:0] y_in,  //!< tile pixel Y
+    input         [SHIFT_WIDTH-1:0] x_shft,  //!< tile pixel X
+    input         [SHIFT_WIDTH-1:0] y_shft,  //!< tile pixel Y
+    output signed [OUT_WIDTH - 1 : 0] wnd_out            
 );
-    wire [COORD_WIDTH - 1 : 0] x_full;
-    wire [COORD_WIDTH - 1 : 0] y_full;
-    wire                       x_zero;
-    wire                       y_zero;
-    reg                  [1:0] zero; // x_zero | y_zero;
-    reg                  [2:0] regen; //
-    wire   [OUT_WIDTH - 1 : 0] wnd_out_x;            
-    wire   [OUT_WIDTH - 1 : 0] wnd_out_y;            
-    reg  [2*OUT_WIDTH - 1 : 0] wnd_out_r;
-    assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 1: OUT_WIDTH];
+    wire        [COORD_WIDTH - 1 : 0] x_full;
+    wire        [COORD_WIDTH - 1 : 0] y_full;
+    wire                              x_zero;
+    wire                              y_zero;
+//    reg                  [1:0] zero; // x_zero | y_zero;
+    reg                               zero; // x_zero | y_zero;
+    reg                         [2:0] regen; //
+    wire signed   [OUT_WIDTH - 1 : 0] wnd_out_x;   // should be all positive         
+    wire signed   [OUT_WIDTH - 1 : 0] wnd_out_y;   // should be all positive         
+    reg  signed   [OUT_WIDTH - 1 : 0] wnd_out_x_r; // to be absorbed in DSP            
+    reg  signed   [OUT_WIDTH - 1 : 0] wnd_out_y_r; // to be absorbed in DSP            
+    reg  signed [2*OUT_WIDTH - 1 : 0] wnd_out_r;   // should be all positive
+    assign wnd_out = wnd_out_r[2 * OUT_WIDTH - 2: OUT_WIDTH-1];
     
    always @ (posedge clk) begin
        regen <= {regen[1:0],en};
-        zero <= {1'b0, x_zero | y_zero};
-        wnd_out_r <= wnd_out_x * wnd_out_y;
+        wnd_out_x_r <= wnd_out_x;
+        wnd_out_y_r <= wnd_out_y;
+//        zero <= {zero[0],  x_zero | y_zero};
+        zero <= x_zero | y_zero;
+        wnd_out_r <= wnd_out_x_r * wnd_out_y_r;
    end

    mclt_full_shift #(
@@ -106,7 +112,7 @@ module  mclt_wnd_mul#(
        .regen_a   (regen[2]),  // input
        .we_a      (1'b0),      // input
        .rrst_a    (1'b0),      // input
-        .regrst_a  (zero[1]),   // input
+        .regrst_a  (zero),      // input
        .data_out_a(wnd_out_x), // output[17:0] 
        .data_in_a (18'b0),     // input[17:0] 
        .clk_b     (clk),       // input
@@ -115,7 +121,7 @@ module  mclt_wnd_mul#(
        .regen_b   (regen[2]),  // input
        .we_b      (1'b0),      // input
        .rrst_b    (1'b0),      // input
-        .regrst_b  (zero[1]),   // input
+        .regrst_b  (zero),      // input
        .data_out_b(wnd_out_y), // output[17:0] 
        .data_in_b (18'b0)      // input[17:0] 
    );

--- a/includes/mclt_wnd_mul.vh
+++ b/includes/mclt_wnd_mul.vh
 // Created with ./create_wnd_mul_rom.py
 // MCLT 1d 16 count window with 128:1 super resolution data
-, .INIT_00 (256'h1921178F15FD146B12D911470FB50E230C910AFF096D07DB064804B603240192)
-, .INIT_01 (256'h323F30AD2F1B2D8A2BF82A6628D4274325B1241F228D20FB1F691DD71C451AB3)
-, .INIT_02 (256'h4B5449C3483246A14510437F41ED405C3ECB3D393BA83A17388536F4356233D0)
-, .INIT_03 (256'h645F62CE613E5FAE5E1D5C8D5AFC596C57DB564A54BA5329519850074E764CE5)
-, .INIT_04 (256'h7D597BCA7A3B78AB771C758D73FD726E70DE6F4E6DBF6C2F6A9F690F677F65EF)
-, .INIT_05 (256'h964094B39325919790098E7A8CEC8B5E89CF884186B285248395820680777EE8)
-, .INIT_06 (256'hAF10AD84ABF8AA6BA8DFA752A5C5A439A2ACA11E9F919E049C779AE9995C97CE)
-, .INIT_07 (256'hC7C6C63BC4B1C326C19BC010BE85BCFABB6FB9E3B858B6CCB540B3B5B229B09D)
-, .INIT_08 (256'hE05CDED3DD4BDBC2DA39D8B0D727D59ED415D28BD102CF78CDEECC64CADAC950)
-, .INIT_09 (256'hF8D0F749F5C3F43DF2B6F12FEFA8EE21EC9AEB13E98CE804E67CE4F4E36CE1E4)
-, .INIT_0A (256'h111D0F990E150C910B0D09890805068004FB037601F1006CFEE7FD61FBDBFA56)
-, .INIT_0B (256'h294027BF263E24BD233B21BA20381EB61D341BB21A2F18AD172A15A7142412A0)
-, .INIT_0C (256'h41353FB83E393CBB3B3D39BE383F36C0354133C1324230C22F422DC22C412AC1)
-, .INIT_0D (256'h58F9577F56045489530D519250164E9A4D1E4BA14A2548A8472B45AE443142B3)
-, .INIT_0E (256'h70886F116D996C216AA9693167B9664064C8634E61D5605C5EE25D685BEE5A74)
-, .INIT_0F (256'h87DE866A84F68382820E80997F247DAF7C3A7AC5794F77D9766374EC737671FF)
-, .INIT_10 (256'h9EF79D879C179AA7993797C6965594E493729201908F8F1C8DAA8C378AC48951)
-, .INIT_11 (256'hB5D1B465B2F9B18DB020AEB4AD47ABDAAA6CA8FEA790A622A4B4A345A1D6A067)
-, .INIT_12 (256'hCC66CAFFC998C830C6C8C55FC3F6C28DC124BFBBBE51BCE7BB7DBA12B8A7B73C)
-, .INIT_13 (256'hE2B5E153DFEFDE8CDD28DBC5DA60D8FCD797D632D4CDD367D201D09BCF34CDCE)
-, .INIT_14 (256'hF8BAF75CF5FDF49FF340F1E1F081EF21EDC1EC61EB00E99FE83EE6DCE57AE418)
-, .INIT_15 (256'h0E700D170BBE0A64090A07B0065504FA039F024300E8FF8BFE2FFCD2FB75FA18)
-, .INIT_16 (256'h23D62282212E1FD91E841D2F1BDA1A84192E17D71680152913D2127A11220FC9)
-, .INIT_17 (256'h38E73798364934FA33AB325B310B2FBA2E692D182BC62A74292227D0267D2529)
-, .INIT_18 (256'h4DA04C574B0E49C4487A473045E5449A434F420340B73F6A3E1E3CD03B833A35)
-, .INIT_19 (256'h61FE60BB5F785E345CF05BAB5A66592157DB5695554E540752C0517950314EE9)
-, .INIT_1A (256'h75FF74C17384724671086FC96E8A6D4A6C0A6ACA698A6849670765C664846341)
-, .INIT_1B (256'h899E8867872F85F784BF8387824E81147FDB7EA07D667C2B7AF079B47878773B)
-, .INIT_1C (256'h9CD99BA89A779945981496E195AF947B9348921490E08FAB8E768D418C0B8AD4)
-, .INIT_1D (256'hAFACAE82AD58AC2DAB01A9D6A8A9A77DA650A522A3F4A2C6A197A0689F399E09)
-, .INIT_1E (256'hC216C0F3BFCFBEABBD86BC61BB3BBA15B8EFB7C8B6A1B579B451B328B200B0D6)
-, .INIT_1F (256'hD413D2F7D1DAD0BCCF9ECE80CD61CC42CB22CA02C8E2C7C1C6A0C57EC45CC339)
-, .INIT_20 (256'hE5A0E48BE375E25EE148E030DF19DE00DCE8DBCFDAB5D99BD881D766D64BD52F)
-, .INIT_21 (256'hF6BBF5ADF49EF38FF27FF16FF05FEF4EEE3CED2AEC18EB05E9F2E8DEE7CAE6B5)
-, .INIT_22 (256'h0761065A0553044B0343023A01310027FF1DFE12FD07FBFCFAF0F9E3F8D6F7C9)
-, .INIT_23 (256'h178F169015901490138F128E118C108A0F870E840D810C7C0B780A73096D0867)
-, .INIT_24 (256'h2743264C2554245B23622268216E20741F791E7D1D811C851B881A8A198D188E)
-, .INIT_25 (256'h367B358B349B33AA32B931C730D52FE22EEF2DFB2D072C122B1D2A282931283B)
-, .INIT_26 (256'h4534444C4364427B419240A83FBE3ED33DE83CFC3C103B233A3539483859376B)
-, .INIT_27 (256'h536C528C51AC50CB4FEA4F094E264D444C604B7D4A9849B448CE47E84702461B)
-, .INIT_28 (256'h612060495F715E995DC05CE65C0C5B325A57597B589F57C356E55608552A544B)
-, .INIT_29 (256'h6E506D816CB16BE16B106A3F696E689B67C966F66622654E647963A462CE61F7)
-, .INIT_2A (256'h7AF77A31796A78A277DA77117648757F74B473EA731E7253718670B96FEC6F1E)
-, .INIT_2B (256'h87158658859984DA841B835B829A81D9811880557F937ED07E0C7D477C837BBD)
-, .INIT_2C (256'h92A891F3913E90888FD18F1A8E628DA98CF18C378B7D8AC28A07894C889087D3)
-, .INIT_2D (256'h9DAE9D029C559BA89AFA9A4C999D98ED983D978D96DB962A957794C49411935D)
-, .INIT_2E (256'hA826A782A6DFA63AA595A4F0A44AA3A3A2FCA254A1ACA103A05A9FB09F059E5A)
-, .INIT_2F (256'hB20DB172B0D8B03CAFA0AF04AE67ADC9AD2BAC8DABEDAB4DAAADAA0CA96AA8C8)
-, .INIT_30 (256'hBB62BAD1BA3FB9ADB91AB887B7F3B75EB6C9B634B59EB507B470B3D8B33FB2A6)
-, .INIT_31 (256'hC423C39BC313C28AC201C177C0ECC061BFD5BF48BEBBBE2EBDA0BD11BC82BBF2)
-, .INIT_32 (256'hCC50CBD2CB53CAD3CA53C9D2C951C8CFC84CC7C9C746C6C1C63CC5B7C531C4AA)
-, .INIT_33 (256'hD3E7D372D2FDD286D210D198D120D0A8D02FCFB5CF3ACEC0CE44CDC8CD4BCCCE)
-, .INIT_34 (256'hDAE7DA7CDA0FD9A3D935D8C7D859D7EAD77AD70AD699D627D5B5D543D4CFD45C)
-, .INIT_35 (256'hE14FE0EDE08AE027DFC3DF5FDEFADE94DE2EDDC7DD60DCF8DC8FDC26DBBCDB52)
-, .INIT_36 (256'hE71DE6C5E66CE612E5B8E55DE502E4A6E449E3ECE38EE330E2D1E271E211E1B0)
-, .INIT_37 (256'hEC52EC03EBB4EB64EB13EAC2EA70EA1EE9CBE977E923E8CEE879E823E7CCE775)
-, .INIT_38 (256'hF0ECF0A7F061F01BEFD4EF8CEF44EEFCEEB2EE68EE1EEDD3ED87ED3BECEEECA0)
-, .INIT_39 (256'hF4EAF4AEF472F436F3F9F3BBF37DF33EF2FEF2BEF27DF23CF1FAF1B7F174F130)
-, .INIT_3A (256'hF84CF81AF7E8F7B5F782F74EF719F6E4F6AEF678F641F609F5D1F598F55EF524)
-, .INIT_3B (256'hFB11FAE9FAC1FA98FA6EFA44FA19F9EEF9C2F995F968F93AF90CF8DCF8ADF87C)
-, .INIT_3C (256'hFD39FD1BFCFCFCDDFCBDFC9DFC7CFC5BFC38FC16FBF2FBCEFBA9FB84FB5EFB38)
-, .INIT_3D (256'hFEC3FEAFFE9BFE85FE6FFE59FE42FE2AFE12FDF9FDDFFDC5FDAAFD8FFD73FD56)
-, .INIT_3E (256'hFFB0FFA6FF9BFF90FF84FF77FF6AFF5CFF4DFF3EFF2FFF1EFF0DFEFCFEE9FED7)
-, .INIT_3F (256'hFFFFFFFFFFFEFFFCFFFAFFF7FFF4FFF0FFEBFFE6FFE0FFDAFFD3FFCBFFC3FFBA)
-, .INITP_01 (256'h5555555555555555555555555555555555555555555555000000000000000000)
-, .INITP_02 (256'hAAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555)
-, .INITP_03 (256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA)
-, .INITP_04 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAA)
-, .INITP_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
-, .INITP_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
-, .INITP_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+, .INIT_00 (256'h0BC80AFF0A36096D08A407DB07110648057F04B603ED0324025B019200C9FFFF)
+, .INIT_01 (256'h1857178E16C515FC1533146A13A112D8120F1146107E0FB50EEC0E230D5A0C91)
+, .INIT_02 (256'h24E224192351228821BF20F7202E1F651E9D1DD41D0B1C421B7A1AB119E8191F)
+, .INIT_03 (256'h3167309F2FD72F0F2E462D7E2CB62BEE2B252A5D299428CC2804273B267325AA)
+, .INIT_04 (256'h3DE53D1D3C563B8E3AC639FF3937386F37A736DF3617354F348733BF32F7322F)
+, .INIT_05 (256'h4A59499248CB4804473D467645AF44E844204359429241CA4103403C3F743EAC)
+, .INIT_06 (256'h56C255FC5536546F53A952E3521C5156508F4FC94F024E3B4D754CAE4BE74B20)
+, .INIT_07 (256'h631D6258619360CD60085F425E7D5DB75CF25C2C5B665AA059DA5914584E5788)
+, .INIT_08 (256'h6F6A6EA56DE16D1D6C586B946ACF6A0A6946688167BC66F76632656D64A863E3)
+, .INIT_09 (256'h7BA57AE17A1E795B789877D47711764D758974C67402733E727A71B670F2702E)
+, .INIT_0A (256'h87CC870B8649858784C484028340827D81BB80F880367F737EB07DEE7D2B7C68)
+, .INIT_0B (256'h93DF931F925E919E90DD901C8F5B8E9A8DD98D178C568B958AD38A128950888E)
+, .INIT_0C (256'h9FDC9F1D9E5D9D9E9CDF9C1F9B609AA099E19921986197A196E19621956094A0)
+, .INIT_0D (256'hABBFAB02AA44A986A8C9A80BA74DA68FA5D1A512A454A395A2D7A218A159A09B)
+, .INIT_0E (256'hB788B6CCB611B555B498B3DCB320B264B1A7B0EAB02EAF71AEB4ADF7AD3AAC7C)
+, .INIT_0F (256'hC335C27BC1C1C107C04CBF92BED8BE1DBD62BCA7BBECBB31BA76B9BBB8FFB844)
+, .INIT_10 (256'hCEC4CE0CCD53CC9BCBE3CB2ACA72C9B9C900C847C78EC6D5C61BC562C4A8C3EF)
+, .INIT_11 (256'hDA32D97CD8C6D810D75AD6A3D5EDD536D47FD3C8D311D25AD1A2D0EBD033CF7B)
+, .INIT_12 (256'hE57FE4CCE418E364E2AFE1FBE146E092DFDDDF28DE73DDBEDD09DC53DB9EDAE8)
+, .INIT_13 (256'hF0A9EFF8EF46EE94EDE2ED30EC7EEBCBEB19EA66E9B3E900E84DE79AE6E7E633)
+, .INIT_14 (256'hFBAEFAFEFA4FF9A0F8F0F840F790F6E0F630F580F4CFF41FF36EF2BDF20CF15A)
+, .INIT_15 (256'h068B05DF0532048503D8032A027D01CF01210074FFC5FF17FE69FDBAFD0CFC5D)
+, .INIT_16 (256'h114110970FEC0F420E970DED0D420C960BEB0B400A9409E9093D089107E40738)
+, .INIT_17 (256'h1BCC1B241A7D19D5192D188517DD1734168C15E3153A149113E8133E129411EB)
+, .INIT_18 (256'h262B258724E2243D239822F2224D21A72101205B1FB51F0E1E681DC11D1A1C73)
+, .INIT_19 (256'h305D2FBC2F1A2E772DD52D332C902BED2B4A2AA72A03296028BC2818277426D0)
+, .INIT_1A (256'h3A6039C23923388337E4374536A53605356534C53424338332E3324231A030FF)
+, .INIT_1B (256'h4433439742FB425F41C34127408A3FED3F503EB33E153D783CDA3C3C3B9D3AFF)
+, .INIT_1C (256'h4DD44D3B4CA24C094B704AD74A3D49A4490A487047D5473B46A04605456A44CF)
+, .INIT_1D (256'h574156AC5616558054EA545453BE5327529151FA516350CB50344F9C4F044E6C)
+, .INIT_1E (256'h60795FE75F555EC35E305D9D5D0A5C775BE45B505ABC5A28599458FF586B57D6)
+, .INIT_1F (256'h697B68EC685E67CF674066B0662165916501647163E0635062BF622E619C610B)
+, .INIT_20 (256'h724571BA712F70A370186F8C6F006E746DE76D5A6CCD6C406BB36B256A976A09)
+, .INIT_21 (256'h7AD67A4F79C7793F78B7782F77A6771E7695760C758274F9746F73E5735A72D0)
+, .INIT_22 (256'h832D82A9822581A1811D809880137F8E7F097E837DFD7D777CF17C6B7BE47B5D)
+, .INIT_23 (256'h8B488AC88A4889C7894788C6884587C3874286C0863E85BC853984B6843383B0)
+, .INIT_24 (256'h932692A9922D91B1913490B7903A8FBC8F3E8EC08E428DC48D458CC68C478BC7)
+, .INIT_25 (256'h9AC59A4D99D5995C98E3986A97F1977796FD96839609958E95139498941D93A1)
+, .INIT_26 (256'hA226A1B2A13DA0C9A0549FDE9F699EF39E7E9E079D919D1A9CA39C2C9BB59B3D)
+, .INIT_27 (256'hA946A8D6A865A7F5A784A713A6A1A630A5BEA54CA4D9A467A3F4A381A30DA29A)
+, .INIT_28 (256'hB024AFB8AF4CAEDFAE73AE06AD98AD2BACBDAC4FABE1AB72AB04AA94AA25A9B6)
+, .INIT_29 (256'hB6C0B658B5F0B588B51FB4B6B44DB3E4B37AB311B2A6B23CB1D1B166B0FBB090)
+, .INIT_2A (256'hBD18BCB4BC51BBEDBB88BB24BABFBA5AB9F4B98FB929B8C3B85CB7F6B78FB727)
+, .INIT_2B (256'hC32BC2CCC26DC20DC1ADC14DC0ECC08BC02ABFC9BF67BF05BEA3BE41BDDEBD7B)
+, .INIT_2C (256'hC8F9C89EC843C7E8C78CC730C6D4C678C61BC5BEC561C503C4A5C447C3E9C38A)
+, .INIT_2D (256'hCE81CE2ACDD4CD7DCD25CCCECC76CC1ECBC6CB6DCB14CABBCA62CA08C9AEC954)
+, .INIT_2E (256'hD3C1D36FD31DD2CAD277D224D1D1D17ED12AD0D6D081D02CCFD7CF82CF2DCED7)
+, .INIT_2F (256'hD8B9D86BD81ED7D0D782D733D6E4D695D646D5F6D5A6D556D506D4B5D464D412)
+, .INIT_30 (256'hDD68DD1FDCD6DC8DDC43DBF9DBAFDB64DB19DACEDA83DA37D9EBD99FD953D906)
+, .INIT_31 (256'hE1CDE189E145E100E0BBE075E030DFEADFA4DF5DDF17DECFDE88DE40DDF9DDB0)
+, .INIT_32 (256'hE5E8E5A9E569E529E4E9E4A8E467E426E3E4E3A2E360E31EE2DBE298E255E211)
+, .INIT_33 (256'hE9B9E97EE943E907E8CCE890E853E817E7DAE79DE75FE722E6E3E6A5E667E628)
+, .INIT_34 (256'hED3DED07ECD1EC9AEC63EC2CEBF4EBBDEB84EB4CEB13EADAEAA1EA67EA2DE9F3)
+, .INIT_35 (256'hF076F045F013EFE1EFAFEF7CEF4AEF17EEE3EEAFEE7CEE47EE13EDDEEDA9ED73)
+, .INIT_36 (256'hF362F336F309F2DCF2AEF281F253F224F1F6F1C7F197F168F138F108F0D8F0A7)
+, .INIT_37 (256'hF601F5D9F5B1F589F561F538F50FF4E5F4BBF491F467F43CF411F3E6F3BAF38E)
+, .INIT_38 (256'hF853F830F80DF7E9F7C6F7A2F77DF759F734F70EF6E9F6C3F69DF676F650F629)
+, .INIT_39 (256'hFA57FA39FA1AF9FCF9DDF9BEF99EF97FF95EF93EF91DF8FCF8DBF8B9F898F875)
+, .INIT_3A (256'hFC0DFBF3FBDAFBC0FBA6FB8CFB72FB57FB3BFB20FB04FAE8FACBFAAFFA92FA74)
+, .INIT_3B (256'hFD74FD60FD4BFD37FD21FD0CFCF6FCE0FCCAFCB3FC9DFC85FC6EFC56FC3EFC25)
+, .INIT_3C (256'hFE8DFE7EFE6EFE5EFE4EFE3EFE2DFE1CFE0AFDF9FDE7FDD4FDC2FDAFFD9BFD88)
+, .INIT_3D (256'hFF57FF4DFF42FF37FF2CFF20FF15FF08FEFCFEEFFEE2FED5FEC7FEB9FEAAFE9C)
+, .INIT_3E (256'hFFD2FFCDFFC7FFC1FFBBFFB4FFADFFA6FF9FFF97FF8FFF86FF7DFF74FF6BFF61)
+, .INIT_3F (256'hFFFFFFFEFFFEFFFDFFFBFFF9FFF7FFF5FFF3FFF0FFECFFE9FFE5FFE1FFDCFFD8)
+, .INITP_00 (256'h0000000000000000000000000000000000000000000000000000000000000001)
+, .INITP_02 (256'h5555555555555555555550000000000000000000000000000000000000000000)
+, .INITP_03 (256'h5555555555555555555555555555555555555555555555555555555555555555)
+, .INITP_04 (256'h5555555555555555555555555555555555555555555555555555555555555555)
+, .INITP_05 (256'h5555555555555555555555555555555555555555555555555555555555555555)
+, .INITP_06 (256'h5555555555555555555555555555555555555555555555555555555555555555)
+, .INITP_07 (256'h5555555555555555555555555555555555555555555555555555555555555555)
--- a/mclt_test_01.sav
+++ b/mclt_test_01.sav
 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Thu Dec 14 06:19:18 2017
+[*] Sat Dec 16 19:54:45 2017
 [*]
-[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171213195034071.fst"
-[dumpfile_mtime] "Thu Dec 14 02:50:36 2017"
-[dumpfile_size] 935652
+[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_01-20171215180909701.fst"
+[dumpfile_mtime] "Sat Dec 16 01:09:12 2017"
+[dumpfile_size] 940154
 [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_01.sav"
-[timestart] 365600
-[size] 1920 1171
-[pos] -1921 -1
-*-15.459125 415000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[timestart] 394400
+[size] 1814 1171
+[pos] -1 -1
+*-15.197140 538600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] mclt_test_01.
 [treeopen] mclt_test_01.mclt16x16_i.
+[treeopen] mclt_test_01.mclt16x16_i.mclt_wnd_i.
 [sst_width] 242
-[signals_width] 275
+[signals_width] 251
 [sst_expanded] 1
 [sst_vpaned_height] 344
 @800200
@@ -45,11 +46,29 @@ mclt_test_01.dv
 mclt_test_01.dout[24:0]
 @28
 mclt_test_01.pre_last_out
+@420
+mclt_test_01.n1
+mclt_test_01.cntr1
+@22
+mclt_test_01.java_fi_w[7:0]
+@420
+[color] 2
+mclt_test_01.diff1
+mclt_test_01.n2
+mclt_test_01.cntr2
+@22
+mclt_test_01.window_r[17:0]
+mclt_test_01.java_window_w[17:0]
+@420
+mclt_test_01.diff2
+mclt_test_01.diff2a
+@8420
+mclt_test_01.diff2a
 @1000200
 -top
 @800200
 -mclt16x16
-@800022
+@c00022
 mclt_test_01.mclt16x16_i.in_busy[16:0]
 @28
 (0)mclt_test_01.mclt16x16_i.in_busy[16:0]
@@ -69,7 +88,7 @@ mclt_test_01.mclt16x16_i.in_busy[16:0]
 (14)mclt_test_01.mclt16x16_i.in_busy[16:0]
 (15)mclt_test_01.mclt16x16_i.in_busy[16:0]
 (16)mclt_test_01.mclt16x16_i.in_busy[16:0]
-@1001200
+@1401200
 -group_end
 @22
 mclt_test_01.mclt16x16_i.in_cntr[7:0]
@@ -84,7 +103,6 @@ mclt_test_01.mclt16x16_i.mpixel_a[7:0]
 mclt_test_01.mclt16x16_i.mpixel_d[15:0]
 mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]
 mclt_test_01.mclt16x16_i.pix_wnd_r[33:0]
-@23
 mclt_test_01.mclt16x16_i.pix_wnd_r2[24:0]
 @28
 mclt_test_01.mclt16x16_i.mpix_use_d
@@ -115,25 +133,31 @@ mclt_test_01.mclt16x16_i.i_mclt_fold_rom.data_out_a[17:0]
 -
 @1401200
 -fold_rom
-@c00200
+@800200
 -mclt_wnd_mul
 @28
 mclt_test_01.mclt16x16_i.mclt_wnd_i.en
 @22
-mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
 mclt_test_01.mclt16x16_i.mclt_wnd_i.x_shft[6:0]
-@8022
+mclt_test_01.mclt16x16_i.mclt_wnd_i.y_shft[6:0]
 mclt_test_01.mclt16x16_i.mclt_wnd_i.x_in[3:0]
 mclt_test_01.mclt16x16_i.mclt_wnd_i.y_in[3:0]
 mclt_test_01.mclt16x16_i.mclt_wnd_i.x_full[9:0]
 @28
 mclt_test_01.mclt16x16_i.mclt_wnd_i.x_zero
-@8022
+@22
 mclt_test_01.mclt16x16_i.mclt_wnd_i.y_full[9:0]
 @28
-mclt_test_01.mclt16x16_i.mclt_wnd_i.y_zero
+mclt_test_01.mclt16x16_i.mclt_wnd_i.zero
+@c00022
 mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
-@c08022
+@28
+(0)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
+(1)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
+(2)mclt_test_01.mclt16x16_i.mclt_wnd_i.regen[2:0]
+@1401200
+-group_end
+@c00022
 mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
 @28
 (0)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
@@ -156,11 +180,36 @@ mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
 (17)mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_x[17:0]
 @1401200
 -group_end
-@8022
+@22
 mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out_y[17:0]
+mclt_test_01.mclt16x16_i.mclt_wnd_i.wnd_out[17:0]
+@c00200
+-wnd_rom
+@22
+mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.addr_a[9:0]
+@28
+mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.en_a
+mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regen_a
+mclt_test_01.mclt16x16_i.mclt_wnd_i.i_wnd_rom.regrst_a
+@200
+-
 @1401200
+-wnd_rom
+@c00200
+-mclt_full_shift_x
+@22
+mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord[3:0]
+mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.shift[6:0]
+mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_w[11:0]
+mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.mod_coord_r[11:0]
+mclt_test_01.mclt16x16_i.mclt_wnd_i.mclt_full_shift_x_i.coord_out[9:0]
+@200
+-
+@1401200
+-mclt_full_shift_x
+@1000200
 -mclt_wnd_mul
-@c08022
+@c08023
 mclt_test_01.mclt16x16_i.window_r[17:0]
 @28
 (0)mclt_test_01.mclt16x16_i.window_r[17:0]
@@ -181,7 +230,7 @@ mclt_test_01.mclt16x16_i.window_r[17:0]
 (15)mclt_test_01.mclt16x16_i.window_r[17:0]
 (16)mclt_test_01.mclt16x16_i.window_r[17:0]
 (17)mclt_test_01.mclt16x16_i.window_r[17:0]
-@1401200
+@1401201
 -group_end
 @8022
 mclt_test_01.mclt16x16_i.mpixel_d_r[15:0]