more debugging by simulation, bug fixing (38d73a7b) · Commits · Elphel / x393

memctrl/mcntrl393.v

+10 −1

Original line number	Original line	Diff line number	Diff line
	@@ -334,6 +334,7 @@ module mcntrl393 #(
	// wire rpage_nxt_chn0;		// wire rpage_nxt_chn0;
	wire buf_wr_chn0;		wire buf_wr_chn0;
	wire buf_wpage_nxt_chn0;		wire buf_wpage_nxt_chn0;
			wire buf_run0;
	wire [63:0] buf_wdata_chn0;		wire [63:0] buf_wdata_chn0;

	wire want_rq1;		wire want_rq1;
	@@ -341,6 +342,7 @@ module mcntrl393 #(
	wire channel_pgm_en1;		wire channel_pgm_en1;
	wire seq_done1;		wire seq_done1;
	wire rpage_nxt_chn1;		wire rpage_nxt_chn1;
			wire buf_run1;
	wire buf_rd_chn1;		wire buf_rd_chn1;
	wire [63:0] buf_rdata_chn1;		wire [63:0] buf_rdata_chn1;

	@@ -986,6 +988,7 @@ module mcntrl393 #(
	.seq_done0 (seq_done0), // input		.seq_done0 (seq_done0), // input
	.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk		.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
	.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // input @negedge mclk		.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // input @negedge mclk
			.buf_run0 (buf_run0), // input
	.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk		.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk

	.want_rq1 (want_rq1), // output reg		.want_rq1 (want_rq1), // output reg
	@@ -993,6 +996,7 @@ module mcntrl393 #(
	.channel_pgm_en1 (channel_pgm_en1), // input		.channel_pgm_en1 (channel_pgm_en1), // input
	.seq_done1 (seq_done1), // input		.seq_done1 (seq_done1), // input
	.rpage_nxt_chn1 (rpage_nxt_chn1), // input		.rpage_nxt_chn1 (rpage_nxt_chn1), // input
			.buf_run1 (buf_run1), // input
	.buf_rd_chn1 (buf_rd_chn1), // input		.buf_rd_chn1 (buf_rd_chn1), // input
	.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]		.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
	);		);
	@@ -1091,6 +1095,7 @@ module mcntrl393 #(
	.seq_set0 (seq_set0), // input		.seq_set0 (seq_set0), // input
	.seq_done0 (seq_done0), // output		.seq_done0 (seq_done0), // output
	.rpage_nxt_chn0 (), //rpage_nxt_chn0), not used		.rpage_nxt_chn0 (), //rpage_nxt_chn0), not used
			.buf_run0 (buf_run0),
	.buf_wr_chn0 (buf_wr_chn0), // output		.buf_wr_chn0 (buf_wr_chn0), // output
	.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output		.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
	// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]		// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
	@@ -1104,6 +1109,7 @@ module mcntrl393 #(
	.seq_set1 (seq_set0), // seq_set0 from channel 0 (shared in ps_pio), // input		.seq_set1 (seq_set0), // seq_set0 from channel 0 (shared in ps_pio), // input
	.seq_done1 (seq_done1), // output		.seq_done1 (seq_done1), // output
	.rpage_nxt_chn1 (rpage_nxt_chn1), // output		.rpage_nxt_chn1 (rpage_nxt_chn1), // output
			.buf_run1 (buf_run1),
	.buf_rd_chn1 (buf_rd_chn1), // output		.buf_rd_chn1 (buf_rd_chn1), // output
	.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]		.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]

	@@ -1115,6 +1121,7 @@ module mcntrl393 #(
	.seq_set2 (seq_set2x), // input		.seq_set2 (seq_set2x), // input
	.seq_done2 (seq_done2), // output		.seq_done2 (seq_done2), // output
	.rpage_nxt_chn2 (), // not used rpage_nxt_chn2), // output		.rpage_nxt_chn2 (), // not used rpage_nxt_chn2), // output
			.buf_run2 (),
	.buf_wr_chn2 (buf_wr_chn2), // output		.buf_wr_chn2 (buf_wr_chn2), // output
	.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output		.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
	.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]		.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
	@@ -1127,6 +1134,7 @@ module mcntrl393 #(
	.seq_set3 (seq_set3x), // input		.seq_set3 (seq_set3x), // input
	.seq_done3 (seq_done3), // output		.seq_done3 (seq_done3), // output
	.rpage_nxt_chn3 (rpage_nxt_chn3), // output		.rpage_nxt_chn3 (rpage_nxt_chn3), // output
			.buf_run3 (),
	.buf_rd_chn3 (buf_rd_chn3), // output		.buf_rd_chn3 (buf_rd_chn3), // output
	.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]		.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]

	@@ -1138,6 +1146,7 @@ module mcntrl393 #(
	.seq_set4 (seq_set4x), // input		.seq_set4 (seq_set4x), // input
	.seq_done4 (seq_done4), // output		.seq_done4 (seq_done4), // output
	.rpage_nxt_chn4 (rpage_nxt_chn4), // output		.rpage_nxt_chn4 (rpage_nxt_chn4), // output
			.buf_run4 (),
	.buf_wr_chn4 (buf_wr_chn4), // output		.buf_wr_chn4 (buf_wr_chn4), // output
	.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output		.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
	.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]		.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]

memctrl/mcntrl_ps_pio.v

+80 −28

Original line number	Original line	Diff line number	Diff line
	@@ -57,30 +57,30 @@ module mcntrl_ps_pio#(
	output reg need_rq0,		output reg need_rq0,
	input channel_pgm_en0,		input channel_pgm_en0,
	output [9:0] seq_data0, // only address		output [9:0] seq_data0, // only address
	// output seq_wr0, // never generated
	output seq_set0,		output seq_set0,
	input seq_done0,		input seq_done0,
	input buf_wr_chn0,		input buf_wr_chn0,
	input buf_wpage_nxt_chn0,		input buf_wpage_nxt_chn0,
	// input buf_waddr_rst_chn0,		input buf_run0, // @ negedge, use to force page nimber in the buffer (use fifo)
	input [63:0] buf_wdata_chn0,		input [63:0] buf_wdata_chn0,
	// write port 1		// write port 1
	output reg want_rq1,		output reg want_rq1,
	output reg need_rq1,		output reg need_rq1,
	input channel_pgm_en1,		input channel_pgm_en1,
	// output [9:0] seq_data1, // only address (with seq_set) connect externally to seq_data0
	// output seq_wr1, // never generated
	// output seq_set1, // connect externally to seq_set0
	input seq_done1,		input seq_done1,
	input rpage_nxt_chn1,		input rpage_nxt_chn1,
			input buf_run1, // @ posedge, use to force page nimber in the buffer (use fifo)
	input buf_rd_chn1,		input buf_rd_chn1,
	// input buf_raddr_rst_chn1,
	output [63:0] buf_rdata_chn1		output [63:0] buf_rdata_chn1
	);		);
	localparam CMD_WIDTH=14;		localparam CMD_WIDTH=15;
	localparam CMD_FIFO_DEPTH=4;		localparam CMD_FIFO_DEPTH=4;
			localparam PAGE_FIFO_DEPTH = 4;// fifo depth to hold page numbers for channels (2 bits should be OK now)
			localparam PAGE_CNTR_BITS = 4;

	wire channel_pgm_en=channel_pgm_en0 \|\| channel_pgm_en1;		wire channel_pgm_en=channel_pgm_en0 \|\| channel_pgm_en1;
	wire seq_done= seq_done0 \|\| seq_done1;		wire seq_done= seq_done0 \|\| seq_done1;
			reg [PAGE_CNTR_BITS-1:0] pending_pages;


	wire [4:0] cmd_a; // just to compare		wire [4:0] cmd_a; // just to compare
	@@ -99,30 +99,52 @@ module mcntrl_ps_pio#(
	reg [1:0] en_reset;//		reg [1:0] en_reset;//
	wire chn_rst = ~en_reset[0]; // resets command, including fifo;		wire chn_rst = ~en_reset[0]; // resets command, including fifo;
	wire chn_en = &en_reset[1]; // enable requests by channle (continue ones in progress)		wire chn_en = &en_reset[1]; // enable requests by channle (continue ones in progress)
	reg mem_run; // sequencer pgm granted and set, waiting/executing memory transfer to/from buffur 0/1		// reg mem_run; // sequencer pgm granted and set, waiting/executing memory transfer to/from buffur 0/1
	wire busy;		wire busy;
			wire short_busy; // does not include memory transaction
	wire start;		wire start;
	reg [1:0] page;		//reg [1:0] page;
	reg [1:0] page_neg;		reg [1:0] page_neg;
	reg [1:0] cmd_set_d;		reg [1:0] cmd_set_d;
	reg cmd_set_d_neg;
	// reg chn_run; // running memory access to channel 0/1
	// command bit fields		// command bit fields
	wire [9:0] cmd_seq_a= cmd_out[9:0];		wire [9:0] cmd_seq_a= cmd_out[9:0];
	wire [1:0] cmd_page= cmd_out[11:10];		wire [1:0] cmd_page= cmd_out[11:10];
	wire cmd_need= cmd_out[12];		wire cmd_need= cmd_out[12];
	wire cmd_chn= cmd_out[13];		wire cmd_chn= cmd_out[13];
			wire cmd_wait= cmd_out[14]; // wait cmd finished before proceeding
	reg cmd_set;		reg cmd_set;
			reg cmd_wait_r;

			reg channel_pgm_en0_neg;
			wire [1:0] page_out_chn0;
			wire [1:0] page_out_chn1;
			reg nreset_page_fifo;
			reg nreset_page_fifo_neg;
			// wire page_fifo0_nempty_neg;
			// wire page_fifo1_nempty;
			// reg page_fifo0_nempty;

	assign busy= want_rq0 \|\| need_rq0 \|\|want_rq1 \|\| need_rq1 \|\| mem_run;		assign short_busy= want_rq0 \|\| need_rq0 \|\|want_rq1 \|\| need_rq1 \|\| cmd_set; // cmd_set - advance FIFO
	assign start= chn_en && !busy && cmd_nempty;		assign busy= short_busy \|\| (pending_pages != 0); // mem_run;
			assign start= chn_en && !short_busy && cmd_nempty && ((pending_pages == 0) \|\| !cmd_wait_r); //(!mem_run \|\| !cmd_wait_r); // do not wait memory transaction if wait
	assign seq_data0= cmd_seq_a;		assign seq_data0= cmd_seq_a;
	assign seq_set0=cmd_set;		assign seq_set0=cmd_set;
	assign status_data= {cmd_half_full,cmd_nempty \| busy};		assign status_data= {cmd_half_full,cmd_nempty \| busy};
	assign set_cmd_w = cmd_we && (cmd_a== MCNTRL_PS_CMD);		assign set_cmd_w = cmd_we && (cmd_a== MCNTRL_PS_CMD);
	assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);		assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);
	assign set_en_rst = cmd_we && (cmd_a== MCNTRL_PS_EN_RST);		assign set_en_rst = cmd_we && (cmd_a== MCNTRL_PS_EN_RST);
			//PAGE_CNTR_BITS
	always @ (posedge rst or posedge mclk) begin		always @ (posedge rst or posedge mclk) begin

			if (rst) pending_pages <= 0;
			else if (chn_rst) pending_pages <= 0;
			else if ( cmd_set && !seq_done) pending_pages <= pending_pages + 1;
			else if (!cmd_set && seq_done) pending_pages <= pending_pages - 1;

			if (rst) nreset_page_fifo <= 0;
			else nreset_page_fifo <= cmd_nempty \| busy;
			if (rst) cmd_wait_r <= 0;
			else if (channel_pgm_en) cmd_wait_r <= cmd_wait;
	if (rst) en_reset <= 0;		if (rst) en_reset <= 0;
	else if (set_en_rst) en_reset <= cmd_data[1:0];		else if (set_en_rst) en_reset <= cmd_data[1:0];

	@@ -143,27 +165,28 @@ module mcntrl_ps_pio#(
	need_rq1 <= cmd_chn && cmd_need;		need_rq1 <= cmd_chn && cmd_need;
	end		end

	if (rst) mem_run <=0;		// if (rst) mem_run <=0;
	else if (chn_rst \|\| seq_done) mem_run <=0;		// else if (chn_rst \|\| seq_done) mem_run <=0;
	else if (channel_pgm_en) mem_run <=1;		// else if (channel_pgm_en) mem_run <=1;

	if (rst) cmd_set <= 0;		if (rst) cmd_set <= 0;
	else if (chn_rst) cmd_set <= 0;		else if (chn_rst) cmd_set <= 0;
	else cmd_set <= channel_pgm_en;		else cmd_set <= channel_pgm_en;

	// if (rst) chn_run <= 0;
	// else if (cmd_set) chn_run <= cmd_chn;

	if (rst) page <= 0;
	else if (cmd_set) page <= cmd_page;

	if (rst) cmd_set_d <= 0;		if (rst) cmd_set_d <= 0;
	else cmd_set_d <= {cmd_set_d[0],cmd_set};		else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)

			// if (rst) page_fifo0_nempty <= 0;
			// else page_fifo0_nempty <=page_fifo0_nempty_neg;

	end		end

	always @ (negedge mclk) begin		always @ (negedge mclk) begin
	page_neg <= page;		page_neg <= cmd_page; // page;
	cmd_set_d_neg <= cmd_set_d[1];		// wpage_set_chn0_neg <= cmd_set_d[1];
			nreset_page_fifo_neg <= nreset_page_fifo;
			channel_pgm_en0_neg <= channel_pgm_en0;
	end		end

	cmd_deser #(		cmd_deser #(
	@@ -228,8 +251,8 @@ fifo_same_clock #(
	.ext_regen (port0_regen), // input		.ext_regen (port0_regen), // input
	.ext_data_out (port0_data), // output[31:0]		.ext_data_out (port0_data), // output[31:0]
	.wclk (!mclk), // input		.wclk (!mclk), // input
	.wpage_in (page_neg), // input[1:0]		.wpage_in (page_out_chn0), // page_neg), // input[1:0]
	.wpage_set (cmd_set_d_neg), // input		.wpage_set (buf_run0), //wpage_set_chn0_neg), // input
	.page_next (buf_wpage_nxt_chn0), // input		.page_next (buf_wpage_nxt_chn0), // input
	.page (), // output[1:0]		.page (), // output[1:0]
	.we (buf_wr_chn0), // input		.we (buf_wr_chn0), // input
	@@ -243,13 +266,42 @@ fifo_same_clock #(
	.ext_we (port1_we), // input		.ext_we (port1_we), // input
	.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI		.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
	.rclk (mclk), // input		.rclk (mclk), // input
	.rpage_in (page), // input[1:0]		.rpage_in (page_out_chn1), //page), // input[1:0]
	.rpage_set (cmd_set_d[0]), // input		.rpage_set (buf_run1), // rpage_set_chn1), // input
	.page_next (rpage_nxt_chn1), // input		.page_next (rpage_nxt_chn1), // input
	.page (), // output[1:0]		.page (), // output[1:0]
	.rd (buf_rd_chn1), // input		.rd (buf_rd_chn1), // input
	.data_out (buf_rdata_chn1) // output[63:0]		.data_out (buf_rdata_chn1) // output[63:0]
	);		);
			fifo_same_clock #(
			.DATA_WIDTH(2),
			.DATA_DEPTH(PAGE_FIFO_DEPTH)
			) page_fifo0_i (
			.rst (rst),
			.clk (!mclk), // negedge
			.sync_rst (!nreset_page_fifo_neg), // synchronously reset fifo;
			.we (channel_pgm_en0_neg),
			.re (buf_run0),
			.data_in (page_neg),
			.data_out (page_out_chn0),
			.nempty (), //page_fifo0_nempty_neg),
			.half_full ()
			);

			fifo_same_clock #(
			.DATA_WIDTH(2),
			.DATA_DEPTH(PAGE_FIFO_DEPTH)
			) page_fifo1_i (
			.rst (rst),
			.clk (mclk), // posedge
			.sync_rst (!nreset_page_fifo), // synchronously reset fifo;
			.we (channel_pgm_en1),
			.re (buf_run1),
			.data_in (cmd_page), //page),
			.data_out (page_out_chn1),
			.nempty (), //page_fifo1_nempty),
			.half_full ()
			);


	endmodule		endmodule

memctrl/memctrl16.v

+182 −98

File changed.

Preview size limit exceeded, changes collapsed.

memctrl/phy/mcontr_sequencer.v

+14 −9

Original line number	Original line	Diff line number	Diff line
	@@ -148,6 +148,7 @@ module mcontr_sequencer #(
	// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally		// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
	output [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally		output [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
	output ext_buf_rrefresh, // was refresh, invalidates ext_buf_rchn		output ext_buf_rrefresh, // was refresh, invalidates ext_buf_rchn
			output ext_buf_rrun, // run read sequence (to be used with external buffer to set initial address
	input [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2		input [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2

	// Interface to memory read channels (up to 16)		// Interface to memory read channels (up to 16)
	@@ -158,6 +159,7 @@ module mcontr_sequencer #(
	// output [6:0] ext_buf_waddr, // valid with ext_buf_wr		// output [6:0] ext_buf_waddr, // valid with ext_buf_wr
	output [3:0] ext_buf_wchn, // external buffer channel with timing matching buffer writes		output [3:0] ext_buf_wchn, // external buffer channel with timing matching buffer writes
	output ext_buf_wrefresh, // was refresh, invalidates ext_buf_wchn		output ext_buf_wrefresh, // was refresh, invalidates ext_buf_wchn
			output ext_buf_wrun, // @negedge,first cycle of sequencer run matching write delay
	output [63:0] ext_buf_wdata, // valid with ext_buf_wr		output [63:0] ext_buf_wdata, // valid with ext_buf_wr
	// temporary debug data		// temporary debug data
	output [11:0] tmp_debug		output [11:0] tmp_debug
	@@ -248,15 +250,16 @@ module mcontr_sequencer #(
	// reg [15:0] buf_sel_1hot; // 1 hot channel buffer select		// reg [15:0] buf_sel_1hot; // 1 hot channel buffer select
	wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay		wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay
	wire run_refresh_w_d; // run refresh delayed to match buf_wr delay		wire run_refresh_w_d; // run refresh delayed to match buf_wr delay
			wire run_w_d;

	reg [3:0] run_chn_d;		reg [3:0] run_chn_d;
	reg run_refresh_d;		reg run_refresh_d;

	reg [3:0] run_chn_w_d_negedge;		reg [3:0] run_chn_w_d_negedge;
	reg run_refresh_w_d_negedge;		reg run_refresh_w_d_negedge;
			reg run_w_d_negedge;

	// reg run_seq_d;		reg run_seq_d;

	wire [7:0] tmp_debug_a;		wire [7:0] tmp_debug_a;
	assign tmp_debug[11:0] =		assign tmp_debug[11:0] =
	@@ -267,7 +270,7 @@ module mcontr_sequencer #(
	tmp_debug_a[7:0]};		tmp_debug_a[7:0]};

	assign mcontr_reset=ddr_rst; // to reset controller		assign mcontr_reset=ddr_rst; // to reset controller
	assign run_done=sequence_done;		assign run_done=sequence_done; // & cmd_busy[2]; // limit done to 1 cycle only even if duration is non-zero - already set in pause_len
	assign run_busy=cmd_busy[0]; //earliest		assign run_busy=cmd_busy[0]; //earliest
	assign pause=cmd_fetch? (phy_cmd_add_pause \|\| (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));		assign pause=cmd_fetch? (phy_cmd_add_pause \|\| (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
	/// debugging		/// debugging
	@@ -285,6 +288,7 @@ module mcontr_sequencer #(
	assign ext_buf_rchn= run_chn_d;		assign ext_buf_rchn= run_chn_d;
	assign ext_buf_rrefresh= run_refresh_d;		assign ext_buf_rrefresh= run_refresh_d;
	assign buf_rdata[63:0] = ext_buf_rdata;		assign buf_rdata[63:0] = ext_buf_rdata;
			assign ext_buf_rrun=run_seq_d;

	assign ext_buf_wr= buf_wr_negedge;		assign ext_buf_wr= buf_wr_negedge;
	assign ext_buf_wpage_nxt=buf_waddr_reset_negedge;		assign ext_buf_wpage_nxt=buf_waddr_reset_negedge;
	@@ -292,7 +296,7 @@ module mcontr_sequencer #(
	assign ext_buf_wchn= run_chn_w_d_negedge;		assign ext_buf_wchn= run_chn_w_d_negedge;
	assign ext_buf_wrefresh= run_refresh_w_d_negedge;		assign ext_buf_wrefresh= run_refresh_w_d_negedge;
	assign ext_buf_wdata= buf_wdata_negedge;		assign ext_buf_wdata= buf_wdata_negedge;
			assign ext_buf_wrun= run_w_d_negedge;
	// generation of the control signals from byte-serial channel		// generation of the control signals from byte-serial channel
	// generate 8-bit delay data		// generate 8-bit delay data
	cmd_deser #(		cmd_deser #(
	@@ -459,8 +463,8 @@ module mcontr_sequencer #(
	if (rst) run_refresh_d <= 0;		if (rst) run_refresh_d <= 0;
	else if (run_seq) run_refresh_d <= run_refresh;		else if (run_seq) run_refresh_d <= run_refresh;

	// if (rst) run_seq_d <= 0;		if (rst) run_seq_d <= 0;
	// else run_seq_d <= run_seq;		else run_seq_d <= run_seq;

	end		end
	// re-register buffer write address to match DDR3 data		// re-register buffer write address to match DDR3 data
	@@ -471,6 +475,7 @@ module mcontr_sequencer #(
	buf_wdata_negedge <= buf_wdata;		buf_wdata_negedge <= buf_wdata;
	run_chn_w_d_negedge <= run_chn_w_d; //run_chn_d;		run_chn_w_d_negedge <= run_chn_w_d; //run_chn_d;
	run_refresh_w_d_negedge <= run_refresh_w_d;		run_refresh_w_d_negedge <= run_refresh_w_d;
			run_w_d_negedge <= run_w_d;

	end		end
	// Command sequence memories:		// Command sequence memories:
	@@ -610,12 +615,12 @@ module mcontr_sequencer #(
	);		);
	assign wbuf_delay_m1=wbuf_delay-1;		assign wbuf_delay_m1=wbuf_delay-1;

	dly_16 #(5) buf_wchn_dly_i (		dly_16 #(6) buf_wchn_dly_i (
	.clk(mclk), // input		.clk(mclk), // input
	.rst(1'b0), // input		.rst(1'b0), // input
	.dly(wbuf_delay_m1), //wbuf_delay[3:0]-1), // input[3:0]		.dly(wbuf_delay_m1), //wbuf_delay[3:0]-1), // input[3:0]
	.din({run_refresh_d, run_chn_d}), // input		.din({run_seq_d, run_refresh_d, run_chn_d}), // input
	.dout({run_refresh_w_d,run_chn_w_d}) // output reg		.dout({run_w_d,run_refresh_w_d,run_chn_w_d}) // output reg
	);		);
	//run_chn_w_d		//run_chn_w_d
	endmodule		endmodule

memctrl/phy/phy_cmd.v

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -255,7 +255,7 @@ module phy_cmd#(
	assign phy_rcw_in= ~phy_rcw_cur;		assign phy_rcw_in= ~phy_rcw_cur;
	assign phy_cmd_nop= (phy_rcw_pos==0) && !add_pause; // ignores inserted NOP		assign phy_cmd_nop= (phy_rcw_pos==0) && !add_pause; // ignores inserted NOP
	assign sequence_done= phy_cmd_nop && phy_addr_in[CMD_DONE_BIT];		assign sequence_done= phy_cmd_nop && phy_addr_in[CMD_DONE_BIT];
	assign pause_len= phy_addr_in[CMD_PAUSE_BITS-1:0];		assign pause_len= phy_addr_in[CMD_DONE_BIT]? 0: phy_addr_in[CMD_PAUSE_BITS-1:0]; // protect from non-zero length with done bit

	assign phy_addr_calm= (phy_cmd_nop \|\| add_pause) ? phy_addr_prev : phy_addr_in;		assign phy_addr_calm= (phy_cmd_nop \|\| add_pause) ? phy_addr_prev : phy_addr_in;
	assign phy_bank_calm= (phy_cmd_nop \|\| add_pause) ? phy_bank_prev : phy_bank_in;		assign phy_bank_calm= (phy_cmd_nop \|\| add_pause) ? phy_bank_prev : phy_bank_in;