Commit 38d73a7b authored by Andrey Filippov's avatar Andrey Filippov

more debugging by simulation, bug fixing

parent f4751492
......@@ -334,6 +334,7 @@ module mcntrl393 #(
// wire rpage_nxt_chn0;
wire buf_wr_chn0;
wire buf_wpage_nxt_chn0;
wire buf_run0;
wire [63:0] buf_wdata_chn0;
wire want_rq1;
......@@ -341,6 +342,7 @@ module mcntrl393 #(
wire channel_pgm_en1;
wire seq_done1;
wire rpage_nxt_chn1;
wire buf_run1;
wire buf_rd_chn1;
wire [63:0] buf_rdata_chn1;
......@@ -986,6 +988,7 @@ module mcntrl393 #(
.seq_done0 (seq_done0), // input
.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // input @negedge mclk
.buf_run0 (buf_run0), // input
.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk
.want_rq1 (want_rq1), // output reg
......@@ -993,6 +996,7 @@ module mcntrl393 #(
.channel_pgm_en1 (channel_pgm_en1), // input
.seq_done1 (seq_done1), // input
.rpage_nxt_chn1 (rpage_nxt_chn1), // input
.buf_run1 (buf_run1), // input
.buf_rd_chn1 (buf_rd_chn1), // input
.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
);
......@@ -1091,6 +1095,7 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.rpage_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0),
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
......@@ -1103,7 +1108,8 @@ module mcntrl393 #(
.seq_wr1 (1'b0), // not used: seq_wr1), // input
.seq_set1 (seq_set0), // seq_set0 from channel 0 (shared in ps_pio), // input
.seq_done1 (seq_done1), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_run1 (buf_run1),
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
......@@ -1115,6 +1121,7 @@ module mcntrl393 #(
.seq_set2 (seq_set2x), // input
.seq_done2 (seq_done2), // output
.rpage_nxt_chn2 (), // not used rpage_nxt_chn2), // output
.buf_run2 (),
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
......@@ -1127,6 +1134,7 @@ module mcntrl393 #(
.seq_set3 (seq_set3x), // input
.seq_done3 (seq_done3), // output
.rpage_nxt_chn3 (rpage_nxt_chn3), // output
.buf_run3 (),
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
......@@ -1138,6 +1146,7 @@ module mcntrl393 #(
.seq_set4 (seq_set4x), // input
.seq_done4 (seq_done4), // output
.rpage_nxt_chn4 (rpage_nxt_chn4), // output
.buf_run4 (),
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
......
......@@ -57,30 +57,30 @@ module mcntrl_ps_pio#(
output reg need_rq0,
input channel_pgm_en0,
output [9:0] seq_data0, // only address
// output seq_wr0, // never generated
output seq_set0,
input seq_done0,
input buf_wr_chn0,
input buf_wpage_nxt_chn0,
// input buf_waddr_rst_chn0,
input buf_run0, // @ negedge, use to force page nimber in the buffer (use fifo)
input [63:0] buf_wdata_chn0,
// write port 1
output reg want_rq1,
output reg need_rq1,
input channel_pgm_en1,
// output [9:0] seq_data1, // only address (with seq_set) connect externally to seq_data0
// output seq_wr1, // never generated
// output seq_set1, // connect externally to seq_set0
input seq_done1,
input rpage_nxt_chn1,
input buf_run1, // @ posedge, use to force page nimber in the buffer (use fifo)
input buf_rd_chn1,
// input buf_raddr_rst_chn1,
output [63:0] buf_rdata_chn1
);
localparam CMD_WIDTH=14;
localparam CMD_WIDTH=15;
localparam CMD_FIFO_DEPTH=4;
localparam PAGE_FIFO_DEPTH = 4;// fifo depth to hold page numbers for channels (2 bits should be OK now)
localparam PAGE_CNTR_BITS = 4;
wire channel_pgm_en=channel_pgm_en0 || channel_pgm_en1;
wire seq_done= seq_done0 || seq_done1;
reg [PAGE_CNTR_BITS-1:0] pending_pages;
wire [4:0] cmd_a; // just to compare
......@@ -99,30 +99,52 @@ module mcntrl_ps_pio#(
reg [1:0] en_reset;//
wire chn_rst = ~en_reset[0]; // resets command, including fifo;
wire chn_en = &en_reset[1]; // enable requests by channle (continue ones in progress)
reg mem_run; // sequencer pgm granted and set, waiting/executing memory transfer to/from buffur 0/1
// reg mem_run; // sequencer pgm granted and set, waiting/executing memory transfer to/from buffur 0/1
wire busy;
wire short_busy; // does not include memory transaction
wire start;
reg [1:0] page;
//reg [1:0] page;
reg [1:0] page_neg;
reg [1:0] cmd_set_d;
reg cmd_set_d_neg;
// reg chn_run; // running memory access to channel 0/1
// command bit fields
wire [9:0] cmd_seq_a= cmd_out[9:0];
wire [1:0] cmd_page= cmd_out[11:10];
wire cmd_need= cmd_out[12];
wire cmd_chn= cmd_out[13];
wire cmd_wait= cmd_out[14]; // wait cmd finished before proceeding
reg cmd_set;
reg cmd_wait_r;
reg channel_pgm_en0_neg;
wire [1:0] page_out_chn0;
wire [1:0] page_out_chn1;
reg nreset_page_fifo;
reg nreset_page_fifo_neg;
// wire page_fifo0_nempty_neg;
// wire page_fifo1_nempty;
// reg page_fifo0_nempty;
assign busy= want_rq0 || need_rq0 ||want_rq1 || need_rq1 || mem_run;
assign start= chn_en && !busy && cmd_nempty;
assign short_busy= want_rq0 || need_rq0 ||want_rq1 || need_rq1 || cmd_set; // cmd_set - advance FIFO
assign busy= short_busy || (pending_pages != 0); // mem_run;
assign start= chn_en && !short_busy && cmd_nempty && ((pending_pages == 0) || !cmd_wait_r); //(!mem_run || !cmd_wait_r); // do not wait memory transaction if wait
assign seq_data0= cmd_seq_a;
assign seq_set0=cmd_set;
assign status_data= {cmd_half_full,cmd_nempty | busy};
assign set_cmd_w = cmd_we && (cmd_a== MCNTRL_PS_CMD);
assign set_status_w = cmd_we && (cmd_a== MCNTRL_PS_STATUS_CNTRL);
assign set_en_rst = cmd_we && (cmd_a== MCNTRL_PS_EN_RST);
//PAGE_CNTR_BITS
always @ (posedge rst or posedge mclk) begin
if (rst) pending_pages <= 0;
else if (chn_rst) pending_pages <= 0;
else if ( cmd_set && !seq_done) pending_pages <= pending_pages + 1;
else if (!cmd_set && seq_done) pending_pages <= pending_pages - 1;
if (rst) nreset_page_fifo <= 0;
else nreset_page_fifo <= cmd_nempty | busy;
if (rst) cmd_wait_r <= 0;
else if (channel_pgm_en) cmd_wait_r <= cmd_wait;
if (rst) en_reset <= 0;
else if (set_en_rst) en_reset <= cmd_data[1:0];
......@@ -143,27 +165,28 @@ module mcntrl_ps_pio#(
need_rq1 <= cmd_chn && cmd_need;
end
if (rst) mem_run <=0;
else if (chn_rst || seq_done) mem_run <=0;
else if (channel_pgm_en) mem_run <=1;
// if (rst) mem_run <=0;
// else if (chn_rst || seq_done) mem_run <=0;
// else if (channel_pgm_en) mem_run <=1;
if (rst) cmd_set <= 0;
else if (chn_rst) cmd_set <= 0;
else cmd_set <= channel_pgm_en;
// if (rst) chn_run <= 0;
// else if (cmd_set) chn_run <= cmd_chn;
if (rst) page <= 0;
else if (cmd_set) page <= cmd_page;
if (rst) cmd_set_d <= 0;
else cmd_set_d <= {cmd_set_d[0],cmd_set};
else cmd_set_d <= {cmd_set_d[0],cmd_set& ~cmd_chn}; // only for channel0 (memory read)
// if (rst) page_fifo0_nempty <= 0;
// else page_fifo0_nempty <=page_fifo0_nempty_neg;
end
always @ (negedge mclk) begin
page_neg <= page;
cmd_set_d_neg <= cmd_set_d[1];
page_neg <= cmd_page; // page;
// wpage_set_chn0_neg <= cmd_set_d[1];
nreset_page_fifo_neg <= nreset_page_fifo;
channel_pgm_en0_neg <= channel_pgm_en0;
end
cmd_deser #(
......@@ -228,8 +251,8 @@ fifo_same_clock #(
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.wpage_in (page_neg), // input[1:0]
.wpage_set (cmd_set_d_neg), // input
.wpage_in (page_out_chn0), // page_neg), // input[1:0]
.wpage_set (buf_run0), //wpage_set_chn0_neg), // input
.page_next (buf_wpage_nxt_chn0), // input
.page (), // output[1:0]
.we (buf_wr_chn0), // input
......@@ -243,13 +266,42 @@ fifo_same_clock #(
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (page), // input[1:0]
.rpage_set (cmd_set_d[0]), // input
.rpage_in (page_out_chn1), //page), // input[1:0]
.rpage_set (buf_run1), // rpage_set_chn1), // input
.page_next (rpage_nxt_chn1), // input
.page (), // output[1:0]
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
fifo_same_clock #(
.DATA_WIDTH(2),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo0_i (
.rst (rst),
.clk (!mclk), // negedge
.sync_rst (!nreset_page_fifo_neg), // synchronously reset fifo;
.we (channel_pgm_en0_neg),
.re (buf_run0),
.data_in (page_neg),
.data_out (page_out_chn0),
.nempty (), //page_fifo0_nempty_neg),
.half_full ()
);
fifo_same_clock #(
.DATA_WIDTH(2),
.DATA_DEPTH(PAGE_FIFO_DEPTH)
) page_fifo1_i (
.rst (rst),
.clk (mclk), // posedge
.sync_rst (!nreset_page_fifo), // synchronously reset fifo;
.we (channel_pgm_en1),
.re (buf_run1),
.data_in (cmd_page), //page),
.data_out (page_out_chn1),
.nempty (), //page_fifo1_nempty),
.half_full ()
);
endmodule
......
......@@ -164,6 +164,7 @@ module memctrl16 #(
input seq_set0, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done0, // sequencer finished executing sequence for this channel
output rpage_nxt_chn0,
output buf_run0, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn0
output buf_wr_chn0, // @ negedge mclk
output buf_wpage_nxt_chn0, // @ negedge mclk
......@@ -184,6 +185,7 @@ module memctrl16 #(
input seq_set1, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done1, // sequencer finished executing sequence for this channel
output rpage_nxt_chn1,
output buf_run1, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn1
output buf_wr_chn1, // @ negedge mclk
output buf_wpage_nxt_chn1,// @ negedge mclk
......@@ -204,6 +206,7 @@ module memctrl16 #(
input seq_set2, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done2, // sequencer finished executing sequence for this channel
output rpage_nxt_chn2,
output buf_run2, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn2
output buf_wr_chn2,
output buf_wpage_nxt_chn2,
......@@ -224,6 +227,7 @@ module memctrl16 #(
input seq_set3, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done3, // sequencer finished executing sequence for this channel
output rpage_nxt_chn3,
output buf_run3, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn3
output buf_wr_chn3,
output buf_wpage_nxt_chn3,
......@@ -244,6 +248,7 @@ module memctrl16 #(
input seq_set4, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done4, // sequencer finished executing sequence for this channel
output rpage_nxt_chn4,
output buf_run4, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn4
output buf_wr_chn4, // @ negedge mclk
output buf_wpage_nxt_chn4, // @ negedge mclk
......@@ -264,6 +269,7 @@ module memctrl16 #(
input seq_set5, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done5, // sequencer finished executing sequence for this channel
output rpage_nxt_chn5,
output buf_run5, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn5
output buf_wr_chn5, // @ negedge mclk
output buf_wpage_nxt_chn5, // @ negedge mclk
......@@ -284,6 +290,7 @@ module memctrl16 #(
input seq_set6, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done6, // sequencer finished executing sequence for this channel
output rpage_nxt_chn6,
output buf_run6, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn6
output buf_wr_chn6, // @ negedge mclk
output buf_wpage_nxt_chn6, // @ negedge mclk
......@@ -304,6 +311,7 @@ module memctrl16 #(
input seq_set7, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done7, // sequencer finished executing sequence for this channel
output rpage_nxt_chn7,
output buf_run7, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn7
output buf_wr_chn7, // @ negedge mclk
output buf_wpage_nxt_chn7, // @ negedge mclk
......@@ -324,6 +332,7 @@ module memctrl16 #(
input seq_set8, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done8, // sequencer finished executing sequence for this channel
output rpage_nxt_chn8,
output buf_run8, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn8
output buf_wr_chn8, // @ negedge mclk
output buf_wpage_nxt_chn8, // @ negedge mclk
......@@ -344,6 +353,7 @@ module memctrl16 #(
input seq_set9, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done9, // sequencer finished executing sequence for this channel
output rpage_nxt_chn9,
output buf_run9, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn9
output buf_wr_chn9, // @ negedge mclk
output buf_wpage_nxt_chn9, // @ negedge mclk
......@@ -364,6 +374,7 @@ module memctrl16 #(
input seq_set10, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done10, // sequencer finished executing sequence for this channel
output rpage_nxt_chn10,
output buf_run10, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn10
output buf_wr_chn10, // @ negedge mclk
output buf_wpage_nxt_chn10, // @ negedge mclk
......@@ -384,6 +395,7 @@ module memctrl16 #(
input seq_set11, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done11, // sequencer finished executing sequence for this channel
output rpage_nxt_chn11,
output buf_run11, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn11
output buf_wr_chn11, // @ negedge mclk
output buf_wpage_nxt_chn11, // @ negedge mclk
......@@ -404,6 +416,7 @@ module memctrl16 #(
input seq_set12, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done12, // sequencer finished executing sequence for this channel
output rpage_nxt_chn12,
output buf_run12, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn12
output buf_wr_chn12, // @ negedge mclk
output buf_wpage_nxt_chn12, // @ negedge mclk
......@@ -424,6 +437,7 @@ module memctrl16 #(
input seq_set13, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done13, // sequencer finished executing sequence for this channel
output rpage_nxt_chn13,
output buf_run13, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn13
output buf_wr_chn13, // @ negedge mclk
output buf_wpage_nxt_chn13, // @ negedge mclk
......@@ -444,6 +458,7 @@ module memctrl16 #(
input seq_set14, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done14, // sequencer finished executing sequence for this channel
output rpage_nxt_chn14,
output buf_run14, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn14
output buf_wr_chn14, // @ negedge mclk
output buf_wpage_nxt_chn14, // @ negedge mclk
......@@ -464,6 +479,7 @@ module memctrl16 #(
input seq_set15, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done15, // sequencer finished executing sequence for this channel
output rpage_nxt_chn15,
output buf_run15, // external buffer run (may be used to force page) @posedge for write memory write channels, @negedge for read
`ifdef def_read_mem_chn15
output buf_wr_chn15, // @ negedge mclk
output buf_wpage_nxt_chn15, // @ negedge mclk
......@@ -510,13 +526,15 @@ wire rst=rst_in; // TODO: decide where toi generate
wire ext_buf_rpage_nxt;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn;
wire ext_buf_rrefresh;
wire ext_buf_rrefresh;
wire ext_buf_rrun; // run read sequence (to be used with external buffer to set initial address
reg [63:0] ext_buf_rdata;
wire ext_buf_wr;
wire ext_buf_wpage_nxt;
// wire [6:0] ext_buf_waddr;
wire [3:0] ext_buf_wchn;
wire ext_buf_wrefresh;
wire ext_buf_wrun; // @negedge,first cycle of sequencer run matching write delay
wire [63:0] ext_buf_wdata;
wire [15:0] want_rq; // both want_rq and need_rq should go inactive after being granted
......@@ -916,222 +934,288 @@ end
// .ext_buf_raddr (ext_buf_raddr), // output[6:0]
.ext_buf_rchn (ext_buf_rchn), // output[3:0]
.ext_buf_rrefresh(ext_buf_rrefresh), // output
.ext_buf_rrun (ext_buf_rrun), // run read sequence (to be used with external buffer to set initial address
.ext_buf_rdata (ext_buf_rdata), // input[63:0]
.ext_buf_wr (ext_buf_wr), // output
.ext_buf_wpage_nxt (ext_buf_wpage_nxt), // output[6:0]
// .ext_buf_waddr (ext_buf_waddr), // output[6:0]
.ext_buf_wchn (ext_buf_wchn), // output[3:0]
.ext_buf_wrefresh(ext_buf_wrefresh), // output
.ext_buf_wrefresh(ext_buf_wrefresh), // output
.ext_buf_wrun (ext_buf_wrun), // @negedge,first cycle of sequencer run matching write delay
.ext_buf_wdata (ext_buf_wdata), // output[63:0]
.tmp_debug (tmp_debug) // output[11:0]
);
// Registering existing channel buffers I/Os
`ifdef def_enable_mem_chn0
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done0),.rpage_nxt(rpage_nxt_chn0));
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done0),.rpage_nxt(rpage_nxt_chn0));
`ifdef def_read_mem_chn0
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn0),.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_wdata_chn(buf_wdata_chn0));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn0),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_run(buf_run0),.buf_wdata_chn(buf_wdata_chn0));
`else
wire [63:0] ext_buf_rdata0;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata0),.buf_rd_chn(buf_rd_chn0),.buf_rdata_chn (buf_rdata_chn0));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata0),.buf_rd_chn(buf_rd_chn0),.buf_run(buf_run0),.buf_rdata_chn(buf_rdata_chn0));
`endif
`endif
`ifdef def_enable_mem_chn1
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done1),.rpage_nxt(rpage_nxt_chn1));
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done1),.rpage_nxt(rpage_nxt_chn1));
`ifdef def_read_mem_chn1
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn1),.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_wdata_chn(buf_wdata_chn1));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn1),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_run(buf_run1),.buf_wdata_chn(buf_wdata_chn1));
`else
wire [63:0] ext_buf_rdata1;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata1),.buf_rd_chn(buf_rd_chn1),.buf_rdata_chn(buf_rdata_chn1));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata1),.buf_rd_chn(buf_rd_chn1),.buf_run(buf_run1),.buf_rdata_chn(buf_rdata_chn1));
`endif
`endif
`ifdef def_enable_mem_chn2
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done2),.rpage_nxt(rpage_nxt_chn2));
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done2),.rpage_nxt(rpage_nxt_chn2));
`ifdef def_read_mem_chn2
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn2),.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_wdata_chn(buf_wdata_chn2));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn2),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_run(buf_run2),.buf_wdata_chn(buf_wdata_chn2));
`else
wire [63:0] ext_buf_rdata2;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata2),.buf_rd_chn(buf_rd_chn2),.buf_rdata_chn(buf_rdata_chn2));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata2),.buf_rd_chn(buf_rd_chn2),.buf_run(buf_run2),.buf_rdata_chn(buf_rdata_chn2));
`endif
`endif
`ifdef def_enable_mem_chn3
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done3),.rpage_nxt(rpage_nxt_chn3));
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done3),.rpage_nxt(rpage_nxt_chn3));
`ifdef def_read_mem_chn3
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn3),.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_wdata_chn(buf_wdata_chn3));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn3),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_run(buf_run3),.buf_wdata_chn(buf_wdata_chn3));
`else
wire [63:0] ext_buf_rdata3;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata3),.buf_rd_chn(buf_rd_chn3),.buf_rdata_chn(buf_rdata_chn3));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata3),.buf_rd_chn(buf_rd_chn3),.buf_run(buf_run3),.buf_rdata_chn(buf_rdata_chn3));
`endif
`endif
`ifdef def_enable_mem_chn4
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done4),.rpage_nxt(rpage_nxt_chn4));
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done4),.rpage_nxt(rpage_nxt_chn4));
`ifdef def_read_mem_chn4
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn4),.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_wdata_chn(buf_wdata_chn4));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn4),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_run(buf_run4),.buf_wdata_chn(buf_wdata_chn4));
`else
wire [63:0] ext_buf_rdata4;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata4),.buf_rd_chn(buf_rd_chn4),.buf_rdata_chn(buf_rdata_chn4));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata4),.buf_rd_chn(buf_rd_chn4),.buf_run(buf_run4),.buf_rdata_chn(buf_rdata_chn4));
`endif
`endif
`ifdef def_enable_mem_chn5
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done5),.rpage_nxt(rpage_nxt_chn5));
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done5),.rpage_nxt(rpage_nxt_chn5));
`ifdef def_read_mem_chn5
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn5),.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_wdata_chn(buf_wdata_chn5));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn5),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_run(buf_run5),.buf_wdata_chn(buf_wdata_chn5));
`else
wire [63:0] ext_buf_rdata5;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata5),.buf_rd_chn(buf_rd_chn5),.buf_rdata_chn(buf_rdata_chn5));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata5),.buf_rd_chn(buf_rd_chn5),.buf_run(buf_run5),.buf_rdata_chn(buf_rdata_chn5));
`endif
`endif
`ifdef def_enable_mem_chn6
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done6),.rpage_nxt(rpage_nxt_chn6));
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done6),.rpage_nxt(rpage_nxt_chn6));
`ifdef def_read_mem_chn6
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn6),.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_wdata_chn(buf_wdata_chn6));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn6),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_run(buf_run6),.buf_wdata_chn(buf_wdata_chn6));
`else
wire [63:0] ext_buf_rdata6;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata6),.buf_rd_chn(buf_rd_chn6),.buf_rdata_chn(buf_rdata_chn6));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata6),.buf_rd_chn(buf_rd_chn6),.buf_run(buf_run6),.buf_rdata_chn(buf_rdata_chn6));
`endif
`endif
`ifdef def_enable_mem_chn7
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done7),.rpage_nxt(rpage_nxt_chn7));
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done7),.rpage_nxt(rpage_nxt_chn7));
`ifdef def_read_mem_chn7
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn7),.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_wdata_chn(buf_wdata_chn7));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn7),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_run(buf_run7),.buf_wdata_chn(buf_wdata_chn7));
`else
wire [63:0] ext_buf_rdata7;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata7),.buf_rd_chn(buf_rd_chn7),.buf_rdata_chn(buf_rdata_chn7));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata7),.buf_rd_chn(buf_rd_chn7),.buf_run(buf_run7),.buf_rdata_chn(buf_rdata_chn7));
`endif
`endif
`ifdef def_enable_mem_chn8
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done8),.rpage_nxt(rpage_nxt_chn8));
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done8),.rpage_nxt(rpage_nxt_chn8));
`ifdef def_read_mem_chn8
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn8),.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_wdata_chn(buf_wdata_chn8));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn8),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_run(buf_run8),.buf_wdata_chn(buf_wdata_chn8));
`else
wire [63:0] ext_buf_rdata8;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata8),.buf_rd_chn(buf_rd_chn8),.buf_rdata_chn(buf_rdata_chn8));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata8),.buf_rd_chn(buf_rd_chn8),.buf_run(buf_run8),.buf_rdata_chn(buf_rdata_chn8));
`endif
`endif
`ifdef def_enable_mem_chn9
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done9),.rpage_nxt(rpage_nxt_chn9));
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done9),.rpage_nxt(rpage_nxt_chn9));
`ifdef def_read_mem_chn9
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn9),.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_wdata_chn(buf_wdata_chn9));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn9),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_run(buf_run9),.buf_wdata_chn(buf_wdata_chn9));
`else
wire [63:0] ext_buf_rdata9;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata9),.buf_rd_chn(buf_rd_chn9),.buf_rdata_chn(buf_rdata_chn9));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata9),.buf_rd_chn(buf_rd_chn9),.buf_run(buf_run9),.buf_rdata_chn(buf_rdata_chn9));
`endif
`endif
`ifdef def_enable_mem_chn10
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done10),.rpage_nxt(rpage_nxt_chn10));
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),
.buf_done(seq_done10),.rpage_nxt(rpage_nxt_chn10));
`ifdef def_read_mem_chn10
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn10),.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_wdata_chn(buf_wdata_chn10));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),
.ext_buf_wpage_nxt(ext_buf_wpage_nxt),.ext_buf_wchn(ext_buf_wchn), .ext_buf_wrefresh(ext_buf_wrefresh),
.ext_buf_wrun(ext_buf_wrun),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn10),
.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_run(buf_run10),.buf_wdata_chn(buf_wdata_chn10));
`else
wire [63:0] ext_buf_rdata10;
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),.ext_buf_rdata(ext_buf_rdata10),.buf_rd_chn(buf_rd_chn10),.buf_rdata_chn(buf_rdata_chn10));
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),
.ext_buf_rd(ext_buf_rd),.ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh), .ext_buf_rrun(ext_buf_rrun),
.ext_buf_rdata(ext_buf_rdata10),.buf_rd_chn(buf_rd_chn10),.buf_run(buf_run10),.buf_rdata_chn(buf_rdata_chn10));
`endif
`endif
`ifdef def_enable_mem_chn11
mcont_common_chnbuf_reg #( .CHN_NUMBER(11)) mcont_common_chnbuf_reg11_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn), .ext_buf_rrefresh(ext_buf_rrefresh),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done11),.rpage_nxt(rpage_nxt_chn11));