changed user name to full name

.project

@@ -62,52 +62,52 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160504203656004.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160504204346976.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160504203656004.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160504203656004.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
@@ -127,7 +127,7 @@
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20160504203656004.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

compressor_jp/bit_stuffer_27_32.v

 /*******************************************************************************
  * Module: bit_stuffer_27_32
  * Date:2015-10-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words
  *
  * Copyright (c) 2015 Elphel, Inc .

compressor_jp/bit_stuffer_escape.v

 /*******************************************************************************
  * Module: bit_stuffer_escape
  * Date:2015-10-24  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Escapes each 0xff with 0x00, 32-bit input and output
  *
  * Copyright (c) 2015 Elphel, Inc .

compressor_jp/bit_stuffer_metadata.v

 /*******************************************************************************
  * Module: bit_stuffer_metadata
  * Date:2015-10-25  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: 
  *
  * Copyright (c) 2015 Elphel, Inc .

compressor_jp/huffman_merge_code_literal.v

 /*******************************************************************************
  * Module: huffman_merge_code_literal
  * Date:2015-10-22  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data,
  * align result to MSB : {huffman,literal, {n{1'b0}}
  *

compressor_jp/huffman_stuffer_meta.v

 /*******************************************************************************
  * Module: huffman_stuffer_meta
  * Date:2015-10-26  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Huffman encoder, bit stuffer, inser meta-data
  * "New" part of the JPEG/JP4 comressor that used double frequency clock
  *

fpga_version.vh

@@ -32,7 +32,8 @@
  * with at least one of the Free Software programs.
  *******************************************************************************/
  
-      parameter FPGA_VERSION =          32'h03930087;      // Synchronizing i2c sequencer frame number with that of a command sequencer
+        parameter FPGA_VERSION =          32'h03930087;    // Fixed default 90% quantization table
+//      parameter FPGA_VERSION =          32'h03930087;    // Synchronizing i2c sequencer frame number with that of a command sequencer
 //      parameter FPGA_VERSION =          32'h03930086;    // Adding byte-wide JTAG read to speed-up 10359 load
 //      parameter FPGA_VERSION =          32'h03930085;    // Adding software control for i2c pins when sequencer is stopped, timing matched
 //      parameter FPGA_VERSION =          32'h03930084;    // Back to iserdes, inverting xfpgatdo - met

helpers/quantization_100.dat

@@ -16,21 +16,20 @@
    ffff   ffff   ffff   ffff   ffff   ffff   ffff   ffff
    ffff   ffff   ffff   ffff   ffff   ffff   ffff   ffff
 
-   5550   8000   8000   5550   8000   8000   5550   5550
-   5550   5550   4000   5550   5550   4000   3330   2000
-   3330   3330   4000   4000   3330   19a0   2490   2490
-   2ab0   2000   1550   19a0   1550   1550   1740   19a0
-   1740   1740   13b0   1250    e40   1000   13b0   1250
-    f10   1250   1740   1740   1000    ba0   1000    f10
-    d80    cd0    c30    c30    c30   1550   1110    b20
-    ab0    ba0    cd0    ab0    e40    cd0    c30    cd0
-
-   5550   4000   4000   3330   4000   3330   1c70   3330
-   3330   1c70    cd0   13b0   1740   13b0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+   5555   8000   8000   5555   3333   2000   199a   1555   
+   8000   8000   5555   4000   3333   1555   1555   1746   
+   5555   5555   5555   3333   2000   1746   1249   1746   
+   5555   5555   4000   2aab   199a   0f0f   1000   1555   
+   4000   4000   2492   1746   1249   0ba3   0c31   1111   
+   3333   2492   1746   13b1   1000   0c31   0b21   0e39   
+   199a   13b1   1000   0f0f   0c31   0aab   0aab   0ccd   
+   1249   0e39   0d79   0ccd   0ba3   0ccd   0c31   0ccd   
 
+   5555   4000   3333   1c72   0ccd   0ccd   0ccd   0ccd   
+   4000   4000   3333   13b1   0ccd   0ccd   0ccd   0ccd   
+   3333   3333   1746   0ccd   0ccd   0ccd   0ccd   0ccd   
+   1c72   13b1   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   

helpers/quantization_100.dat.vh

@@ -6,11 +6,11 @@
 , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
 , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
 , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
-, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550)
-, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330)
-, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740)
-, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80)
-, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550)
-, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
-, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
-, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
+, .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555)
+, .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555)
+, .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000)
+, .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A)
+, .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555)
+, .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333)
+, .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
+, .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)

includes/quantization_100.dat.vh

@@ -6,11 +6,11 @@
 , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
 , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
 , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
-, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550)
-, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330)
-, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740)
-, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80)
-, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550)
-, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
-, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
-, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
+, .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555)
+, .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555)
+, .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000)
+, .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A)
+, .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555)
+, .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333)
+, .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
+, .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)

includes/tasks_tests_memory.vh

 /*******************************************************************************
  * Module: tasks_tests_memory
  * Date:2015-08-01  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Top-level tasks for testing memory subsystem functionality
  *
  * Copyright (c) 2015 Elphel, Inc .

input_data/quantization_100.dat

@@ -16,21 +16,20 @@
    ffff   ffff   ffff   ffff   ffff   ffff   ffff   ffff
    ffff   ffff   ffff   ffff   ffff   ffff   ffff   ffff
 
-   5550   8000   8000   5550   8000   8000   5550   5550
-   5550   5550   4000   5550   5550   4000   3330   2000
-   3330   3330   4000   4000   3330   19a0   2490   2490
-   2ab0   2000   1550   19a0   1550   1550   1740   19a0
-   1740   1740   13b0   1250    e40   1000   13b0   1250
-    f10   1250   1740   1740   1000    ba0   1000    f10
-    d80    cd0    c30    c30    c30   1550   1110    b20
-    ab0    ba0    cd0    ab0    e40    cd0    c30    cd0
-
-   5550   4000   4000   3330   4000   3330   1c70   3330
-   3330   1c70    cd0   13b0   1740   13b0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
-    cd0    cd0    cd0    cd0    cd0    cd0    cd0    cd0
+   5555   8000   8000   5555   3333   2000   199a   1555   
+   8000   8000   5555   4000   3333   1555   1555   1746   
+   5555   5555   5555   3333   2000   1746   1249   1746   
+   5555   5555   4000   2aab   199a   0f0f   1000   1555   
+   4000   4000   2492   1746   1249   0ba3   0c31   1111   
+   3333   2492   1746   13b1   1000   0c31   0b21   0e39   
+   199a   13b1   1000   0f0f   0c31   0aab   0aab   0ccd   
+   1249   0e39   0d79   0ccd   0ba3   0ccd   0c31   0ccd   
 
+   5555   4000   3333   1c72   0ccd   0ccd   0ccd   0ccd   
+   4000   4000   3333   13b1   0ccd   0ccd   0ccd   0ccd   
+   3333   3333   1746   0ccd   0ccd   0ccd   0ccd   0ccd   
+   1c72   13b1   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   
+   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   0ccd   

sensor/sens_10398.v

 /*******************************************************************************
  * Module: sens_10398
  * Date:2015-10-15  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Top level module for the 10398 SFE (with MT9F002 sensor)
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sens_hispi12l4.v

 /*******************************************************************************
  * Module: sens_hispi12l4
  * Date:2015-10-13  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sens_hispi_clock.v

 /*******************************************************************************
  * Module: sens_hispi_clock
  * Date:2015-10-13  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Recover iclk/iclk2x from the HiSPi differntial clock
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sens_hispi_din.v

 /*******************************************************************************
  * Module: sens_hispi_din
  * Date:2015-10-13  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Input differential receivers for HiSPi lanes
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sens_hispi_fifo.v

 /*******************************************************************************
  * Module: sens_hispi_fifo
  * Date:2015-10-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: cross-clock FIFO with special handling of 'run' output
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sens_hispi_lane.v

 /*******************************************************************************
  * Module: sens_hispi_lane
  * Date:2015-10-13  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode a single lane of the HiSPi data assuming packetized-SP protocol
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sensor_i2c_prot.v

 /*******************************************************************************
  * Module: sensor_i2c_prot
  * Date:2015-10-05  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Generate i2c R/W sequence from a 32-bit word and LUT
  *
  * Copyright (c) 2015 Elphel, Inc .

sensor/sensor_i2c_scl_sda.v

 /*******************************************************************************
  * Module: sensor_i2c_scl_sda
  * Date:2015-10-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Generation of i2c signals
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/par12_hispi_psp4l.v

 /*******************************************************************************
  * Module: par12_hispi_psp4l
  * Date:2015-10-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/sim_clk_div.v

 /*******************************************************************************
  * Module: sim_clk_div
  * Date:2015-10-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Divide clock frequency by integer number
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/sim_frac_clk_delay.v

 /*******************************************************************************
  * Module: sim_frac_clk_delay
  * Date:2015-10-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Delay clock-synchronous signal by fractional number of periods
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/simul_clk.v

 /*******************************************************************************
  * Module: simul_clk
  * Date:2015-07-29  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Generate clocks for simulation
  *
  * Copyright (c) 2015 Elphel, Inc.

simulation_modules/simul_clk_div_mult.v

 /*******************************************************************************
  * Module: simul_clk_div_mult
  * Date:2015-10-12  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation clock rational multiplier
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/simul_clk_mult.v

 /*******************************************************************************
  * Module: simul_clk_mult
  * Date:2015-10-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Clock multiplier
  *
  * Copyright (c) 2015 Elphel, Inc .

simulation_modules/simul_clk_mult_div.v

 /*******************************************************************************
  * Module: simul_clk_mult_div
  * Date:2015-10-12  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation clock rational multiplier
  *
  * Copyright (c) 2015 Elphel, Inc .

unisims_extra/IBUFG.v

 /*******************************************************************************
  * Module: IBUFG
  * Date:2015-11-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Module name "known" to synthesis, but missing in unisims
  *
  * Copyright (c) 2015 Elphel, Inc .

unisims_extra/IBUFGDS.v

 /*******************************************************************************
  * Module: IBUFGDS
  * Date:2015-11-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Module name "known" to synthesis, but missing in unisims
  *
  * Copyright (c) 2015 Elphel, Inc .

util_modules/debug_master.v

 /*******************************************************************************
  * Module: debug_master
  * Date:2015-09-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Debug master module to send/receive serial debug data
  *
  * Copyright (c) 2015 Elphel, Inc .

util_modules/debug_slave.v

 /*******************************************************************************
  * Module: debug_slave
  * Date:2015-09-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Send/receive debug data over the serial ring
  *
  * Copyright (c) 2015 Elphel, Inc .

util_modules/fifo_sameclock_control.v

 /*******************************************************************************
  * Module: fifo_sameclock_control
  * Date:2016-01-20  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: BRAM-based fifo control, uses BARM output registers
  *
  * Copyright (c) 2016 Elphel, Inc .

util_modules/frame_num_sync.v

 /*******************************************************************************
  * Module: frame_num_sync
  * Date:2016-04-28  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Propagating frame number from acquisition to compressor output
  *
  * Copyright (c) 2016 Elphel, Inc .

wrap/obufds.v

 /*******************************************************************************
  * Module: obufds
  * Date:2015-10-15  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Wrapper for OBUFDS primitive
  *
  * Copyright (c) 2015 Elphel, Inc .

wrap/select_clk_buf.v

 /*******************************************************************************
  * Module: select_clk_buf
  * Date:2015-11-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Select one of the clock buffers primitives by parameter
  *
  * Copyright (c) 2015 Elphel, Inc .

x393_sata/ahci/ahci_ctrl_stat.v

 /*******************************************************************************
  * Module: ahci_ctrl_stat
  * Date:2016-01-12  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Copy of significant register fields, updating them in
  * axi_ahci_regs registers (software accessible)
  *

x393_sata/ahci/ahci_dma_rd_stuff.v

 /*******************************************************************************
  * Module: ahci_dma_rd_stuff
  * Date:2016-01-01  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Stuff DWORD data with missing words into continuous 32-bit data
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/ahci/ahci_fis_transmit.v

 /*******************************************************************************
  * Module: ahci_fis_transmit
  * Date:2016-01-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Fetches commands, command tables, creates/sends FIS
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/ahci/ahci_fsm.v

 /*******************************************************************************
  * Module: ahci_fsm
  * Date:2016-01-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: AHCI host+port0 state machine
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/ahci/ahci_sata_layers.v

 /*******************************************************************************
  * Module: ahci_sata_layers
  * Date:2016-01-19  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Link and PHY SATA layers
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/ahci/axi_hp_abort.v

 /*******************************************************************************
  * Module: axi_hp_abort
  * Date:2016-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Trying to gracefully reset AXI HP after aborted transmission
  * For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
  * For write - keep track aof all what was sent so far, assuming aw is always ahead of w

x393_sata/ahci/freq_meter.v

 /*******************************************************************************
  * Module: freq_meter
  * Date:2016-02-13  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Measure device clock frequency to set the local clock
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/host/drp_other_registers.v

 /*******************************************************************************
  * Module: drp_other_registers
  * Date:2016-03-13
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Additional registers controlled/read back over DRP
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/host/elastic1632.v

 /*******************************************************************************
  * Module: elastic1632
  * Date:2016-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Elastic buffer with 16-bit data input and 32-bit output
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_sata/wrapper/clock_inverter.v

 /*******************************************************************************
  * Module: clock_inverter
  * Date:2016-02-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Glitch-free clock controlled inverter
  *
  * Copyright (c) 2016 Elphel, Inc .

x393_testbench03.tf

@@ -1226,13 +1226,13 @@ assign #10 gpio_pins[9] = gpio_pins[8];
            'h10000 >> 5); // input [26:0] afi_cmprs3_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
         */
         'h10000000 >> 5,  // input [26:0] afi_cmprs0_sa;   // input [26:0] sa;   // start address in 32-byte chunks
-             'h800 >> 5,  // input [26:0] afi_cmprs0_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
+             'h5c0 >> 5,  // 'h800 >> 5,  // input [26:0] afi_cmprs0_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
         'h10010000 >> 5,  // input [26:0] afi_cmprs1_sa;   // input [26:0] sa;   // start address in 32-byte chunks
-             'h400 >> 5,  // input [26:0] afi_cmprs1_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
+             'h2e0 >> 5,  // h400 >> 5,  // input [26:0] afi_cmprs1_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
         'h10020000 >> 5,  // input [26:0] afi_cmprs2_sa;   // input [26:0] sa;   // start address in 32-byte chunks
-             'h200 >> 5,  // input [26:0] afi_cmprs2_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
+             'h280 >> 5,  // 'h200 >> 5,  // input [26:0] afi_cmprs2_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
         'h10030000 >> 5,  // input [26:0] afi_cmprs3_sa;   // input [26:0] sa;   // start address in 32-byte chunks
-             'h100 >> 5); // input [26:0] afi_cmprs3_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
+             'h1e0 >> 5); // 'h100 >> 5); // input [26:0] afi_cmprs3_len; //  input [26:0] length;     // channel buffer length in 32-byte chunks
     camsync_setup (
         4'hf ); // sensor_mask); //
 /*
@@ -2756,7 +2756,7 @@ task setup_sensor_channel;
     
     compressor_run (num_sensor, 0); // reset compressor
     
-    simulation_datasimulation_dataspecify_window 66 36 0 0 0 3 1
+    
     
     if (cmode == CMPRS_CBIT_CMODE_JPEG18) begin
         setup_compressor_channel(
@@ -2819,7 +2819,7 @@ task setup_sensor_channel;
              (cmode == CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2)) begin
         setup_compressor_channel(
             num_sensor,              // sensor channel number (0..3)
-            0,                       // qbank;    // [6:3] quantization table page - 100% quality
+            ((num_sensor == 1) || (num_sensor == 3))?  1 : 0, // 0,          // qbank;    // [6:3] quantization table page - 100% quality
     //        1,                       // qbank;    // [6:3] quantization table page - 85%? quality
             1,                       // dc_sub;   // [8:7] subtract DC
             cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode;   //  [13:9] color mode:

x393_testbench04.sav

 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Wed May  4 20:52:00 2016
+[*] Thu May  5 06:16:12 2016
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160504133628289.fst"
-[dumpfile_mtime] "Wed May  4 20:03:27 2016"
-[dumpfile_size] 89230413
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160504231654593.fst"
+[dumpfile_mtime] "Thu May  5 05:44:01 2016"
+[dumpfile_size] 89249645
 [savefile] "/home/andrey/git/x393/x393_testbench04.sav"
 [timestart] 0
 [size] 1823 1180
 [pos] -1 -1
-*-24.733164 47500000 121282388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-24.979511 145131000 121282388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench03.
 [treeopen] x393_testbench03.simul_axi_hp_wr_i.
 [treeopen] x393_testbench03.x393_i.
@@ -18,7 +18,8 @@
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].
 [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].
-[treeopen] x393_testbench03.x393_i.sensors393_i.
+[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.
+[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
@@ -28,7 +29,7 @@
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
 [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i.
-[sst_width] 257
+[sst_width] 377
 [signals_width] 340
 [sst_expanded] 1
 [sst_vpaned_height] 575
@@ -64,7 +65,6 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.fifo
 @22
 x393_testbench03.setup_sensor_channel.num_sensor[1:0]
 x393_testbench03.setup_compressor_channel.num_sensor[1:0]
-@23
 x393_testbench03.setup_compressor_channel.qbank[31:0]
 @200
 -
@@ -140,8 +140,36 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.left
 x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.left_marg[4:0]
 x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.left_marg[4:0]
 x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.left_marg[4:0]
+@c00200
+-status
+@22
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.chunk_ptr_ra[3:0]
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.chunk_ptr_rd[25:0]
+@28
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_rq
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_start
+@1401200
+-status
+@22
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunk_ptr_rd[26:0]
+x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.chunk_ptr_rd[26:0]
 @1000200
 -all_cmprs_out
+@800200
+-sim_afi1
+@200
+-
+@23
+x393_testbench03.sim_cmprs0_addr[31:0]
+x393_testbench03.sim_cmprs0_data[63:0]
+x393_testbench03.sim_cmprs1_addr[31:0]
+x393_testbench03.sim_cmprs1_data[63:0]
+x393_testbench03.sim_cmprs2_addr[31:0]
+x393_testbench03.sim_cmprs2_data[63:0]
+x393_testbench03.sim_cmprs3_addr[31:0]
+x393_testbench03.sim_cmprs3_data[63:0]
+@1000200
+-sim_afi1
 @c00200
 -all_sensor_data
 @22