Loading .project +11 −11 Original line number Original line Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <link> <name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -127,7 +127,7 @@ <link> <link> <name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160504203656004.dcp</location> </link> </link> </linkedResources> </linkedResources> </projectDescription> </projectDescription> compressor_jp/bit_stuffer_27_32.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_27_32 * Module: bit_stuffer_27_32 * Date:2015-10-23 * Date:2015-10-23 * Author: andrey * Author: Andrey Filippov * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading compressor_jp/bit_stuffer_escape.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_escape * Module: bit_stuffer_escape * Date:2015-10-24 * Date:2015-10-24 * Author: andrey * Author: Andrey Filippov * Description: Escapes each 0xff with 0x00, 32-bit input and output * Description: Escapes each 0xff with 0x00, 32-bit input and output * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading compressor_jp/bit_stuffer_metadata.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_metadata * Module: bit_stuffer_metadata * Date:2015-10-25 * Date:2015-10-25 * Author: andrey * Author: Andrey Filippov * Description: * Description: * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading compressor_jp/huffman_merge_code_literal.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: huffman_merge_code_literal * Module: huffman_merge_code_literal * Date:2015-10-22 * Date:2015-10-22 * Author: andrey * Author: Andrey Filippov * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * align result to MSB : {huffman,literal, {n{1'b0}} * align result to MSB : {huffman,literal, {n{1'b0}} * * Loading Loading
.project +11 −11 Original line number Original line Diff line number Diff line Loading @@ -62,52 +62,52 @@ <link> <link> <name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160504204346976.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160504203656004.log</location> </link> </link> <link> <link> <name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name> Loading @@ -127,7 +127,7 @@ <link> <link> <name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name> <type>1</type> <type>1</type> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160504203656004.dcp</location> </link> </link> </linkedResources> </linkedResources> </projectDescription> </projectDescription>
compressor_jp/bit_stuffer_27_32.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_27_32 * Module: bit_stuffer_27_32 * Date:2015-10-23 * Date:2015-10-23 * Author: andrey * Author: Andrey Filippov * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading
compressor_jp/bit_stuffer_escape.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_escape * Module: bit_stuffer_escape * Date:2015-10-24 * Date:2015-10-24 * Author: andrey * Author: Andrey Filippov * Description: Escapes each 0xff with 0x00, 32-bit input and output * Description: Escapes each 0xff with 0x00, 32-bit input and output * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading
compressor_jp/bit_stuffer_metadata.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: bit_stuffer_metadata * Module: bit_stuffer_metadata * Date:2015-10-25 * Date:2015-10-25 * Author: andrey * Author: Andrey Filippov * Description: * Description: * * * Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc . Loading
compressor_jp/huffman_merge_code_literal.v +1 −1 Original line number Original line Diff line number Diff line /******************************************************************************* /******************************************************************************* * Module: huffman_merge_code_literal * Module: huffman_merge_code_literal * Date:2015-10-22 * Date:2015-10-22 * Author: andrey * Author: Andrey Filippov * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * align result to MSB : {huffman,literal, {n{1'b0}} * align result to MSB : {huffman,literal, {n{1'b0}} * * Loading