Commit 374d7837 authored by Andrey Filippov's avatar Andrey Filippov

changed user name to full name

parent 8eee7a90
...@@ -62,52 +62,52 @@ ...@@ -62,52 +62,52 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160504203656004.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160504204346976.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160504203656004.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160504203656004.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
...@@ -127,7 +127,7 @@ ...@@ -127,7 +127,7 @@
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20160504203656004.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
/******************************************************************************* /*******************************************************************************
* Module: bit_stuffer_27_32 * Module: bit_stuffer_27_32
* Date:2015-10-23 * Date:2015-10-23
* Author: andrey * Author: Andrey Filippov
* Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: bit_stuffer_escape * Module: bit_stuffer_escape
* Date:2015-10-24 * Date:2015-10-24
* Author: andrey * Author: Andrey Filippov
* Description: Escapes each 0xff with 0x00, 32-bit input and output * Description: Escapes each 0xff with 0x00, 32-bit input and output
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: bit_stuffer_metadata * Module: bit_stuffer_metadata
* Date:2015-10-25 * Date:2015-10-25
* Author: andrey * Author: Andrey Filippov
* Description: * Description:
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: huffman_merge_code_literal * Module: huffman_merge_code_literal
* Date:2015-10-22 * Date:2015-10-22
* Author: andrey * Author: Andrey Filippov
* Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data,
* align result to MSB : {huffman,literal, {n{1'b0}} * align result to MSB : {huffman,literal, {n{1'b0}}
* *
......
/******************************************************************************* /*******************************************************************************
* Module: huffman_stuffer_meta * Module: huffman_stuffer_meta
* Date:2015-10-26 * Date:2015-10-26
* Author: andrey * Author: Andrey Filippov
* Description: Huffman encoder, bit stuffer, inser meta-data * Description: Huffman encoder, bit stuffer, inser meta-data
* "New" part of the JPEG/JP4 comressor that used double frequency clock * "New" part of the JPEG/JP4 comressor that used double frequency clock
* *
......
...@@ -32,7 +32,8 @@ ...@@ -32,7 +32,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*******************************************************************************/ *******************************************************************************/
parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer parameter FPGA_VERSION = 32'h03930087; // Fixed default 90% quantization table
// parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer
// parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load // parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load
// parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched // parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched
// parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met
......
...@@ -16,21 +16,20 @@ ...@@ -16,21 +16,20 @@
ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff
ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff
5550 8000 8000 5550 8000 8000 5550 5550 5555 8000 8000 5555 3333 2000 199a 1555
5550 5550 4000 5550 5550 4000 3330 2000 8000 8000 5555 4000 3333 1555 1555 1746
3330 3330 4000 4000 3330 19a0 2490 2490 5555 5555 5555 3333 2000 1746 1249 1746
2ab0 2000 1550 19a0 1550 1550 1740 19a0 5555 5555 4000 2aab 199a 0f0f 1000 1555
1740 1740 13b0 1250 e40 1000 13b0 1250 4000 4000 2492 1746 1249 0ba3 0c31 1111
f10 1250 1740 1740 1000 ba0 1000 f10 3333 2492 1746 13b1 1000 0c31 0b21 0e39
d80 cd0 c30 c30 c30 1550 1110 b20 199a 13b1 1000 0f0f 0c31 0aab 0aab 0ccd
ab0 ba0 cd0 ab0 e40 cd0 c30 cd0 1249 0e39 0d79 0ccd 0ba3 0ccd 0c31 0ccd
5550 4000 4000 3330 4000 3330 1c70 3330
3330 1c70 cd0 13b0 1740 13b0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
5555 4000 3333 1c72 0ccd 0ccd 0ccd 0ccd
4000 4000 3333 13b1 0ccd 0ccd 0ccd 0ccd
3333 3333 1746 0ccd 0ccd 0ccd 0ccd 0ccd
1c72 13b1 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
...@@ -6,11 +6,11 @@ ...@@ -6,11 +6,11 @@
, .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550) , .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555)
, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330) , .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555)
, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740) , .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000)
, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80) , .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A)
, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550) , .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555)
, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333)
, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
...@@ -6,11 +6,11 @@ ...@@ -6,11 +6,11 @@
, .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550) , .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555)
, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330) , .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555)
, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740) , .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000)
, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80) , .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A)
, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550) , .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555)
, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333)
, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) , .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD)
/******************************************************************************* /*******************************************************************************
* Module: tasks_tests_memory * Module: tasks_tests_memory
* Date:2015-08-01 * Date:2015-08-01
* Author: andrey * Author: Andrey Filippov
* Description: Top-level tasks for testing memory subsystem functionality * Description: Top-level tasks for testing memory subsystem functionality
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
...@@ -16,21 +16,20 @@ ...@@ -16,21 +16,20 @@
ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff
ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff
5550 8000 8000 5550 8000 8000 5550 5550 5555 8000 8000 5555 3333 2000 199a 1555
5550 5550 4000 5550 5550 4000 3330 2000 8000 8000 5555 4000 3333 1555 1555 1746
3330 3330 4000 4000 3330 19a0 2490 2490 5555 5555 5555 3333 2000 1746 1249 1746
2ab0 2000 1550 19a0 1550 1550 1740 19a0 5555 5555 4000 2aab 199a 0f0f 1000 1555
1740 1740 13b0 1250 e40 1000 13b0 1250 4000 4000 2492 1746 1249 0ba3 0c31 1111
f10 1250 1740 1740 1000 ba0 1000 f10 3333 2492 1746 13b1 1000 0c31 0b21 0e39
d80 cd0 c30 c30 c30 1550 1110 b20 199a 13b1 1000 0f0f 0c31 0aab 0aab 0ccd
ab0 ba0 cd0 ab0 e40 cd0 c30 cd0 1249 0e39 0d79 0ccd 0ba3 0ccd 0c31 0ccd
5550 4000 4000 3330 4000 3330 1c70 3330
3330 1c70 cd0 13b0 1740 13b0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0
5555 4000 3333 1c72 0ccd 0ccd 0ccd 0ccd
4000 4000 3333 13b1 0ccd 0ccd 0ccd 0ccd
3333 3333 1746 0ccd 0ccd 0ccd 0ccd 0ccd
1c72 13b1 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd
/******************************************************************************* /*******************************************************************************
* Module: sens_10398 * Module: sens_10398
* Date:2015-10-15 * Date:2015-10-15
* Author: andrey * Author: Andrey Filippov
* Description: Top level module for the 10398 SFE (with MT9F002 sensor) * Description: Top level module for the 10398 SFE (with MT9F002 sensor)
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sens_hispi12l4 * Module: sens_hispi12l4
* Date:2015-10-13 * Date:2015-10-13
* Author: andrey * Author: Andrey Filippov
* Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor * Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sens_hispi_clock * Module: sens_hispi_clock
* Date:2015-10-13 * Date:2015-10-13
* Author: andrey * Author: Andrey Filippov
* Description: Recover iclk/iclk2x from the HiSPi differntial clock * Description: Recover iclk/iclk2x from the HiSPi differntial clock
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sens_hispi_din * Module: sens_hispi_din
* Date:2015-10-13 * Date:2015-10-13
* Author: andrey * Author: Andrey Filippov
* Description: Input differential receivers for HiSPi lanes * Description: Input differential receivers for HiSPi lanes
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sens_hispi_fifo * Module: sens_hispi_fifo
* Date:2015-10-14 * Date:2015-10-14
* Author: andrey * Author: Andrey Filippov
* Description: cross-clock FIFO with special handling of 'run' output * Description: cross-clock FIFO with special handling of 'run' output
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sens_hispi_lane * Module: sens_hispi_lane
* Date:2015-10-13 * Date:2015-10-13
* Author: andrey * Author: Andrey Filippov
* Description: Decode a single lane of the HiSPi data assuming packetized-SP protocol * Description: Decode a single lane of the HiSPi data assuming packetized-SP protocol
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sensor_i2c_prot * Module: sensor_i2c_prot
* Date:2015-10-05 * Date:2015-10-05
* Author: andrey * Author: Andrey Filippov
* Description: Generate i2c R/W sequence from a 32-bit word and LUT * Description: Generate i2c R/W sequence from a 32-bit word and LUT
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sensor_i2c_scl_sda * Module: sensor_i2c_scl_sda
* Date:2015-10-06 * Date:2015-10-06
* Author: andrey * Author: Andrey Filippov
* Description: Generation of i2c signals * Description: Generation of i2c signals
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: par12_hispi_psp4l * Module: par12_hispi_psp4l
* Date:2015-10-11 * Date:2015-10-11
* Author: andrey * Author: Andrey Filippov
* Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes * Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sim_clk_div * Module: sim_clk_div
* Date:2015-10-11 * Date:2015-10-11
* Author: andrey * Author: Andrey Filippov
* Description: Divide clock frequency by integer number * Description: Divide clock frequency by integer number
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: sim_frac_clk_delay * Module: sim_frac_clk_delay
* Date:2015-10-11 * Date:2015-10-11
* Author: andrey * Author: Andrey Filippov
* Description: Delay clock-synchronous signal by fractional number of periods * Description: Delay clock-synchronous signal by fractional number of periods
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: simul_clk * Module: simul_clk
* Date:2015-07-29 * Date:2015-07-29
* Author: andrey * Author: Andrey Filippov
* Description: Generate clocks for simulation * Description: Generate clocks for simulation
* *
* Copyright (c) 2015 Elphel, Inc. * Copyright (c) 2015 Elphel, Inc.
......
/******************************************************************************* /*******************************************************************************
* Module: simul_clk_div_mult * Module: simul_clk_div_mult
* Date:2015-10-12 * Date:2015-10-12
* Author: andrey * Author: Andrey Filippov
* Description: Simulation clock rational multiplier * Description: Simulation clock rational multiplier
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: simul_clk_mult * Module: simul_clk_mult
* Date:2015-10-10 * Date:2015-10-10
* Author: andrey * Author: Andrey Filippov
* Description: Clock multiplier * Description: Clock multiplier
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: simul_clk_mult_div * Module: simul_clk_mult_div
* Date:2015-10-12 * Date:2015-10-12
* Author: andrey * Author: Andrey Filippov
* Description: Simulation clock rational multiplier * Description: Simulation clock rational multiplier
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: IBUFG * Module: IBUFG
* Date:2015-11-06 * Date:2015-11-06
* Author: andrey * Author: Andrey Filippov
* Description: Module name "known" to synthesis, but missing in unisims * Description: Module name "known" to synthesis, but missing in unisims
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: IBUFGDS * Module: IBUFGDS
* Date:2015-11-06 * Date:2015-11-06
* Author: andrey * Author: Andrey Filippov
* Description: Module name "known" to synthesis, but missing in unisims * Description: Module name "known" to synthesis, but missing in unisims
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: debug_master * Module: debug_master
* Date:2015-09-03 * Date:2015-09-03
* Author: andrey * Author: Andrey Filippov
* Description: Debug master module to send/receive serial debug data * Description: Debug master module to send/receive serial debug data
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: debug_slave * Module: debug_slave
* Date:2015-09-03 * Date:2015-09-03
* Author: andrey * Author: Andrey Filippov
* Description: Send/receive debug data over the serial ring * Description: Send/receive debug data over the serial ring
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: fifo_sameclock_control * Module: fifo_sameclock_control
* Date:2016-01-20 * Date:2016-01-20
* Author: andrey * Author: Andrey Filippov
* Description: BRAM-based fifo control, uses BARM output registers * Description: BRAM-based fifo control, uses BARM output registers
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: frame_num_sync * Module: frame_num_sync
* Date:2016-04-28 * Date:2016-04-28
* Author: andrey * Author: Andrey Filippov
* Description: Propagating frame number from acquisition to compressor output * Description: Propagating frame number from acquisition to compressor output
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: obufds * Module: obufds
* Date:2015-10-15 * Date:2015-10-15
* Author: andrey * Author: Andrey Filippov
* Description: Wrapper for OBUFDS primitive * Description: Wrapper for OBUFDS primitive
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: select_clk_buf * Module: select_clk_buf
* Date:2015-11-07 * Date:2015-11-07
* Author: andrey * Author: Andrey Filippov
* Description: Select one of the clock buffers primitives by parameter * Description: Select one of the clock buffers primitives by parameter
* *
* Copyright (c) 2015 Elphel, Inc . * Copyright (c) 2015 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_ctrl_stat * Module: ahci_ctrl_stat
* Date:2016-01-12 * Date:2016-01-12
* Author: andrey * Author: Andrey Filippov
* Description: Copy of significant register fields, updating them in * Description: Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible) * axi_ahci_regs registers (software accessible)
* *
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_dma_rd_stuff * Module: ahci_dma_rd_stuff
* Date:2016-01-01 * Date:2016-01-01
* Author: andrey * Author: Andrey Filippov
* Description: Stuff DWORD data with missing words into continuous 32-bit data * Description: Stuff DWORD data with missing words into continuous 32-bit data
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_fis_transmit * Module: ahci_fis_transmit
* Date:2016-01-07 * Date:2016-01-07
* Author: andrey * Author: Andrey Filippov
* Description: Fetches commands, command tables, creates/sends FIS * Description: Fetches commands, command tables, creates/sends FIS
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_fsm * Module: ahci_fsm
* Date:2016-01-10 * Date:2016-01-10
* Author: andrey * Author: Andrey Filippov
* Description: AHCI host+port0 state machine * Description: AHCI host+port0 state machine
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: ahci_sata_layers * Module: ahci_sata_layers
* Date:2016-01-19 * Date:2016-01-19
* Author: andrey * Author: Andrey Filippov
* Description: Link and PHY SATA layers * Description: Link and PHY SATA layers
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......
/******************************************************************************* /*******************************************************************************
* Module: axi_hp_abort * Module: axi_hp_abort
* Date:2016-02-07 * Date:2016-02-07
* Author: andrey * Author: Andrey Filippov
* Description: Trying to gracefully reset AXI HP after aborted transmission * Description: Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0) * For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w * For write - keep track aof all what was sent so far, assuming aw is always ahead of w
......
/******************************************************************************* /*******************************************************************************
* Module: freq_meter * Module: freq_meter
* Date:2016-02-13 * Date:2016-02-13
* Author: andrey * Author: Andrey Filippov
* Description: Measure device clock frequency to set the local clock * Description: Measure device clock frequency to set the local clock
* *
* Copyright (c) 2016 Elphel, Inc . * Copyright (c) 2016 Elphel, Inc .
......