From 374d7837522fc4ee4c66c041e60b5c0396bf20aa Mon Sep 17 00:00:00 2001 From: Andrey Filippov Date: Thu, 5 May 2016 10:38:44 -0600 Subject: [PATCH] changed user name to full name --- .project | 22 +++++------ compressor_jp/bit_stuffer_27_32.v | 2 +- compressor_jp/bit_stuffer_escape.v | 2 +- compressor_jp/bit_stuffer_metadata.v | 2 +- compressor_jp/huffman_merge_code_literal.v | 2 +- compressor_jp/huffman_stuffer_meta.v | 2 +- fpga_version.vh | 3 +- helpers/quantization_100.dat | 33 ++++++++-------- helpers/quantization_100.dat.vh | 16 ++++---- includes/quantization_100.dat.vh | 16 ++++---- includes/tasks_tests_memory.vh | 2 +- input_data/quantization_100.dat | 33 ++++++++-------- sensor/sens_10398.v | 2 +- sensor/sens_hispi12l4.v | 2 +- sensor/sens_hispi_clock.v | 2 +- sensor/sens_hispi_din.v | 2 +- sensor/sens_hispi_fifo.v | 2 +- sensor/sens_hispi_lane.v | 2 +- sensor/sensor_i2c_prot.v | 2 +- sensor/sensor_i2c_scl_sda.v | 2 +- simulation_modules/par12_hispi_psp4l.v | 2 +- simulation_modules/sim_clk_div.v | 2 +- simulation_modules/sim_frac_clk_delay.v | 2 +- simulation_modules/simul_clk.v | 2 +- simulation_modules/simul_clk_div_mult.v | 2 +- simulation_modules/simul_clk_mult.v | 2 +- simulation_modules/simul_clk_mult_div.v | 2 +- unisims_extra/IBUFG.v | 2 +- unisims_extra/IBUFGDS.v | 2 +- util_modules/debug_master.v | 2 +- util_modules/debug_slave.v | 2 +- util_modules/fifo_sameclock_control.v | 2 +- util_modules/frame_num_sync.v | 2 +- wrap/obufds.v | 2 +- wrap/select_clk_buf.v | 2 +- x393_sata/ahci/ahci_ctrl_stat.v | 2 +- x393_sata/ahci/ahci_dma_rd_stuff.v | 2 +- x393_sata/ahci/ahci_fis_transmit.v | 2 +- x393_sata/ahci/ahci_fsm.v | 2 +- x393_sata/ahci/ahci_sata_layers.v | 2 +- x393_sata/ahci/axi_hp_abort.v | 2 +- x393_sata/ahci/freq_meter.v | 2 +- x393_sata/host/drp_other_registers.v | 2 +- x393_sata/host/elastic1632.v | 2 +- x393_sata/wrapper/clock_inverter.v | 2 +- x393_testbench03.tf | 12 +++--- x393_testbench04.sav | 44 ++++++++++++++++++---- 47 files changed, 142 insertions(+), 115 deletions(-) diff --git a/.project b/.project index a780f29..9365acd 100644 --- a/.project +++ b/.project @@ -62,52 +62,52 @@ vivado_logs/VivadoBitstream.log 1 - /home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoBitstream-20160504204346976.log vivado_logs/VivadoOpt.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoOpt-20160504204346976.log vivado_logs/VivadoOptPhys.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160504204346976.log vivado_logs/VivadoOptPower.log 1 - /home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoOptPower-20160504204346976.log vivado_logs/VivadoPlace.log 1 - /home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoPlace-20160504204346976.log vivado_logs/VivadoRoute.log 1 - /home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoRoute-20160504204346976.log vivado_logs/VivadoSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log + /home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160504203656004.log vivado_logs/VivadoTimimgSummaryReportImplemented.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log + /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160504204346976.log vivado_logs/VivadoTimimgSummaryReportSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log + /home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160504203656004.log vivado_logs/VivadoTimingReportSynthesis.log 1 - /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log + /home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160504203656004.log vivado_state/x393-opt-phys.dcp @@ -127,7 +127,7 @@ vivado_state/x393-synth.dcp 1 - /home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp + /home/andrey/git/x393/vivado_state/x393-synth-20160504203656004.dcp diff --git a/compressor_jp/bit_stuffer_27_32.v b/compressor_jp/bit_stuffer_27_32.v index fdbdc8d..77cad58 100644 --- a/compressor_jp/bit_stuffer_27_32.v +++ b/compressor_jp/bit_stuffer_27_32.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: bit_stuffer_27_32 * Date:2015-10-23 - * Author: andrey + * Author: Andrey Filippov * Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words * * Copyright (c) 2015 Elphel, Inc . diff --git a/compressor_jp/bit_stuffer_escape.v b/compressor_jp/bit_stuffer_escape.v index 66b45ee..c60e99a 100644 --- a/compressor_jp/bit_stuffer_escape.v +++ b/compressor_jp/bit_stuffer_escape.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: bit_stuffer_escape * Date:2015-10-24 - * Author: andrey + * Author: Andrey Filippov * Description: Escapes each 0xff with 0x00, 32-bit input and output * * Copyright (c) 2015 Elphel, Inc . diff --git a/compressor_jp/bit_stuffer_metadata.v b/compressor_jp/bit_stuffer_metadata.v index b998148..303978c 100644 --- a/compressor_jp/bit_stuffer_metadata.v +++ b/compressor_jp/bit_stuffer_metadata.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: bit_stuffer_metadata * Date:2015-10-25 - * Author: andrey + * Author: Andrey Filippov * Description: * * Copyright (c) 2015 Elphel, Inc . diff --git a/compressor_jp/huffman_merge_code_literal.v b/compressor_jp/huffman_merge_code_literal.v index 6b62cb2..758e564 100644 --- a/compressor_jp/huffman_merge_code_literal.v +++ b/compressor_jp/huffman_merge_code_literal.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: huffman_merge_code_literal * Date:2015-10-22 - * Author: andrey + * Author: Andrey Filippov * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data, * align result to MSB : {huffman,literal, {n{1'b0}} * diff --git a/compressor_jp/huffman_stuffer_meta.v b/compressor_jp/huffman_stuffer_meta.v index 0cf980e..9020cda 100644 --- a/compressor_jp/huffman_stuffer_meta.v +++ b/compressor_jp/huffman_stuffer_meta.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: huffman_stuffer_meta * Date:2015-10-26 - * Author: andrey + * Author: Andrey Filippov * Description: Huffman encoder, bit stuffer, inser meta-data * "New" part of the JPEG/JP4 comressor that used double frequency clock * diff --git a/fpga_version.vh b/fpga_version.vh index 86e4b5a..69271aa 100644 --- a/fpga_version.vh +++ b/fpga_version.vh @@ -32,7 +32,8 @@ * with at least one of the Free Software programs. *******************************************************************************/ - parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer + parameter FPGA_VERSION = 32'h03930087; // Fixed default 90% quantization table +// parameter FPGA_VERSION = 32'h03930087; // Synchronizing i2c sequencer frame number with that of a command sequencer // parameter FPGA_VERSION = 32'h03930086; // Adding byte-wide JTAG read to speed-up 10359 load // parameter FPGA_VERSION = 32'h03930085; // Adding software control for i2c pins when sequencer is stopped, timing matched // parameter FPGA_VERSION = 32'h03930084; // Back to iserdes, inverting xfpgatdo - met diff --git a/helpers/quantization_100.dat b/helpers/quantization_100.dat index 19abce8..84cc028 100644 --- a/helpers/quantization_100.dat +++ b/helpers/quantization_100.dat @@ -16,21 +16,20 @@ ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff - 5550 8000 8000 5550 8000 8000 5550 5550 - 5550 5550 4000 5550 5550 4000 3330 2000 - 3330 3330 4000 4000 3330 19a0 2490 2490 - 2ab0 2000 1550 19a0 1550 1550 1740 19a0 - 1740 1740 13b0 1250 e40 1000 13b0 1250 - f10 1250 1740 1740 1000 ba0 1000 f10 - d80 cd0 c30 c30 c30 1550 1110 b20 - ab0 ba0 cd0 ab0 e40 cd0 c30 cd0 - - 5550 4000 4000 3330 4000 3330 1c70 3330 - 3330 1c70 cd0 13b0 1740 13b0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 + 5555 8000 8000 5555 3333 2000 199a 1555 + 8000 8000 5555 4000 3333 1555 1555 1746 + 5555 5555 5555 3333 2000 1746 1249 1746 + 5555 5555 4000 2aab 199a 0f0f 1000 1555 + 4000 4000 2492 1746 1249 0ba3 0c31 1111 + 3333 2492 1746 13b1 1000 0c31 0b21 0e39 + 199a 13b1 1000 0f0f 0c31 0aab 0aab 0ccd + 1249 0e39 0d79 0ccd 0ba3 0ccd 0c31 0ccd + 5555 4000 3333 1c72 0ccd 0ccd 0ccd 0ccd + 4000 4000 3333 13b1 0ccd 0ccd 0ccd 0ccd + 3333 3333 1746 0ccd 0ccd 0ccd 0ccd 0ccd + 1c72 13b1 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd diff --git a/helpers/quantization_100.dat.vh b/helpers/quantization_100.dat.vh index 9970ab6..181fc5c 100644 --- a/helpers/quantization_100.dat.vh +++ b/helpers/quantization_100.dat.vh @@ -6,11 +6,11 @@ , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) -, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550) -, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330) -, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740) -, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80) -, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550) -, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) -, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) -, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) +, .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555) +, .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555) +, .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000) +, .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A) +, .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555) +, .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333) +, .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD) +, .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD) diff --git a/includes/quantization_100.dat.vh b/includes/quantization_100.dat.vh index 9970ab6..181fc5c 100644 --- a/includes/quantization_100.dat.vh +++ b/includes/quantization_100.dat.vh @@ -6,11 +6,11 @@ , .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) , .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) -, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550) -, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330) -, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740) -, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80) -, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550) -, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) -, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) -, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0) +, .INIT_08 (256'h174615551555333340005555800080001555199A200033335555800080005555) +, .INIT_09 (256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555) +, .INIT_0A (256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000) +, .INIT_0B (256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A) +, .INIT_0C (256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555) +, .INIT_0D (256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333) +, .INIT_0E (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD) +, .INIT_0F (256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD) diff --git a/includes/tasks_tests_memory.vh b/includes/tasks_tests_memory.vh index 0010db5..98e8850 100644 --- a/includes/tasks_tests_memory.vh +++ b/includes/tasks_tests_memory.vh @@ -1,7 +1,7 @@ /******************************************************************************* * Module: tasks_tests_memory * Date:2015-08-01 - * Author: andrey + * Author: Andrey Filippov * Description: Top-level tasks for testing memory subsystem functionality * * Copyright (c) 2015 Elphel, Inc . diff --git a/input_data/quantization_100.dat b/input_data/quantization_100.dat index 19abce8..84cc028 100644 --- a/input_data/quantization_100.dat +++ b/input_data/quantization_100.dat @@ -16,21 +16,20 @@ ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff - 5550 8000 8000 5550 8000 8000 5550 5550 - 5550 5550 4000 5550 5550 4000 3330 2000 - 3330 3330 4000 4000 3330 19a0 2490 2490 - 2ab0 2000 1550 19a0 1550 1550 1740 19a0 - 1740 1740 13b0 1250 e40 1000 13b0 1250 - f10 1250 1740 1740 1000 ba0 1000 f10 - d80 cd0 c30 c30 c30 1550 1110 b20 - ab0 ba0 cd0 ab0 e40 cd0 c30 cd0 - - 5550 4000 4000 3330 4000 3330 1c70 3330 - 3330 1c70 cd0 13b0 1740 13b0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 - cd0 cd0 cd0 cd0 cd0 cd0 cd0 cd0 + 5555 8000 8000 5555 3333 2000 199a 1555 + 8000 8000 5555 4000 3333 1555 1555 1746 + 5555 5555 5555 3333 2000 1746 1249 1746 + 5555 5555 4000 2aab 199a 0f0f 1000 1555 + 4000 4000 2492 1746 1249 0ba3 0c31 1111 + 3333 2492 1746 13b1 1000 0c31 0b21 0e39 + 199a 13b1 1000 0f0f 0c31 0aab 0aab 0ccd + 1249 0e39 0d79 0ccd 0ba3 0ccd 0c31 0ccd + 5555 4000 3333 1c72 0ccd 0ccd 0ccd 0ccd + 4000 4000 3333 13b1 0ccd 0ccd 0ccd 0ccd + 3333 3333 1746 0ccd 0ccd 0ccd 0ccd 0ccd + 1c72 13b1 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd + 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd 0ccd diff --git a/sensor/sens_10398.v b/sensor/sens_10398.v index 3385da9..b68bf0c 100644 --- a/sensor/sens_10398.v +++ b/sensor/sens_10398.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_10398 * Date:2015-10-15 - * Author: andrey + * Author: Andrey Filippov * Description: Top level module for the 10398 SFE (with MT9F002 sensor) * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sens_hispi12l4.v b/sensor/sens_hispi12l4.v index 02940cd..dd01fa1 100644 --- a/sensor/sens_hispi12l4.v +++ b/sensor/sens_hispi12l4.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_hispi12l4 * Date:2015-10-13 - * Author: andrey + * Author: Andrey Filippov * Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sens_hispi_clock.v b/sensor/sens_hispi_clock.v index a589482..456c10e 100644 --- a/sensor/sens_hispi_clock.v +++ b/sensor/sens_hispi_clock.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_hispi_clock * Date:2015-10-13 - * Author: andrey + * Author: Andrey Filippov * Description: Recover iclk/iclk2x from the HiSPi differntial clock * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sens_hispi_din.v b/sensor/sens_hispi_din.v index 47f0437..772d136 100644 --- a/sensor/sens_hispi_din.v +++ b/sensor/sens_hispi_din.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_hispi_din * Date:2015-10-13 - * Author: andrey + * Author: Andrey Filippov * Description: Input differential receivers for HiSPi lanes * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sens_hispi_fifo.v b/sensor/sens_hispi_fifo.v index 346dbd1..e1a35c4 100644 --- a/sensor/sens_hispi_fifo.v +++ b/sensor/sens_hispi_fifo.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_hispi_fifo * Date:2015-10-14 - * Author: andrey + * Author: Andrey Filippov * Description: cross-clock FIFO with special handling of 'run' output * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sens_hispi_lane.v b/sensor/sens_hispi_lane.v index 19e0d52..089d072 100644 --- a/sensor/sens_hispi_lane.v +++ b/sensor/sens_hispi_lane.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sens_hispi_lane * Date:2015-10-13 - * Author: andrey + * Author: Andrey Filippov * Description: Decode a single lane of the HiSPi data assuming packetized-SP protocol * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sensor_i2c_prot.v b/sensor/sensor_i2c_prot.v index e757140..880a6e0 100644 --- a/sensor/sensor_i2c_prot.v +++ b/sensor/sensor_i2c_prot.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sensor_i2c_prot * Date:2015-10-05 - * Author: andrey + * Author: Andrey Filippov * Description: Generate i2c R/W sequence from a 32-bit word and LUT * * Copyright (c) 2015 Elphel, Inc . diff --git a/sensor/sensor_i2c_scl_sda.v b/sensor/sensor_i2c_scl_sda.v index 6ce6df3..0fde5e3 100644 --- a/sensor/sensor_i2c_scl_sda.v +++ b/sensor/sensor_i2c_scl_sda.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sensor_i2c_scl_sda * Date:2015-10-06 - * Author: andrey + * Author: Andrey Filippov * Description: Generation of i2c signals * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/par12_hispi_psp4l.v b/simulation_modules/par12_hispi_psp4l.v index 501defc..b7a244e 100644 --- a/simulation_modules/par12_hispi_psp4l.v +++ b/simulation_modules/par12_hispi_psp4l.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: par12_hispi_psp4l * Date:2015-10-11 - * Author: andrey + * Author: Andrey Filippov * Description: Convertp parallel 12bit to HiSPi packetized-SP 4 lanes * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/sim_clk_div.v b/simulation_modules/sim_clk_div.v index cf4b82a..238fbe0 100644 --- a/simulation_modules/sim_clk_div.v +++ b/simulation_modules/sim_clk_div.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sim_clk_div * Date:2015-10-11 - * Author: andrey + * Author: Andrey Filippov * Description: Divide clock frequency by integer number * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/sim_frac_clk_delay.v b/simulation_modules/sim_frac_clk_delay.v index 989b9bd..f4cfa89 100644 --- a/simulation_modules/sim_frac_clk_delay.v +++ b/simulation_modules/sim_frac_clk_delay.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: sim_frac_clk_delay * Date:2015-10-11 - * Author: andrey + * Author: Andrey Filippov * Description: Delay clock-synchronous signal by fractional number of periods * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/simul_clk.v b/simulation_modules/simul_clk.v index fd24d74..b5fe918 100644 --- a/simulation_modules/simul_clk.v +++ b/simulation_modules/simul_clk.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: simul_clk * Date:2015-07-29 - * Author: andrey + * Author: Andrey Filippov * Description: Generate clocks for simulation * * Copyright (c) 2015 Elphel, Inc. diff --git a/simulation_modules/simul_clk_div_mult.v b/simulation_modules/simul_clk_div_mult.v index b684149..2b98a92 100644 --- a/simulation_modules/simul_clk_div_mult.v +++ b/simulation_modules/simul_clk_div_mult.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: simul_clk_div_mult * Date:2015-10-12 - * Author: andrey + * Author: Andrey Filippov * Description: Simulation clock rational multiplier * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/simul_clk_mult.v b/simulation_modules/simul_clk_mult.v index a45b86a..7cc56f6 100644 --- a/simulation_modules/simul_clk_mult.v +++ b/simulation_modules/simul_clk_mult.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: simul_clk_mult * Date:2015-10-10 - * Author: andrey + * Author: Andrey Filippov * Description: Clock multiplier * * Copyright (c) 2015 Elphel, Inc . diff --git a/simulation_modules/simul_clk_mult_div.v b/simulation_modules/simul_clk_mult_div.v index b3ab3b4..91a9a63 100644 --- a/simulation_modules/simul_clk_mult_div.v +++ b/simulation_modules/simul_clk_mult_div.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: simul_clk_mult_div * Date:2015-10-12 - * Author: andrey + * Author: Andrey Filippov * Description: Simulation clock rational multiplier * * Copyright (c) 2015 Elphel, Inc . diff --git a/unisims_extra/IBUFG.v b/unisims_extra/IBUFG.v index c32de2d..0e35b52 100644 --- a/unisims_extra/IBUFG.v +++ b/unisims_extra/IBUFG.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: IBUFG * Date:2015-11-06 - * Author: andrey + * Author: Andrey Filippov * Description: Module name "known" to synthesis, but missing in unisims * * Copyright (c) 2015 Elphel, Inc . diff --git a/unisims_extra/IBUFGDS.v b/unisims_extra/IBUFGDS.v index 64515a5..c045596 100644 --- a/unisims_extra/IBUFGDS.v +++ b/unisims_extra/IBUFGDS.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: IBUFGDS * Date:2015-11-06 - * Author: andrey + * Author: Andrey Filippov * Description: Module name "known" to synthesis, but missing in unisims * * Copyright (c) 2015 Elphel, Inc . diff --git a/util_modules/debug_master.v b/util_modules/debug_master.v index f500e67..3d1cf76 100644 --- a/util_modules/debug_master.v +++ b/util_modules/debug_master.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: debug_master * Date:2015-09-03 - * Author: andrey + * Author: Andrey Filippov * Description: Debug master module to send/receive serial debug data * * Copyright (c) 2015 Elphel, Inc . diff --git a/util_modules/debug_slave.v b/util_modules/debug_slave.v index 1a5d1ab..57d8033 100644 --- a/util_modules/debug_slave.v +++ b/util_modules/debug_slave.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: debug_slave * Date:2015-09-03 - * Author: andrey + * Author: Andrey Filippov * Description: Send/receive debug data over the serial ring * * Copyright (c) 2015 Elphel, Inc . diff --git a/util_modules/fifo_sameclock_control.v b/util_modules/fifo_sameclock_control.v index c0e30d4..cdb95d9 100644 --- a/util_modules/fifo_sameclock_control.v +++ b/util_modules/fifo_sameclock_control.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: fifo_sameclock_control * Date:2016-01-20 - * Author: andrey + * Author: Andrey Filippov * Description: BRAM-based fifo control, uses BARM output registers * * Copyright (c) 2016 Elphel, Inc . diff --git a/util_modules/frame_num_sync.v b/util_modules/frame_num_sync.v index 67c409a..dbff4b0 100644 --- a/util_modules/frame_num_sync.v +++ b/util_modules/frame_num_sync.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: frame_num_sync * Date:2016-04-28 - * Author: andrey + * Author: Andrey Filippov * Description: Propagating frame number from acquisition to compressor output * * Copyright (c) 2016 Elphel, Inc . diff --git a/wrap/obufds.v b/wrap/obufds.v index 97521c3..fb99e30 100644 --- a/wrap/obufds.v +++ b/wrap/obufds.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: obufds * Date:2015-10-15 - * Author: andrey + * Author: Andrey Filippov * Description: Wrapper for OBUFDS primitive * * Copyright (c) 2015 Elphel, Inc . diff --git a/wrap/select_clk_buf.v b/wrap/select_clk_buf.v index d494185..e676e29 100644 --- a/wrap/select_clk_buf.v +++ b/wrap/select_clk_buf.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: select_clk_buf * Date:2015-11-07 - * Author: andrey + * Author: Andrey Filippov * Description: Select one of the clock buffers primitives by parameter * * Copyright (c) 2015 Elphel, Inc . diff --git a/x393_sata/ahci/ahci_ctrl_stat.v b/x393_sata/ahci/ahci_ctrl_stat.v index 3b9fe76..e508484 100644 --- a/x393_sata/ahci/ahci_ctrl_stat.v +++ b/x393_sata/ahci/ahci_ctrl_stat.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: ahci_ctrl_stat * Date:2016-01-12 - * Author: andrey + * Author: Andrey Filippov * Description: Copy of significant register fields, updating them in * axi_ahci_regs registers (software accessible) * diff --git a/x393_sata/ahci/ahci_dma_rd_stuff.v b/x393_sata/ahci/ahci_dma_rd_stuff.v index 8b15bbb..639d79a 100644 --- a/x393_sata/ahci/ahci_dma_rd_stuff.v +++ b/x393_sata/ahci/ahci_dma_rd_stuff.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: ahci_dma_rd_stuff * Date:2016-01-01 - * Author: andrey + * Author: Andrey Filippov * Description: Stuff DWORD data with missing words into continuous 32-bit data * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/ahci/ahci_fis_transmit.v b/x393_sata/ahci/ahci_fis_transmit.v index b74902d..c4073c6 100644 --- a/x393_sata/ahci/ahci_fis_transmit.v +++ b/x393_sata/ahci/ahci_fis_transmit.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: ahci_fis_transmit * Date:2016-01-07 - * Author: andrey + * Author: Andrey Filippov * Description: Fetches commands, command tables, creates/sends FIS * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/ahci/ahci_fsm.v b/x393_sata/ahci/ahci_fsm.v index 04edf4f..51aa9b9 100644 --- a/x393_sata/ahci/ahci_fsm.v +++ b/x393_sata/ahci/ahci_fsm.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: ahci_fsm * Date:2016-01-10 - * Author: andrey + * Author: Andrey Filippov * Description: AHCI host+port0 state machine * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/ahci/ahci_sata_layers.v b/x393_sata/ahci/ahci_sata_layers.v index 473502b..94023e6 100644 --- a/x393_sata/ahci/ahci_sata_layers.v +++ b/x393_sata/ahci/ahci_sata_layers.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: ahci_sata_layers * Date:2016-01-19 - * Author: andrey + * Author: Andrey Filippov * Description: Link and PHY SATA layers * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/ahci/axi_hp_abort.v b/x393_sata/ahci/axi_hp_abort.v index 4607cf9..19c847b 100644 --- a/x393_sata/ahci/axi_hp_abort.v +++ b/x393_sata/ahci/axi_hp_abort.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: axi_hp_abort * Date:2016-02-07 - * Author: andrey + * Author: Andrey Filippov * Description: Trying to gracefully reset AXI HP after aborted transmission * For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0) * For write - keep track aof all what was sent so far, assuming aw is always ahead of w diff --git a/x393_sata/ahci/freq_meter.v b/x393_sata/ahci/freq_meter.v index 4e03ab8..b7ebfc7 100644 --- a/x393_sata/ahci/freq_meter.v +++ b/x393_sata/ahci/freq_meter.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: freq_meter * Date:2016-02-13 - * Author: andrey + * Author: Andrey Filippov * Description: Measure device clock frequency to set the local clock * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/host/drp_other_registers.v b/x393_sata/host/drp_other_registers.v index 774fcfa..fb3ae0f 100644 --- a/x393_sata/host/drp_other_registers.v +++ b/x393_sata/host/drp_other_registers.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: drp_other_registers * Date:2016-03-13 - * Author: andrey + * Author: Andrey Filippov * Description: Additional registers controlled/read back over DRP * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/host/elastic1632.v b/x393_sata/host/elastic1632.v index e9b13ec..33e88ad 100644 --- a/x393_sata/host/elastic1632.v +++ b/x393_sata/host/elastic1632.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: elastic1632 * Date:2016-02-03 - * Author: andrey + * Author: Andrey Filippov * Description: Elastic buffer with 16-bit data input and 32-bit output * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_sata/wrapper/clock_inverter.v b/x393_sata/wrapper/clock_inverter.v index 894d967..f7f1b86 100644 --- a/x393_sata/wrapper/clock_inverter.v +++ b/x393_sata/wrapper/clock_inverter.v @@ -1,7 +1,7 @@ /******************************************************************************* * Module: clock_inverter * Date:2016-02-11 - * Author: andrey + * Author: Andrey Filippov * Description: Glitch-free clock controlled inverter * * Copyright (c) 2016 Elphel, Inc . diff --git a/x393_testbench03.tf b/x393_testbench03.tf index fb75ab5..93844b7 100644 --- a/x393_testbench03.tf +++ b/x393_testbench03.tf @@ -1226,13 +1226,13 @@ assign #10 gpio_pins[9] = gpio_pins[8]; 'h10000 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks */ 'h10000000 >> 5, // input [26:0] afi_cmprs0_sa; // input [26:0] sa; // start address in 32-byte chunks - 'h800 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks + 'h5c0 >> 5, // 'h800 >> 5, // input [26:0] afi_cmprs0_len; // input [26:0] length; // channel buffer length in 32-byte chunks 'h10010000 >> 5, // input [26:0] afi_cmprs1_sa; // input [26:0] sa; // start address in 32-byte chunks - 'h400 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks + 'h2e0 >> 5, // h400 >> 5, // input [26:0] afi_cmprs1_len; // input [26:0] length; // channel buffer length in 32-byte chunks 'h10020000 >> 5, // input [26:0] afi_cmprs2_sa; // input [26:0] sa; // start address in 32-byte chunks - 'h200 >> 5, // input [26:0] afi_cmprs2_len; // input [26:0] length; // channel buffer length in 32-byte chunks + 'h280 >> 5, // 'h200 >> 5, // input [26:0] afi_cmprs2_len; // input [26:0] length; // channel buffer length in 32-byte chunks 'h10030000 >> 5, // input [26:0] afi_cmprs3_sa; // input [26:0] sa; // start address in 32-byte chunks - 'h100 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks + 'h1e0 >> 5); // 'h100 >> 5); // input [26:0] afi_cmprs3_len; // input [26:0] length; // channel buffer length in 32-byte chunks camsync_setup ( 4'hf ); // sensor_mask); // /* @@ -2756,7 +2756,7 @@ task setup_sensor_channel; compressor_run (num_sensor, 0); // reset compressor - simulation_datasimulation_dataspecify_window 66 36 0 0 0 3 1 + if (cmode == CMPRS_CBIT_CMODE_JPEG18) begin setup_compressor_channel( @@ -2819,7 +2819,7 @@ task setup_sensor_channel; (cmode == CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2)) begin setup_compressor_channel( num_sensor, // sensor channel number (0..3) - 0, // qbank; // [6:3] quantization table page - 100% quality + ((num_sensor == 1) || (num_sensor == 3))? 1 : 0, // 0, // qbank; // [6:3] quantization table page - 100% quality // 1, // qbank; // [6:3] quantization table page - 85%? quality 1, // dc_sub; // [8:7] subtract DC cmode, // CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode: diff --git a/x393_testbench04.sav b/x393_testbench04.sav index fe22cfd..bb87775 100644 --- a/x393_testbench04.sav +++ b/x393_testbench04.sav @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI -[*] Wed May 4 20:52:00 2016 +[*] Thu May 5 06:16:12 2016 [*] -[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160504133628289.fst" -[dumpfile_mtime] "Wed May 4 20:03:27 2016" -[dumpfile_size] 89230413 +[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160504231654593.fst" +[dumpfile_mtime] "Thu May 5 05:44:01 2016" +[dumpfile_size] 89249645 [savefile] "/home/andrey/git/x393/x393_testbench04.sav" [timestart] 0 [size] 1823 1180 [pos] -1 -1 -*-24.733164 47500000 121282388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-24.979511 145131000 121282388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] x393_testbench03. [treeopen] x393_testbench03.simul_axi_hp_wr_i. [treeopen] x393_testbench03.x393_i. @@ -18,7 +18,8 @@ [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1]. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2]. [treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3]. -[treeopen] x393_testbench03.x393_i.sensors393_i. +[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3. +[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1]. @@ -28,7 +29,7 @@ [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_parallel12_i. -[sst_width] 257 +[sst_width] 377 [signals_width] 340 [sst_expanded] 1 [sst_vpaned_height] 575 @@ -64,7 +65,6 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.fifo @22 x393_testbench03.setup_sensor_channel.num_sensor[1:0] x393_testbench03.setup_compressor_channel.num_sensor[1:0] -@23 x393_testbench03.setup_compressor_channel.qbank[31:0] @200 - @@ -140,8 +140,36 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.left x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.left_marg[4:0] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.left_marg[4:0] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.left_marg[4:0] +@c00200 +-status +@22 +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.chunk_ptr_ra[3:0] +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.chunk_ptr_rd[25:0] +@28 +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_rq +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_status_i.status_start +@1401200 +-status +@22 +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_i.chunk_ptr_rd[26:0] +x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.chunk_ptr_rd[26:0] @1000200 -all_cmprs_out +@800200 +-sim_afi1 +@200 +- +@23 +x393_testbench03.sim_cmprs0_addr[31:0] +x393_testbench03.sim_cmprs0_data[63:0] +x393_testbench03.sim_cmprs1_addr[31:0] +x393_testbench03.sim_cmprs1_data[63:0] +x393_testbench03.sim_cmprs2_addr[31:0] +x393_testbench03.sim_cmprs2_data[63:0] +x393_testbench03.sim_cmprs3_addr[31:0] +x393_testbench03.sim_cmprs3_data[63:0] +@1000200 +-sim_afi1 @c00200 -all_sensor_data @22 -- 2.18.1