modifying table write in compressor chian modules

//TODO: Modify to work with other modes (now only on color)

module focus_sharp393(

    input             clk,          // pixel clock, posedge

    input             clk2x,        // 2x pixel clock

    input             en,           // enable (0 resets)

    input             mclk,         // system clock to write tables

    input             tser_we,      // enable write to a  table

    reg [2:0] clksync;

    wire      csync=clksync[2];

    always @ (posedge sclk) begin

    always @ (posedge clk2x) begin

       clksync[2:0] <= {(clksync[1]==clksync[0]),clksync[0],clkdiv2};

    end

    assign       mult_a[17:0] = use_coef ? {1'b0,tdo[15:0],1'b0}: mult_s[17:0];

    assign      mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];

    always @ (posedge sclk) begin

    always @ (posedge clk2x) begin

        filt_sel[3:0] <= filt_sel0[3:0];

        if (clksync[2]) d1[11:0]<=di_d[11:0];

        start2[8:0] <= {start2[7:0], start && csync};

    reg      [17:0] mult_a_r;

    reg      [17:0] mult_b_r;

    assign mult_p = mult_p_r;

    always @(posedge sclk) begin

    always @(posedge clk2x) begin

        mult_a_r <= mult_a;

        mult_b_r <= mult_b;

        mult_p_r <= mult_a_r * mult_b_r;

    wire   [31:0] hifreq;       // output[31:0] reg accumulated high frequency components in a frame sub-window

    focus_sharp393 focus_sharp393_i (

        .clk                (xclk),                   // input

        .clk                (xclk),                   // input - pixel clock

        .clk2x              (xclk2x),                 // input 2x pixel clock

        .en                 (frame_en),               // input 

        .sclk               (mclk),                   // input system clock:  twe, ta,tdi - valid @negedge (ra, tdi - 2 cycles ahead)

        .twe                (twfe),                   // input enable write to a table

        .ta                 (ta[9:0]),                // input[9:0]  table address

        .tdi                (tdi),                    // input[15:0]  table data in (8 LSBs - quantization data)

        .mclk               (mclk),                   // input system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge)

        .tser_we            (tser_fe),                // input - write to a quantization table

        .tser_a_not_d       (tser_a_not_d),           // input - address/not data to tables

        .tser_d             (tser_d),                 // input[7:0] - byte-wide data to tables

        .mode               (cmprs_fmode_this[1:0]),  // input[1:0] focus mode (combine image with focus info) - 0 - none, 1 - replace, 2 - combine all,  3 - combine woi

        .firsti             (color_first),            // input first macroblock

        .lasti              (color_last),             // input last macroblock