committing pending changes

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[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI

[*] Tue Dec 13 19:22:06 2016

[*] Tue Dec 13 19:43:18 2016

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[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213121815935.fst"

[dumpfile_mtime] "Tue Dec 13 19:18:19 2016"

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[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213123921501.fst"

[dumpfile_mtime] "Tue Dec 13 19:39:21 2016"

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dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0]

    output reg               [2:0] y_index   // for simulation - valid with dout - index of the data output

);

// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*

// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*

// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*

    localparam RSHIFT1 = 2; // safe right shift for stage 1

    localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates

        end 

    end

    //register files

    assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];

    assign dsp_din_2 = dsp_din_2_ram[dsp_din_2_ra];

module  dct_iv_8x8#(

    parameter INPUT_WIDTH =     25,

    parameter OUT_WIDTH =       25,

    parameter OUT_RSHIFT1 =      3,  // overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation)

    parameter OUT_RSHIFT2 =      0,  // overall right shift of the result from input, aligned by MSB for pass2 (>=3 will never cause saturation)

    parameter OUT_RSHIFT1 =      1,  // overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation)

    parameter OUT_RSHIFT2 =      1, //  if sum OUT_RSHIFT1+OUT_RSHIFT2 == 2, direct*reverse == ident (may use 3, -1) or 3,0 with wider output and saturate

    parameter TRANSPOSE_WIDTH = 25, // transpose memory width

    parameter DSP_B_WIDTH =     18,

    parameter DSP_A_WIDTH =     25,

// 3. common transpose memory plus 2 input reorder memory for each of the vertical DCT

// 4. 2 of the vertical DCTs

// 5. small memory to combine/reorder outputs (2 stages as 1 x16 memory is not enough)

// TODO make a version that uses common transpose memory (twice width) and simultaneously calculates dst-iv (invert time sequence, alternate sign)

// That can be used for lateral chromatic aberration (shift in time domain). Reverse transform does not need it - will always be just dct-iv

    reg                               x_run;

    reg                        [5:0]  x_wa;

    wire                              dcth_phin_start = x_run && (x_wa[5:0] == 6); 

//    parameter OUT_WIDTH =     16; // output data width

    parameter OUT_WIDTH =       24; // output data width

    parameter TRANSPOSE_WIDTH = 24; // width of the transpose memory (intermediate results)    

    parameter OUT_RSHIFT =       3;  // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)

    parameter OUT_RSHIFT =       2;  // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)

    parameter OUT_RSHIFT2 =      0;  // overall right shift for the second (vertical) pass

    parameter DCT_GAP = 16; // between runs            

    reg              start = 0;

    reg              start2 = 0; // second start for 2d

    wire [OUT_WIDTH-1:0] y_dct;           // S uppressThisWarning VEditor - simulation only

    wire                 pre2_start_out;  // S uppressThisWarning VEditor - simulation only

    wire                 en_out;          // S uppressThisWarning VEditor - simulation only

    wire [OUT_WIDTH-1:0] y_dct;

    wire                 pre2_start_out;

    wire                 en_out;

    reg                  y_pre_we;

    reg                  y_we;

    reg  signed     [WIDTH-1:0] data_in[0:63];

    reg  signed [OUT_WIDTH-1:0] data_out[0:63];

    reg  signed     [WIDTH-1:0] d_in;     

    wire                        pre_last_in_2d; 

    wire                        pre_first_out_2d;

    wire                        pre_busy_2d;

    wire                        dv_2d;

    wire                        pre_last_in_2d;    // SuppressThisWarning VEditor - simulation only

    wire                        pre_first_out_2d;  // SuppressThisWarning VEditor - simulation only

    wire                        pre_busy_2d;       // SuppressThisWarning VEditor - simulation only

    wire                        dv_2d;             // SuppressThisWarning VEditor - simulation only

    wire signed [OUT_WIDTH-1:0] d_out_2d; 

    wire                        pre_last_in_2dr; 

    wire                        pre_first_out_2dr;

    wire                        pre_busy_2dr;

    wire                        dv_2dr;

    wire signed [OUT_WIDTH-1:0] d_out_2dr; 

    wire                        pre_last_in_2dr;   // SuppressThisWarning VEditor - simulation only

    wire                        pre_first_out_2dr; // SuppressThisWarning VEditor - simulation only

    wire                        pre_busy_2dr;      // SuppressThisWarning VEditor - simulation only

    wire                        dv_2dr;            // SuppressThisWarning VEditor - simulation only

    wire signed [OUT_WIDTH-1:0] d_out_2dr;         // SuppressThisWarning VEditor - simulation only

    integer              i,j, i1, j1;

    integer              i,j, i1;

    initial begin

        for (i=0; i<64; i=i+1) begin

`ifdef DCT_INPUT_UNITY