diff --git a/dct_tests_01.sav b/dct_tests_01.sav index fb63551d1e28273a7dc25b69c16f8507074490bf..d39450e6405ae0dc361dea9a923118640139229d 100644 --- a/dct_tests_01.sav +++ b/dct_tests_01.sav @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI -[*] Tue Dec 13 19:22:06 2016 +[*] Tue Dec 13 19:43:18 2016 [*] -[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213121815935.fst" -[dumpfile_mtime] "Tue Dec 13 19:18:19 2016" -[dumpfile_size] 101333 +[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213123921501.fst" +[dumpfile_mtime] "Tue Dec 13 19:39:21 2016" +[dumpfile_size] 103386 [savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav" [timestart] 0 [size] 1814 1171 [pos] 1912 0 -*-19.687614 1470200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-19.687614 3465000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] dct_tests_01. [treeopen] dct_tests_01.dct_iv8_1d_i. [treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i. @@ -17,7 +17,7 @@ [treeopen] dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_0_i. [treeopen] dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i. [sst_width] 204 -[signals_width] 264 +[signals_width] 302 [sst_expanded] 1 [sst_vpaned_height] 344 @c00200 @@ -93,10 +93,14 @@ dct_tests_01.y_out[23:0] dct_tests_01.dct_iv8_1d_i.y_index[2:0] @1401200 -top -@800200 +@c00200 -2d-1d @28 dct_tests_01.start +@420 +dct_tests_01.x_in[23:0] +@8420 +dct_tests_01.x_in[23:0] @22 dct_tests_01.x_out[23:0] @8420 @@ -152,7 +156,7 @@ dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.en_out dct_tests_01.dct_iv_8x8_i.dct_iv8_1d_pass1_1_i.y_index[2:0] @200 - -@1000200 +@1401200 -2d-1d @c00200 -dct_iv8_1d @@ -381,13 +385,15 @@ dct_tests_01.pre_busy_2d dct_tests_01.pre_last_in_2d dct_tests_01.pre_first_out_2d dct_tests_01.dv_2d -@22 +@420 +dct_tests_01.d_out_2d[23:0] +@8420 dct_tests_01.d_out_2d[23:0] @28 dct_tests_01.dv_2dr @22 dct_tests_01.d_out_2dr[23:0] -@8420 +@8421 dct_tests_01.d_out_2dr[23:0] @200 - @@ -622,7 +628,7 @@ dct_tests_01.dct_iv_8x8_i.dctv_out_run_2 dct_tests_01.dct_iv_8x8_i.dctv_out_ra_2[6:0] @420 dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0] -@8421 +@8420 dct_tests_01.dct_iv_8x8_i.dctv_out_reg_2[23:0] @22 dct_tests_01.dct_iv_8x8_i.dctv_out_debug_reg_2[2:0] diff --git a/dsp/dct_iv.ods b/dsp/dct_iv.ods index 6d256b7f472248552ae39627f0aa3965b407e248..66e767931dc4b6df0660eb57ef9dd6c38f5288a2 100644 Binary files a/dsp/dct_iv.ods and b/dsp/dct_iv.ods differ diff --git a/dsp/dct_iv8_1d.v b/dsp/dct_iv8_1d.v index 548c9815f4a347dc15e375e8350cb8b4b99ef21b..bdb8a06af448549c5494db570d618f5af083bd0a 100644 --- a/dsp/dct_iv8_1d.v +++ b/dsp/dct_iv8_1d.v @@ -75,9 +75,6 @@ module dct_iv8_1d#( output reg [2:0] y_index // for simulation - valid with dout - index of the data output ); -// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-* -// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-* -// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-* localparam RSHIFT1 = 2; // safe right shift for stage 1 localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates @@ -172,7 +169,6 @@ module dct_iv8_1d#( end end - //register files assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra]; assign dsp_din_2 = dsp_din_2_ram[dsp_din_2_ra]; diff --git a/dsp/dct_iv_8x8.v b/dsp/dct_iv_8x8.v index 28a74bcaf5a382cfd156a4a5088033831491ac41..fc13c73d6dc19edca064c59e791a4996f1a26c93 100644 --- a/dsp/dct_iv_8x8.v +++ b/dsp/dct_iv_8x8.v @@ -41,8 +41,8 @@ module dct_iv_8x8#( parameter INPUT_WIDTH = 25, parameter OUT_WIDTH = 25, - parameter OUT_RSHIFT1 = 3, // overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation) - parameter OUT_RSHIFT2 = 0, // overall right shift of the result from input, aligned by MSB for pass2 (>=3 will never cause saturation) + parameter OUT_RSHIFT1 = 1, // overall right shift of the result from input, aligned by MSB for pass1 (>=3 will never cause saturation) + parameter OUT_RSHIFT2 = 1, // if sum OUT_RSHIFT1+OUT_RSHIFT2 == 2, direct*reverse == ident (may use 3, -1) or 3,0 with wider output and saturate parameter TRANSPOSE_WIDTH = 25, // transpose memory width parameter DSP_B_WIDTH = 18, parameter DSP_A_WIDTH = 25, @@ -76,6 +76,9 @@ module dct_iv_8x8#( // 3. common transpose memory plus 2 input reorder memory for each of the vertical DCT // 4. 2 of the vertical DCTs // 5. small memory to combine/reorder outputs (2 stages as 1 x16 memory is not enough) +// TODO make a version that uses common transpose memory (twice width) and simultaneously calculates dst-iv (invert time sequence, alternate sign) +// That can be used for lateral chromatic aberration (shift in time domain). Reverse transform does not need it - will always be just dct-iv + reg x_run; reg [5:0] x_wa; wire dcth_phin_start = x_run && (x_wa[5:0] == 6); diff --git a/dsp/dct_tests_01.tf b/dsp/dct_tests_01.tf index b66032488ea3486f028eedf38501d69e0ad52c35..e1256fdf3fbe65728bc5853850fa96204f0e52c5 100644 --- a/dsp/dct_tests_01.tf +++ b/dsp/dct_tests_01.tf @@ -66,7 +66,7 @@ module dct_tests_01 (); // parameter OUT_WIDTH = 16; // output data width parameter OUT_WIDTH = 24; // output data width parameter TRANSPOSE_WIDTH = 24; // width of the transpose memory (intermediate results) - parameter OUT_RSHIFT = 3; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation) + parameter OUT_RSHIFT = 2; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation) parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass parameter DCT_GAP = 16; // between runs @@ -96,9 +96,9 @@ module dct_tests_01 (); reg start = 0; reg start2 = 0; // second start for 2d - wire [OUT_WIDTH-1:0] y_dct; // S uppressThisWarning VEditor - simulation only - wire pre2_start_out; // S uppressThisWarning VEditor - simulation only - wire en_out; // S uppressThisWarning VEditor - simulation only + wire [OUT_WIDTH-1:0] y_dct; + wire pre2_start_out; + wire en_out; reg y_pre_we; reg y_we; @@ -111,21 +111,20 @@ module dct_tests_01 (); reg signed [WIDTH-1:0] data_in[0:63]; reg signed [OUT_WIDTH-1:0] data_out[0:63]; - reg signed [WIDTH-1:0] d_in; - wire pre_last_in_2d; - wire pre_first_out_2d; - wire pre_busy_2d; - wire dv_2d; + wire pre_last_in_2d; // SuppressThisWarning VEditor - simulation only + wire pre_first_out_2d; // SuppressThisWarning VEditor - simulation only + wire pre_busy_2d; // SuppressThisWarning VEditor - simulation only + wire dv_2d; // SuppressThisWarning VEditor - simulation only wire signed [OUT_WIDTH-1:0] d_out_2d; - wire pre_last_in_2dr; - wire pre_first_out_2dr; - wire pre_busy_2dr; - wire dv_2dr; - wire signed [OUT_WIDTH-1:0] d_out_2dr; + wire pre_last_in_2dr; // SuppressThisWarning VEditor - simulation only + wire pre_first_out_2dr; // SuppressThisWarning VEditor - simulation only + wire pre_busy_2dr; // SuppressThisWarning VEditor - simulation only + wire dv_2dr; // SuppressThisWarning VEditor - simulation only + wire signed [OUT_WIDTH-1:0] d_out_2dr; // SuppressThisWarning VEditor - simulation only - integer i,j, i1, j1; + integer i,j, i1; initial begin for (i=0; i<64; i=i+1) begin `ifdef DCT_INPUT_UNITY