Commit 2ad4b0cf authored by Andrey Filippov's avatar Andrey Filippov

split system_defines.vh into versions, changed to vospi (lepton), fpga version 0393013a

parent 713cc74a
...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h0393401b; // same as 0393401a with updated histograms saxigp0 (not used, just testing it did not break) parameter FPGA_VERSION = 32'h0393013a; // Adding IMU to Lepton
// parameter FPGA_VERSION = 32'h0393401b; // same as 0393401a with updated histograms saxigp0 (not used, just testing it did not break)
// parameter FPGA_VERSION = 32'h03931017; // restoring both saxigp clocks to 150MHz (from 100 MHz) - OK, pushed, xclk slightly timing not matched // parameter FPGA_VERSION = 32'h03931017; // restoring both saxigp clocks to 150MHz (from 100 MHz) - OK, pushed, xclk slightly timing not matched
// parameter FPGA_VERSION = 32'h03931016; // debugging histograms - MOD_SAXI on, restore actual histogram data (works, pushed to git) // parameter FPGA_VERSION = 32'h03931016; // debugging histograms - MOD_SAXI on, restore actual histogram data (works, pushed to git)
// parameter FPGA_VERSION = 32'h03931015; // debugging histograms - MOD_SAXI on, fixed some bugs related to inactive cycle with page_ra == 8'hff - works? // parameter FPGA_VERSION = 32'h03931015; // debugging histograms - MOD_SAXI on, fixed some bugs related to inactive cycle with page_ra == 8'hff - works?
......
...@@ -945,7 +945,7 @@ module sensors393 #( ...@@ -945,7 +945,7 @@ module sensors393 #(
`ifndef LWIR `ifndef LWIR
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"), .IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
`endif ///`endif
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
...@@ -1024,6 +1024,7 @@ module sensors393 #( ...@@ -1024,6 +1024,7 @@ module sensors393 #(
.UART_STOP_BITS (UART_STOP_BITS), // 1) .UART_STOP_BITS (UART_STOP_BITS), // 1)
.UART_EXTIF_MODE (UART_EXTIF_MODE), // 1) .UART_EXTIF_MODE (UART_EXTIF_MODE), // 1)
`endif `endif
`endif // `ifndef LWIR
`ifdef DEBUG_RING `ifdef DEBUG_RING
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY), .DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
......
/*!
* @file system_defines.vh
* @date 2015-02-28
* @author Andrey Filippov
*
* @brief Preprocessor macros definitions to be included in the project
* These defines specify overall configuration of the system, set type
* of the sensor interface and more.
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define DEBUG_HISTOGRAMS
// TODO: Later compare instantiate/infer
`define INSTANTIATE_DSP48E1 // not yet tesetd/debugged otherwise
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE // ======== WTF? ======== is undefined in synthesis mode
`define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT
// Parameters from x393_sata project
`define USE_DRP
`define ALIGN_CLOCKS
// `define STRAIGHT_XCLK
`define USE_DATASCOPE
// `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS
// `define AHCI_SATA 1
// `define DEBUG_ELASTIC
// End of parameters from x393_sata project
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
`define BOSON 1
`define BOSON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON"
// `define LWIR
// `define HISPI
// also change in bitstream, utilization and timimg summary tools (x393_parallel_utilization.report, ...)
`ifdef BOSON
`elsif LWIR
`elsif HISPI
`else
`define PAR12 1 // use default sensors interface
`endif
`ifdef BOSON
`define PCLK_MASTER /* pclk is generated by the sensors, no global pclk and prst!*/
`endif
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
`define REVERSE_LANES 1
`define DEBUG_RING 1
`define USE_HARD_CURPARAMS // Adjustment of actual hardware may break simulation
// `define DEBUG_SENS_MEM_PAGES 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
// `define sg15E 1
// `define sg187E 1
`define den4096Mb 1
`define MCLK_VCO_MULT 16
// `define MCLK_VCO_MULT 18
// `define MCLK_VCO_MULT 20
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif
`ifdef COCOTB
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif
`ifdef CVC
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif // CVC
`ifndef SIMULATION
`undef DEBUG_COMPRESSOR_SCRAMBLE
`undef DEBUG_DCT1D // undefine after debugging is over
`endif
// will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch
`undef INFER_LATCHES
// define when using CDC - it does not support them
`undef IGNORE_ATTR
//`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
// chn 7 is disabled
`undef def_enable_mem_chn7
// chn 8 is scanline w (sensor channel 0)
`define def_enable_mem_chn8
`undef def_read_mem_chn8
`define def_write_mem_chn8
`define def_scanline_chn8
`undef def_tiled_chn8
// chn 9 is scanline w (sensor channel 1)
`define def_enable_mem_chn9
`undef def_read_mem_chn9
`define def_write_mem_chn9
`define def_scanline_chn9
`undef def_tiled_chn9
// chn 10 is scanline w (sensor channel 2)
`define def_enable_mem_chn10
`undef def_read_mem_chn10
`define def_write_mem_chn10
`define def_scanline_chn10
`undef def_tiled_chn10
// chn 11 is scanline w (sensor channel 3)
`define def_enable_mem_chn11
`undef def_read_mem_chn11
`define def_write_mem_chn11
`define def_scanline_chn11
`undef def_tiled_chn11
// chn 12 is tiled read + scanline read (for Tiff) (compressor channel 0)
`define def_enable_mem_chn12
`define def_read_mem_chn12
`undef def_write_mem_chn12
`define def_scanline_chn12
`define def_tiled_chn12
// chn 13 is tiled read + scanline read (for Tiff) (compressor channel 1)
`define def_enable_mem_chn13
`define def_read_mem_chn13
`undef def_write_mem_chn13
`define def_scanline_chn13
`define def_tiled_chn13
// chn 14 is tiled read + scanline read (for Tiff) (compressor channel 2)
`define def_enable_mem_chn14
`define def_read_mem_chn14
`undef def_write_mem_chn14
`define def_scanline_chn14
`define def_tiled_chn14
// chn 15 is tiled read + scanline read (for Tiff) (compressor channel 3)
`define def_enable_mem_chn15
`define def_read_mem_chn15
`undef def_write_mem_chn15
`define def_scanline_chn15
`define def_tiled_chn15
`endif
\ No newline at end of file
...@@ -65,10 +65,10 @@ ...@@ -65,10 +65,10 @@
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels // if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/ /*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
`define BOSON 1 // `define BOSON 1
`define BOSON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON" // `define BOSON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON"
// `define LWIR `define LWIR 1
// `define HISPI // `define HISPI
// also change in bitstream, utilization and timimg summary tools (x393_parallel_utilization.report, ...) // also change in bitstream, utilization and timimg summary tools (x393_parallel_utilization.report, ...)
`ifdef BOSON `ifdef BOSON
......
/*!
* @file system_defines.vh
* @date 2015-02-28
* @author Andrey Filippov
*
* @brief Preprocessor macros definitions to be included in the project
* These defines specify overall configuration of the system, set type
* of the sensor interface and more.
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define DEBUG_HISTOGRAMS
// TODO: Later compare instantiate/infer
`define INSTANTIATE_DSP48E1 // not yet tesetd/debugged otherwise
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE // ======== WTF? ======== is undefined in synthesis mode
`define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT
// Parameters from x393_sata project
`define USE_DRP
`define ALIGN_CLOCKS
// `define STRAIGHT_XCLK
`define USE_DATASCOPE
// `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS
// `define AHCI_SATA 1
// `define DEBUG_ELASTIC
// End of parameters from x393_sata project
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
// `define BOSON 1
// `define BOSON_REVA 1 /* 103993 REVA board*/ // need to comment both - TCL recognizes as "BO-SON"
`define LWIR 1
// `define HISPI
// also change in bitstream, utilization and timimg summary tools (x393_parallel_utilization.report, ...)
`ifdef BOSON
`elsif LWIR
`elsif HISPI
`else
`define PAR12 1 // use default sensors interface
`endif
`ifdef BOSON
`define PCLK_MASTER /* pclk is generated by the sensors, no global pclk and prst!*/
`endif
`define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
`define REVERSE_LANES 1
`define DEBUG_RING 1
`define USE_HARD_CURPARAMS // Adjustment of actual hardware may break simulation
// `define DEBUG_SENS_MEM_PAGES 1
// `define MCLK_VCO_MULT 16
// DDR3 memory speed grade and density
`define sg25 1
// `define sg15E 1
// `define sg187E 1
`define den4096Mb 1
`define MCLK_VCO_MULT 16
// `define MCLK_VCO_MULT 18
// `define MCLK_VCO_MULT 20
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif
`ifdef COCOTB
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif
`ifdef CVC
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif // CVC
`ifndef SIMULATION
`undef DEBUG_COMPRESSOR_SCRAMBLE
`undef DEBUG_DCT1D // undefine after debugging is over
`endif
// will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch
`undef INFER_LATCHES
// define when using CDC - it does not support them
`undef IGNORE_ATTR
//`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
// chn 7 is disabled
`undef def_enable_mem_chn7
// chn 8 is scanline w (sensor channel 0)
`define def_enable_mem_chn8
`undef def_read_mem_chn8
`define def_write_mem_chn8
`define def_scanline_chn8
`undef def_tiled_chn8
// chn 9 is scanline w (sensor channel 1)
`define def_enable_mem_chn9
`undef def_read_mem_chn9
`define def_write_mem_chn9
`define def_scanline_chn9
`undef def_tiled_chn9
// chn 10 is scanline w (sensor channel 2)
`define def_enable_mem_chn10
`undef def_read_mem_chn10
`define def_write_mem_chn10
`define def_scanline_chn10
`undef def_tiled_chn10
// chn 11 is scanline w (sensor channel 3)
`define def_enable_mem_chn11
`undef def_read_mem_chn11
`define def_write_mem_chn11
`define def_scanline_chn11
`undef def_tiled_chn11
// chn 12 is tiled read + scanline read (for Tiff) (compressor channel 0)
`define def_enable_mem_chn12
`define def_read_mem_chn12
`undef def_write_mem_chn12
`define def_scanline_chn12
`define def_tiled_chn12
// chn 13 is tiled read + scanline read (for Tiff) (compressor channel 1)
`define def_enable_mem_chn13
`define def_read_mem_chn13
`undef def_write_mem_chn13
`define def_scanline_chn13
`define def_tiled_chn13
// chn 14 is tiled read + scanline read (for Tiff) (compressor channel 2)
`define def_enable_mem_chn14
`define def_read_mem_chn14
`undef def_write_mem_chn14
`define def_scanline_chn14
`define def_tiled_chn14
// chn 15 is tiled read + scanline read (for Tiff) (compressor channel 3)
`define def_enable_mem_chn15
`define def_read_mem_chn15
`undef def_write_mem_chn15
`define def_scanline_chn15
`define def_tiled_chn15
`endif
\ No newline at end of file
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Mon May 20 11:20:59 2019 | Date : Sun Apr 23 14:10:04 2023
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS | Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report | Command : report_utilization -file vivado_build/x393_vospi.utilization_report
| Design : x393 | Design : x393
| Device : 7z030fbg484-1 | Device : 7z030fbg484-1
| Design State : Routed | Design State : Routed
...@@ -31,15 +31,15 @@ Table of Contents ...@@ -31,15 +31,15 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42162 | 0 | 78600 | 53.64 | | Slice LUTs | 42158 | 0 | 78600 | 53.64 |
| LUT as Logic | 38807 | 0 | 78600 | 49.37 | | LUT as Logic | 38795 | 0 | 78600 | 49.36 |
| LUT as Memory | 3355 | 0 | 26600 | 12.61 | | LUT as Memory | 3363 | 0 | 26600 | 12.64 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2810 | 0 | | |
| LUT as Shift Register | 553 | 0 | | | | LUT as Shift Register | 553 | 0 | | |
| Slice Registers | 54240 | 0 | 157200 | 34.50 | | Slice Registers | 54499 | 0 | 157200 | 34.67 |
| Register as Flip Flop | 54240 | 0 | 157200 | 34.50 | | Register as Flip Flop | 54499 | 0 | 157200 | 34.67 |
| Register as Latch | 0 | 0 | 157200 | 0.00 | | Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 | | F7 Muxes | 58 | 0 | 39300 | 0.15 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 | | F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
...@@ -57,9 +57,9 @@ Table of Contents ...@@ -57,9 +57,9 @@ Table of Contents
| 0 | _ | Reset | - | | 0 | _ | Reset | - |
| 0 | Yes | - | - | | 0 | Yes | - | - |
| 8 | Yes | - | Set | | 8 | Yes | - | Set |
| 680 | Yes | - | Reset | | 685 | Yes | - | Reset |
| 1109 | Yes | Set | - | | 1120 | Yes | Set | - |
| 52443 | Yes | Reset | - | | 52686 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
...@@ -69,27 +69,27 @@ Table of Contents ...@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16575 | 0 | 19650 | 84.35 | | Slice | 16859 | 0 | 19650 | 85.80 |
| SLICEL | 10941 | 0 | | | | SLICEL | 11111 | 0 | | |
| SLICEM | 5634 | 0 | | | | SLICEM | 5748 | 0 | | |
| LUT as Logic | 38807 | 0 | 78600 | 49.37 | | LUT as Logic | 38795 | 0 | 78600 | 49.36 |
| using O5 output only | 3 | | | | | using O5 output only | 4 | | | |
| using O6 output only | 30134 | | | | | using O6 output only | 30105 | | | |
| using O5 and O6 | 8670 | | | | | using O5 and O6 | 8686 | | | |
| LUT as Memory | 3355 | 0 | 26600 | 12.61 | | LUT as Memory | 3363 | 0 | 26600 | 12.64 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2810 | 0 | | |
| using O5 output only | 2 | | | | | using O5 output only | 2 | | | |
| using O6 output only | 84 | | | | | using O6 output only | 108 | | | |
| using O5 and O6 | 2716 | | | | | using O5 and O6 | 2700 | | | |
| LUT as Shift Register | 553 | 0 | | | | LUT as Shift Register | 553 | 0 | | |
| using O5 output only | 275 | | | | | using O5 output only | 268 | | | |
| using O6 output only | 227 | | | | | using O6 output only | 233 | | | |
| using O5 and O6 | 51 | | | | | using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24469 | 0 | 78600 | 31.13 | | LUT Flip Flop Pairs | 24618 | 0 | 78600 | 31.32 |
| fully used LUT-FF pairs | 4529 | | | | | fully used LUT-FF pairs | 4524 | | | |
| LUT-FF pairs with one unused LUT output | 17760 | | | | | LUT-FF pairs with one unused LUT output | 17869 | | | |
| LUT-FF pairs with one unused Flip Flop | 17622 | | | | | LUT-FF pairs with one unused Flip Flop | 17828 | | | |
| Unique Control Sets | 4810 | | | | | Unique Control Sets | 4753 | | | |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets. * Note: Review the Control Sets Report for more information regarding control sets.
...@@ -196,28 +196,29 @@ Table of Contents ...@@ -196,28 +196,29 @@ Table of Contents
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| FDRE | 52443 | Flop & Latch | | FDRE | 52686 | Flop & Latch |
| LUT3 | 11395 | LUT | | LUT3 | 11432 | LUT |
| LUT6 | 10215 | LUT | | LUT6 | 10240 | LUT |
| LUT2 | 8461 | LUT | | LUT2 | 8311 | LUT |
| LUT4 | 7997 | LUT | | LUT4 | 8026 | LUT |
| LUT5 | 7805 | LUT | | LUT5 | 7863 | LUT |
| RAMD32 | 4126 | Distributed Memory | | RAMD32 | 4102 | Distributed Memory |
| CARRY4 | 2733 | CarryLogic | | CARRY4 | 2749 | CarryLogic |
| LUT1 | 1604 | LUT | | LUT1 | 1609 | LUT |
| RAMS32 | 1392 | Distributed Memory | | RAMS32 | 1384 | Distributed Memory |
| FDSE | 1109 | Flop & Latch | | FDSE | 1120 | Flop & Latch |
| FDCE | 680 | Flop & Latch | | FDCE | 685 | Flop & Latch |
| SRL16E | 496 | Distributed Memory | | SRL16E | 497 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory | | SRLC32E | 108 | Distributed Memory |
| IBUF | 99 | IO | | IBUF | 99 | IO |
| OBUFT | 97 | IO | | OBUFT | 97 | IO |
| DSP48E1 | 76 | Block Arithmetic | | DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 62 | Block Memory | | RAMB18E1 | 62 | Block Memory |
| RAMB36E1 | 58 | Block Memory | | RAMB36E1 | 58 | Block Memory |
| MUXF7 | 58 | MuxFx |
| OSERDESE2 | 43 | IO | | OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO | | ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 34 | MuxFx | | RAMD64E | 24 | Distributed Memory |
| OBUFT_DCIEN | 18 | IO | | OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO | | IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO | | IBUF_IBUFDISABLE | 18 | IO |
......
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