added hardwired option for x393_cur_params_target.vh

.settings/com.elphel.vdt.VivadoBitstream.prefs

@@ -3,6 +3,6 @@ VivadoBitstream_105_force=true
 VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
 VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
 VivadoBitstream_124_force=true
-VivadoBitstream_124_rawfile=x393_parallel
+VivadoBitstream_124_rawfile=x393_hispi
 com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
 eclipse.preferences.version=1

fpga_version.vh

@@ -31,7 +31,8 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  *******************************************************************************/
-          parameter FPGA_VERSION =          32'h03930095;    // parallel  -0.068/-0.342/5 82.38%
+          parameter FPGA_VERSION =          32'h03930096;    // serial, next
+//          parameter FPGA_VERSION =          32'h03930095;    // parallel  -0.068/-0.342/5 82.38%
 //          parameter FPGA_VERSION =          32'h03930094;    // hispi, disabling debug  -0.187/-1.252/16 84.14%  
 //        parameter FPGA_VERSION =          32'h03930093;    // hispi, masking sensor data to memory buffer, debug still on
 //        parameter FPGA_VERSION =          32'h03930092;    // hispi, even more debugging memory pages sens-> memory

system_defines.vh

@@ -48,13 +48,13 @@
   `define PRELOAD_BRAMS
   `define DISPLAY_COMPRESSED_DATA  
   // if HISPI is not defined, parallel sensor interface is used for all channels
-//  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
+  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
 //    `define USE_OLD_XDCT393  
 //  `define USE_PCLK2X
 //  `define USE_XCLK2X
   `define REVERSE_LANES 1
   `define DEBUG_RING 1
-  
+  `define USE_HARD_CURPARAMS // Adjustment of actual hardware may break simulation
 //  `define DEBUG_SENS_MEM_PAGES 1   
 //  `define MCLK_VCO_MULT 16
 // DDR3 memory speed grade and density

x393_testbench03.tf

@@ -98,7 +98,18 @@ module  x393_testbench03 #(
 `define DEBUG_RD_DATA 1  
 
 //`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
-`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
+// *** Adjusting includes/x393_cur_params_target.vh by the hardware may break simulation, hard-wired parameters below are tested ***
+`ifdef USE_HARD_CURPARAMS
+    localparam  DLY_LANE0_ODELAY =  80'hd85c1014141814181218;
+    localparam  DLY_LANE0_IDELAY =  72'h2c7a8380897c807b88;
+    localparam  DLY_LANE1_ODELAY =  80'hd8581812181418181814;
+    localparam  DLY_LANE1_IDELAY =  72'h108078807a887c8280;
+    localparam          DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
+    localparam         DLY_PHASE =   8'h33;
+`else
+    `include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
+`endif
+
 parameter TRIGGER_MODE =          0; // 1;     // 0 - auto, 1 - triggered
 parameter EXT_TRIGGER_MODE =      1 ;    // 0 - internal, 1 - external trigger (camsync)
 parameter EXTERNAL_TIMESTAMP =    0; // 1 ;    // embed local timestamp, 1 - embed received timestamp