Commit 16bc2093 authored by Andrey Filippov's avatar Andrey Filippov

restored settins for tghe x393 simulation (from dct-iv)

parent 69ef600d
FPGA_project_@_DUTTopFile=cocotb/x393_dut.v FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
FPGA_project_@_DUTTopModule=x393_dut FPGA_project_@_DUTTopModule=x393_dut
FPGA_project_@_ImplementationTopFile=x393.v FPGA_project_@_ImplementationTopFile=x393.v
FPGA_project_@_SimulationTopFile=dsp/dct_tests_01.tf FPGA_project_@_SimulationTopFile=x393_testbench03.tf
FPGA_project_@_SimulationTopModule=dct_tests_01 FPGA_project_@_SimulationTopModule=x393_testbench03
FPGA_project_@_part=xc7z030fbg484-1 FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@-> com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0 com.elphel.store.version.FPGA_project=1.0
......
com.elphel.store.context.iverilog=iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
com.elphel.store.version.iverilog=1.1 com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_@_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=dct_tests_01.sav iverilog_@_GTKWaveSavFile=x393_testbench04.sav
iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@-> iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_@_SaveLogsPreprocessor=false iverilog_@_SaveLogsPreprocessor=false
iverilog_@_SaveLogsSimulator=true iverilog_@_SaveLogsSimulator=true
......
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