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Commit 1434e8fb authored by Oleg Dzhimiev's avatar Oleg Dzhimiev
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Merge branch 'lwir' of https://git.elphel.com/Elphel/x393 into lwir

parents f3e1a3d2 c4db5df9
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Showing with 4378 additions and 300 deletions
cocotb/x393_cocotb_lwir_04.sav
View file @ 1434e8fb
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Fri Apr 19 05:17:10 2019
[*] Thu Apr 25 23:42:15 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190418181641542.fst"
[dumpfile_mtime] "Fri Apr 19 04:43:12 2019"
[dumpfile_size] 1314203898
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190425172733675.fst"
[dumpfile_mtime] "Thu Apr 25 23:38:14 2019"
[dumpfile_size] 13065486
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_lwir_04.sav"
[timestart] 949964300
[timestart] 34144200
[size] 1804 1171
[pos] -1 -1
*-12.313575 949969888 1019686803 237352388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-14.717531 34226035 1019686803 237352388 855469045 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_lwir160x120_vospi1_i.
[treeopen] x393_dut.x393_i.
......@@ -68,9 +68,11 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.crc16_x16x12x5x0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.chn1wr_buf_i.
......@@ -87,8 +89,8 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 346
[signals_width] 388
[sst_width] 204
[signals_width] 335
[sst_expanded] 1
[sst_vpaned_height] 459
@820
......@@ -3104,6 +3106,9 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_start_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_end_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.hact_r[2:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.running_good
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_stb
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.segment_good
@200
-
@28
......@@ -3155,6 +3160,18 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
@800200
-vospi_packet80_0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.will_sync
[color] 1
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.sync_end
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.last_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_invalid_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.set_id_r
[color] 2
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.sync_err
@200
-
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.pre_lsb_w
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.wcntr[6:0]
......@@ -3170,9 +3187,14 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.start
@22
@c00022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.cs_r[1:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.cs_r[1:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.cs_r[1:0]
@1401200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.spi_clken
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.spi_cs
@8022
......@@ -3206,7 +3228,15 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.d_r[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.set_id_r
@800028
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_end[2:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_end[2:0]
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_end[2:0]
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_end[2:0]
@1001200
-group_end
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_busy
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_done
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_invalid
......@@ -3218,6 +3248,8 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.packet_done
[color] 6
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.crc_err
[color] 7
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.sync_err
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.crc_r[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.crc_w[15:0]
......@@ -3232,6 +3264,73 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.den_r
@800200
-vospi_resync
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.rst
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.clk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.clken
@8022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.count_ones[4:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.count_tail[10:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.count_zeros[8:0]
@28
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.miso
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.will_sync
[color] 2
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.set_ending
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.spi_clken
[color] 7
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.spi_cs
@800022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
@28
[color] 5
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
[color] 5
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
[color] 5
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
[color] 5
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
[color] 5
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state[4:0]
@1001200
-group_end
@800022
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
@28
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
@29
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
@28
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_reset[4:0]
@1001200
-group_end
@800022
[color] 3
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
@28
[color] 3
(0)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
[color] 3
(1)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
[color] 3
(2)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
[color] 3
(3)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
[color] 3
(4)x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_resync_i.state_set[4:0]
@1001200
-group_end
@200
-
@1000200
-vospi_resync
@800200
-crc
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.vospi_segment_61_i.vospi_packet_80_i.crc16_x16x12x5x0_i.en
......@@ -3257,8 +3356,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.cmd_we
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.crc_err_r
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.crc_err_w
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.crc_reset_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.crc_reset_pclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.data_r[31:0]
@28
......@@ -3268,7 +3365,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.exp_segment[3:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.fake_in
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.fake_out
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.gpio[3:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.gpio_en[3:0]
......@@ -3337,12 +3433,10 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepto
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_miso
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_miso_int
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_mosi
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_mosi_int
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_nrst_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.spi_nrst_pclk[1:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.start_segment
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.status[13:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.status_ad[7:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_lepton3_i.status_rq
......@@ -8085,19 +8179,13 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.uncompressed
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_buf_ra[11:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_pxd[7:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_width[13:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_we
@23
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_din[63:0]
@8022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ram_512x64w_1kx32r_i.waddr[8:0]
@200
-
@800200
......
fpga_version.vh
View file @ 1434e8fb
......@@ -35,7 +35,18 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930122; // Added debug output
parameter FPGA_VERSION = 32'h0393012d; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012c; // debugging - working sync
// parameter FPGA_VERSION = 32'h0393012b; // debugging
// parameter FPGA_VERSION = 32'h0393012a; // debugging
// parameter FPGA_VERSION = 32'h03930129; // adding synchronization by discard packets
// parameter FPGA_VERSION = 32'h03930128; // output dbg_segment_stb on [7]
// parameter FPGA_VERSION = 32'h03930127; // output vsync_use, reduced sclk to 10MHz
// parameter FPGA_VERSION = 32'h03930126; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930125; // fast slew to sensor
// parameter FPGA_VERSION = 32'h03930124; // more hardware debug circuitry
// parameter FPGA_VERSION = 32'h03930123; // Implementing VSYNC/GPIO3 input
// parameter FPGA_VERSION = 32'h03930122; // Added debug output
// parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS
// parameter FPGA_VERSION = 32'h03930120; // VOSPI
// parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch
......
includes/x393_parameters.vh
View file @ 1434e8fb
......@@ -559,13 +559,17 @@
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28,
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -616,6 +620,13 @@
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
`ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
......@@ -1017,8 +1028,8 @@
parameter CLKOUT_DIV_PCLK = 2, //480 MHz // 4, // 240 MHz
parameter CLKOUT_DIV_PCLK2X = 1, //9060 MHz // 2, // 480 MHz
`else
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
parameter CLKOUT_DIV_PCLK = 96, // 10MHz // 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 48, // 20 MHz // 24, // 40 MHz
`endif
`else
......
py393/vrlg.py
View file @ 1434e8fb
......@@ -170,6 +170,7 @@ MEMBRIDGE_LEN64__TYPE = str
SENSOR_TIMING_STATUS_REG_INC = int
HISTOGRAM_ADDR_MASK__RAW = str
LOGGER_CONF_EN__RAW = str
VOSPI_IBUF_LOW_PWR__RAW = str
LWIR_TELEMETRY_AGC_LOW__TYPE = str
HIST_CONFIRM_WRITE = int
CMPRS_GROUP_ADDR__TYPE = str
......@@ -189,6 +190,7 @@ NUM_CYCLES_20__TYPE = str
SENSI2C_TBL_NBRD__TYPE = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
VOSPI_SLEW = str
CMPRS_CBIT_RUN_BITS__TYPE = str
SENSOR12BITS_TDDO1 = int
TILED_EXTRA_PAGES__RAW = str
......@@ -274,6 +276,7 @@ MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
MCONTR_LINTILE_LINEAR = int
VOSPI_VSYNC_BITS__TYPE = str
DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
......@@ -304,7 +307,6 @@ MCONTR_SENS_STATUS_BASE__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
VOSPI_NO_INVALID__RAW = str
VOSPI_FAKE_OUT__TYPE = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
......@@ -349,6 +351,7 @@ CAMSYNC_TRIG_PERIOD__TYPE = str
SENSIO_STATUS = int
DFLT_DQS_PATTERN = int
MCONTR_BUF3_RD_ADDR__RAW = str
CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
SLEW_CLK = str
......@@ -356,10 +359,10 @@ CMPRS_JP4DIFF = int
RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
SENS_GAMMA_BUFFER = int
TILED_EXTRA_PAGES__TYPE = str
FRAME_START_ADDRESS__TYPE = str
AXI_RDADDR_LATENCY = int
VOSPI_VSYNC__TYPE = str
AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int
CLK_CNTRL__RAW = str
......@@ -396,7 +399,7 @@ AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
CMDFRAMESEQ_DEPTH__TYPE = str
DLY_DM_ODELAY__RAW = str
CMPRS_FRMT_MBRM1_BITS = int
CAMSYNC_EXTERNAL_BIT = int
CMPRS_STATUS_REG_BASE__TYPE = str
......@@ -419,7 +422,6 @@ SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
DLY_DQS_ODELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
......@@ -466,6 +468,7 @@ AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK = int
SENSI2C_SLEW = str
VOSPI_DBG_SRC_BITS__RAW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
......@@ -485,7 +488,7 @@ CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str
VOSPI_NORESYNC = int
TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
......@@ -523,6 +526,7 @@ SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
GPIO_PORTEN__RAW = str
LOGGER_BIT_DURATION__RAW = str
VOSPI_DBG_SRC_BITS = int
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
......@@ -561,13 +565,14 @@ CMPRS_CBIT_BE16 = int
SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
VOSPI_VSYNC_BITS__RAW = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
CMPRS_TABLES__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
......@@ -583,6 +588,7 @@ CLKIN_PERIOD__TYPE = str
SENS_GAMMA_CTRL = int
HISPI_WAIT_ALL_LANES__TYPE = str
SENSIO_RADDR = int
VOSPI_NORESYNC_BITS__RAW = str
BUF_CLK1X_PCLK__RAW = str
LWIR_FRAME_DELAY = int
GPIO_N__TYPE = str
......@@ -599,6 +605,7 @@ MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
HISPI_FIFO_DEPTH__TYPE = str
LOGGER_CONF_SYN_BITS = int
MCONTR_CMPRS_BASE__RAW = str
NUM_CYCLES_19 = int
MULTICLK_DIV_XCLK2X = int
SENS_CTRL_GP1__TYPE = str
......@@ -615,7 +622,6 @@ NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int
HIST_SAXI_ADDR_REL__TYPE = str
SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str
......@@ -627,6 +633,7 @@ LWIR_WINDOW_WIDTH__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = long
BUF_IPCLK_SENS1__TYPE = str
VOSPI_DRIVE = int
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
......@@ -683,7 +690,7 @@ MCONTR_PHY_16BIT_PATTERNS = int
SENSOR_CTRL_ADDR_MASK__TYPE = str
CMPRS_MONO16__RAW = str
RTC_ADDR = int
MCLK_PHASE__RAW = str
VOSPI_RESET_ERR__TYPE = str
SENSIO_RADDR__TYPE = str
CLKFBOUT_MULT_PCLK__TYPE = str
CLK_ADDR__TYPE = str
......@@ -762,7 +769,7 @@ SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int
VOSPI_RESET_CRC = int
HIST_SAXI_ADDR_REL__TYPE = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int
......@@ -854,6 +861,7 @@ HISTOGRAM_RADDR_INC__TYPE = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP1 = int
FFCLK0_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_MINBITS__TYPE = str
LWIR_TELEMETRY_REV = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
SENS_GAMMA_RADDR = int
......@@ -884,6 +892,7 @@ MCONTR_LINTILE_NRESET__RAW = str
MULT_SAXI_CNTRL_MODE = int
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MULT_SAXI_ADV_WR = int
MCNTRL_SCANLINE_MASK = int
MCONTR_LINTILE_LINEAR__TYPE = str
MULTICLK_DIVCLK = int
......@@ -906,7 +915,7 @@ SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_TIMEOUT__TYPE = str
MULT_SAXI_ADV_WR = int
MCLK_PHASE__RAW = str
NUM_CYCLES_10__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
SENS_LENS_FAT0_IN__RAW = str
......@@ -976,6 +985,7 @@ CMPRS_CBIT_CMODE_RAW__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
VOSPI_VSYNC_BITS = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
......@@ -1018,6 +1028,7 @@ FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str
LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
VOSPI_IBUF_LOW_PWR__TYPE = str
CMPRS_AFIMUX_MODE__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
SENSI2C_TBL_RAH_BITS = int
......@@ -1052,6 +1063,7 @@ MULT_SAXI_ADV_RD__RAW = str
SENS_GAMMA_MODE_EN_SET__RAW = str
SENS_GAMMA_MODE_BAYER_SET__TYPE = str
T_RFC__RAW = str
VOSPI_IOSTANDARD__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
......@@ -1062,6 +1074,7 @@ LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
VOSPI_IBUF_LOW_PWR = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
......@@ -1126,7 +1139,7 @@ MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
VOSPI_MOSI__RAW = str
SENS_GAMMA_BUFFER = int
GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
......@@ -1150,8 +1163,10 @@ MCNTRL_TILED_STARTADDR = int
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
TILE_HEIGHT__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
VOSPI_DBG_SRC = int
MCNTRL_TILED_CHN4_ADDR__TYPE = str
HISPI_NUMLANES__TYPE = str
VOSPI_DBG_SRC__RAW = str
HISPI_FIFO_START = int
TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
......@@ -1162,7 +1177,6 @@ VOSPI_SEGM0_OK__TYPE = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
DLY_DM_ODELAY__RAW = str
CMPRS_STATUS_REG_BASE__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
......@@ -1193,8 +1207,8 @@ MULT_SAXI_IRQLEN_ADDR = int
XOR_HIST_BAYER = int
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
VOSPI_VSYNC__RAW = str
CLKFBOUT_PHASE_SENSOR__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
MCONTR_SENS_BASE = int
CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
......@@ -1202,9 +1216,11 @@ MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
VOSPI_IOSTANDARD = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
VOSPI_SLEW__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
VOSPI_OUT_EN_SINGL__TYPE = str
......@@ -1288,6 +1304,7 @@ CMPRS_FRMT_MBRM1__RAW = str
MCONTR_SENS_BASE__TYPE = str
LOGGER_BIT_HALF_PERIOD = int
CMPRS_CBIT_CMODE_JP4 = int
VOSPI_DRIVE__RAW = str
CAMSYNC_TRIGGERED_BIT = int
VOSPI_SPI_CLK_BITS__RAW = str
LOGGER_PAGE_IMU__TYPE = str
......@@ -1331,6 +1348,7 @@ CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
VOSPI_SLEW__TYPE = str
GPIO_SET_PINS = int
FRAME_START_ADDRESS__RAW = str
LOGGER_BIT_DURATION = int
......@@ -1423,13 +1441,14 @@ MCNTRL_TILED_STATUS_CNTRL__RAW = str
CMPRS_CBIT_BAYER__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
SENSIO_JTAG__TYPE = str
VOSPI_NORESYNC__RAW = str
SENSOR_GROUP_ADDR__RAW = str
LOGGER_MASK__TYPE = str
T_RFC = int
FFCLK1_IOSTANDARD__RAW = str
CMD_DONE_BIT__TYPE = str
SENSOR_DATA_WIDTH__TYPE = str
SENS_LENS_SCALES__RAW = str
VOSPI_RESET_ERR__RAW = str
RTC_BITC_PREDIV__RAW = str
CMPRS_CORING_BITS__TYPE = str
STATUS_DEPTH__TYPE = str
......@@ -1473,7 +1492,7 @@ LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int
IPCLK2X_PHASE__RAW = str
SENS_SYNC_MINBITS__TYPE = str
VOSPI_NORESYNC_BITS__TYPE = str
SENSI2C_IOSTANDARD__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
REFCLK_FREQUENCY__TYPE = str
......@@ -1490,6 +1509,7 @@ CMPRS_CBIT_RUN_STANDALONE__TYPE = str
BUF_IPCLK_SENS1__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
VOSPI_NO_INVALID__TYPE = str
VOSPI_DRIVE__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
......@@ -1545,6 +1565,7 @@ BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
VOSPI_VSYNC = int
MCNTRL_TEST01_CHN1_MODE__RAW = str
SLEW_CMDA__TYPE = str
MULT_SAXI_CNTRL_MODE__TYPE = str
......@@ -1568,6 +1589,7 @@ SENSOR_IMAGE_TYPE3__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
VOSPI_NORESYNC__TYPE = str
NUM_INTERRUPTS__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MEMBRIDGE_ADDR__RAW = str
......@@ -1630,6 +1652,7 @@ DLY_LANE1_IDELAY = long
HIST_SAXI_NRESET__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
CMPRS_AFIMUX_SA_LEN__TYPE = str
SENS_LENS_SCALES__RAW = str
MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
DLY_LANE0_ODELAY__TYPE = str
SENS_LENS_FAT0_IN_MASK = int
......@@ -1640,7 +1663,6 @@ MCONTR_PHY_0BIT_CKE_EN = int
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_CBIT_FRAMES__RAW = str
SLEW_DQS = str
VOSPI_MOSI__TYPE = str
MCONTR_WR_MASK = int
MCONTR_LINTILE_ABORT_LATE = int
CMPRS_FRMT_MBCM1 = int
......@@ -1682,7 +1704,6 @@ LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
VOSPI_RESET_CRC__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
......@@ -1734,6 +1755,7 @@ TABLE_CORING_INDEX__RAW = str
MCONTR_LINTILE_ABORT_LATE__TYPE = str
SENSI2C_CMD_RESET__TYPE = str
LWIR_DATA_FILE4__RAW = str
VOSPI_NORESYNC_BITS = int
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
......@@ -1749,7 +1771,7 @@ HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS = int
CMPRS_MONO8__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
SENS_LENS_FAT0_OUT__TYPE = str
CMPRS_AFIMUX_REG_ADDR0 = int
SENS_BANDWIDTH__TYPE = str
LD_DLY_LANE0_IDELAY__TYPE = str
CLKFBOUT_PHASE__RAW = str
......@@ -1982,7 +2004,7 @@ SENSOR12BITS_TMD__TYPE = str
SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str
MCONTR_CMPRS_BASE__RAW = str
VOSPI_DBG_SRC_BITS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
TEST01_SUSPEND = int
NUM_FRAME_BITS = int
......@@ -2015,6 +2037,7 @@ SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE = str
IPCLK2X_PHASE__TYPE = str
SENSOR_HIST_BITS_SET = int
VOSPI_DBG_SRC__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR = int
VOSPI_PWDN_BITS__TYPE = str
VOSPI_MCLK__TYPE = str
......@@ -2107,6 +2130,7 @@ SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
SENS_JTAG_TMS__RAW = str
VOSPI_RESET_ERR = int
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str
SENS_CTRL_MRST = int
......@@ -2125,7 +2149,7 @@ SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
VOSPI_MOSI = int
SIMULATE_CMPRS_CMODE1__TYPE = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
SENSOR_CHN_EN_BIT_SET__TYPE = str
......@@ -2166,7 +2190,7 @@ SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int
CAMSYNC_GPIO_INT_IN__RAW = str
CMPRS_CBIT_BE16__RAW = str
CAMSYNC_TRIGGERED_BIT__TYPE = str
VOSPI_IOSTANDARD__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
CMPRS_FRMT_LMARG_BITS__RAW = str
......@@ -2184,7 +2208,7 @@ CMPRS_CBIT_CMODE_MONO4__RAW = str
MULT_SAXI_MASK = int
SENS_LENS_BX_MASK__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
VOSPI_FAKE_OUT = int
CMDFRAMESEQ_DEPTH__TYPE = str
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
DLY_LANE0_IDELAY__RAW = str
HISPI_UNTUNED_SPLIT__RAW = str
......@@ -2211,7 +2235,7 @@ MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str
VOSPI_RESET_CRC__RAW = str
DFLT_REFRESH_PERIOD__RAW = str
SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
......@@ -2293,7 +2317,6 @@ BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MEMBRIDGE_LEN64 = int
HISPI_MMCM2__TYPE = str
VOSPI_FAKE_OUT__RAW = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
......@@ -2302,7 +2325,7 @@ DLY_DQ_IDELAY__RAW = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int
REF_JITTER1 = float
CONTROL_ADDR__RAW = str
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
SENSOR_16BIT_BIT_SET = int
......@@ -2550,6 +2573,7 @@ HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int
CONTROL_ADDR_MASK__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
REF_JITTER1 = float
SENSOR_BASE_INC__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
SENS_DIVCLK_DIVIDE__TYPE = str
......@@ -2568,7 +2592,7 @@ MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
CMPRS_TABLES__TYPE = str
SENS_LENS_FAT0_OUT__TYPE = str
VOSPI_SPI_CLK = int
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
......
py393/x393_export_c.py
View file @ 1434e8fb
......@@ -1890,15 +1890,14 @@ class X393ExportC(object):
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
dw.append(("fake_in", 11, 1,0, "Just to keep hardware"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by the command bit"))
dw.append(("sync_err", 11, 1,0, "At least 1 synchronization error happened since reset by the command bit"))
dw.append(("fake_in", 12, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2139,15 +2138,19 @@ class X393ExportC(object):
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("reset_err", vrlg.VOSPI_RESET_ERR, 1, 0, "Reset CRC and synchronization error status bits"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("vsync_use", vrlg.VOSPI_VSYNC, 1, 0, "Wait for the VSYNC (GPIO3). Should be enabled via i2c"))
dw.append(("vsync_use_set",vrlg.VOSPI_VSYNC+1, 1, 0, "Enable vsync_use set/reset"))
dw.append(("noresync", vrlg.VOSPI_NORESYNC, 1, 0, "Disable re-synchronization by discard packets"))
dw.append(("noresync_set", vrlg.VOSPI_NORESYNC+1, 1, 0, "Enable noresync set/reset"))
dw.append(("dbg_src", vrlg.VOSPI_DBG_SRC, 3, 0, "Hardware debug source:0-running,1-vsync_rdy[0],2-vsync_rdy[1],3-discard_segment,4-in_busy,5-out_busy,6-hact,7-sof"))
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw
def _enc_sensio_jtag(self):
......
py393/x393_sensor.py
View file @ 1434e8fb
......@@ -467,8 +467,9 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -484,8 +485,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
@return VOSPI sensor i/o control word
"""
rslt = 0
......@@ -504,7 +513,7 @@ class X393Sensor(object):
if out_single:
rslt |= 1 << vrlg.VOSPI_OUT_EN_SINGL
if reset_crc:
rslt |= 1 << vrlg.VOSPI_RESET_CRC
rslt |= 1 << vrlg.VOSPI_RESET_ERR
if not spi_clk is None:
rslt |= (2,3)[spi_clk] << vrlg.VOSPI_SPI_CLK
if not gpio0 is None:
......@@ -515,10 +524,20 @@ class X393Sensor(object):
rslt |= (gpio2 & 3) << (vrlg.VOSPI_GPIO + 4)
if not gpio3 is None:
rslt |= (gpio3 & 3) << (vrlg.VOSPI_GPIO + 6)
if fake:
rslt |= 1 << vrlg.VOSPI_FAKE_OUT
if fake:
mosi |= 1 << vrlg.VOSPI_MOSI
if not vsync_use is None:
rslt |= (2,3)[vsync_use] << vrlg.VOSPI_VSYNC
if not noresync is None:
rslt |= (2,3)[noresync] << vrlg.VOSPI_NORESYNC
if not dbg_src is None:
rslt |= ((dbg_src & (( 1 << (vrlg.VOSPI_DBG_SRC_BITS - 1)) -1 )) |
(1 << (vrlg.VOSPI_DBG_SRC_BITS - 1))) << vrlg.VOSPI_DBG_SRC
pass
# .VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 26, // source of the debug output
# .VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
return rslt
......@@ -1056,8 +1075,10 @@ class X393Sensor(object):
gpio1 = None,
gpio2 = None,
gpio3 = None,
fake = None,
mosi = None):
vsync_use = None,
noresync = None,
dbg_src = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
......@@ -1073,9 +1094,16 @@ class X393Sensor(object):
@param gpio1 = Output control for GPIO0: 1 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio2 = Output control for GPIO0: 2 - nop, 1 - set low, 2 - set high, 3 - input
@param gpio3 = Output control for GPIO0: 3 - nop, 1 - set low, 2 - set high, 3 - input
@param fake = Do not use, just for keeping hardware portsNone,
@param mosi = Do not use, just for keeping hardware portsNone,
@return VOSPI sensor i/o control word
@param vsync_use = Wait for VSYNC (should be enabled over i2c) before reading each segment
@param noresync = Disable resynchronization by discard packets
@param dbg_src = source of the hardware debug output: 0 - dbg_running
1 - vsync_rdy[0]
2 - vsync_rdy[1]
3 - discard_segment
4 - in_busy
5 - out_busy
6 - hact
7 - sof
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
......@@ -1094,8 +1122,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
return
except:
pass
......@@ -1113,8 +1142,9 @@ class X393Sensor(object):
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3,
fake = fake,
mosi = mosi)
vsync_use = vsync_use,
noresync = noresync,
dbg_src = dbg_src)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
......
sensor/sens_lepton3.v
View file @ 1434e8fb
......@@ -43,11 +43,13 @@ module sens_lepton3 #(
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
/*
parameter SENSIO_JTAG = 'h2,
parameter SENSIO_WIDTH = 'h3, // set line width (1.. 2^16) if 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
*/
parameter SENSIO_STATUS_REG = 'h21,
/*
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
......@@ -96,6 +98,11 @@ module sens_lepton3 #(
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4,
*/
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16) parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
// mode bits
parameter VOSPI_MRST = 0,
......@@ -111,15 +118,18 @@ module sens_lepton3 #(
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // pot used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -177,13 +187,23 @@ module sens_lepton3 #(
input dn6 // input reserved
);
localparam VOSPI_STATUS_BITS = 14;
localparam VOSPI_STATUS_BITS = 15;
// Status data (6 bits + 4)
wire [VOSPI_STATUS_BITS-1:0] status;
wire [ 3:0] segment_id;
wire dbg_running; // output debug output for oscilloscope
wire dbg_combined; // output debug output for oscilloscope
wire [ 7:0] dbg_sources;
reg [ 2:0] dbg_sel; // @mclk, no need to re-sync
wire dbg_running;
wire [ 1:0] dbg_vsync_rdy;
wire dbg_segment_stb;
wire dbg_will_sync;
wire [4:0] dbg_state;
wire crc_err_w; // single-cycle CRC error
reg crc_err_r; // at least one CRC error happened since reset
wire sync_err_w; // single-cycle synchronzation error
reg sync_err_r; // at least one synchronzation error happened since reset
wire in_busy;
wire out_busy;
wire [ 3:0] gpio_in; // none currently used
......@@ -192,15 +212,6 @@ module sens_lepton3 #(
wire fake_dn2; // input reserved
wire fake_dn6; // input reserved
assign status = {
fake_in,
crc_err_r,
out_busy,
in_busy,
gpio_in [3:0],
segment_id [3:0],
out_busy | in_busy, senspgm_int
};
// then re-sync to pclk (and to sns_mclk)
reg spi_nrst_mclk;
......@@ -208,11 +219,13 @@ module sens_lepton3 #(
reg segm0_ok_mclk; // from mode register?
reg out_en_mclk; // single paulse - single frame, level - continuous
wire out_en_single_mclk;
wire crc_reset_mclk;
wire err_reset_mclk;
reg lwir_mrst_mclk;
reg lwir_pwdn_mclk;
reg sns_mclk_en_mclk;
reg spi_clk_en_mclk;
reg vsync_use_mclk;
reg noresync_mclk;
wire [ 3:0] gpio_out; // only [3] may be used
wire [ 3:0] gpio_en; // none currently used
......@@ -225,8 +238,13 @@ module sens_lepton3 #(
reg [ 1:0] lwir_pwdn_pclk;
// reg [ 1:0] sns_mclk_en_pclk;
reg [ 1:0] spi_clk_en_pclk;
reg [ 1:0] vsync_use_pclk;
reg [ 1:0] noresync_pclk;
reg [ 1:0] vsync_pclk;
wire vsync;
wire out_en_single_pclk;
wire crc_reset_pclk;
wire err_reset_pclk;
// wire fake_out;
......@@ -264,11 +282,38 @@ module sens_lepton3 #(
assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int ^ fake_dp2 ^ fake_dn2 ^ fake_dn6;
assign out_en_single_mclk = set_ctrl_r && data_r[VOSPI_OUT_EN_SINGL] && !mrst;
assign crc_reset_mclk = set_ctrl_r && data_r[VOSPI_RESET_CRC] && !mrst;
/// assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT];
/// assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used
assign err_reset_mclk = set_ctrl_r && data_r[VOSPI_RESET_ERR] && !mrst;
assign prsts = prst | !lwir_mrst_pclk[1];
assign vsync = gpio_in[3];
assign status = {
fake_in,
sync_err_r,
crc_err_r,
out_busy,
in_busy,
gpio_in [3:0],
segment_id [3:0],
out_busy | in_busy, senspgm_int
};
assign dbg_combined= dbg_sel[2]?
(dbg_sel[1]?( dbg_sel[0]? dbg_sources[7]:dbg_sources[6]):( dbg_sel[0]? dbg_sources[5]: dbg_sources[4])):
(dbg_sel[1]?( dbg_sel[0]? dbg_sources[3]:dbg_sources[2]):( dbg_sel[0]? dbg_sources[1]: dbg_sources[0]));
assign dbg_sources[0] = dbg_running;
assign dbg_sources[1] = dbg_will_sync; //
assign dbg_sources[2] = dbg_vsync_rdy[1]; //
assign dbg_sources[3] = discard_segment; // dbg_state[0]; //
assign dbg_sources[4] = in_busy; // dbg_state[1]; //
assign dbg_sources[5] = out_busy; // dbg_state[2]; //
assign dbg_sources[6] = hact; // dbg_state[3]; //
assign dbg_sources[7] = sof; // dbg_state[4]; //
//dbg_will_sync dbg_state
always @(posedge mclk) begin
if (mrst) data_r <= 0;
......@@ -277,7 +322,7 @@ module sens_lepton3 #(
if (mrst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mrst) set_ctrl_r <=0;
if (mrst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mrst) spi_nrst_mclk <= 0;
......@@ -303,6 +348,17 @@ module sens_lepton3 #(
if (mrst) spi_clk_en_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_SPI_CLK + VOSPI_SPI_CLK_BITS - 1]) spi_clk_en_mclk <= data_r[VOSPI_SPI_CLK];
if (mrst) vsync_use_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_VSYNC + VOSPI_VSYNC_BITS - 1]) vsync_use_mclk <= data_r[VOSPI_VSYNC];
if (mrst) noresync_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_NORESYNC + VOSPI_NORESYNC_BITS - 1]) noresync_mclk <= data_r[VOSPI_NORESYNC];
if (mrst) dbg_sel <= 0;
else if (set_ctrl_r && data_r[VOSPI_DBG_SRC + VOSPI_DBG_SRC_BITS - 1]) dbg_sel <= data_r[VOSPI_DBG_SRC +: VOSPI_DBG_SRC_BITS-1];
end
// resync to pclk
always @ (posedge pclk) begin
......@@ -313,11 +369,18 @@ module sens_lepton3 #(
lwir_mrst_pclk[1:0] <= {lwir_mrst_pclk[0], lwir_mrst_mclk};
lwir_pwdn_pclk[1:0] <= {lwir_pwdn_pclk[0], lwir_pwdn_mclk};
spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk};
vsync_use_pclk[1:0] <= {vsync_use_pclk[0], vsync_use_mclk};
noresync_pclk[1:0] <= {noresync_pclk[0], noresync_mclk};
vsync_pclk[1:0] <= {vsync_pclk[0], vsync};
out_en_r <= out_en_single_pclk | out_en_pclk[1];
if (prst || crc_reset_pclk) crc_err_r <= 0;
if (prst || err_reset_pclk) crc_err_r <= 0;
else if (crc_err_w) crc_err_r <= 1;
if (prst || err_reset_pclk) sync_err_r <= 0;
else if (sync_err_w) sync_err_r <= 1;
end
......@@ -347,8 +410,8 @@ module sens_lepton3 #(
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (crc_reset_mclk), // input
.out_pulse (crc_reset_pclk), // output
.in_pulse (err_reset_mclk), // input
.out_pulse (err_reset_pclk), // output
.busy() // output
);
......@@ -360,8 +423,8 @@ module sens_lepton3 #(
prst_r <= prst;
end
oddr_ss #( // spi_clk
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW),
.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT (1'b0),
.SRTYPE ("SYNC")
......@@ -376,10 +439,10 @@ module sens_lepton3 #(
);
// sensor master clock (25MHz)
iobuf #( // lwir_mclk
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) lwir_mclk_i (
.O (), // output
.IO (lwir_mclk), // inout I/O pad
......@@ -388,10 +451,10 @@ module sens_lepton3 #(
);
iobuf #( // spi_miso
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) spi_miso_i (
.O (spi_miso_int), // output
.IO (spi_miso), // inout I/O pad
......@@ -400,10 +463,10 @@ module sens_lepton3 #(
);
iobuf #( // spi_mosi, not implemented in the sensor
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) spi_mosi_i (
.O (), // output - currently not used
.IO (spi_mosi), // inout I/O pad
......@@ -413,10 +476,10 @@ module sens_lepton3 #(
);
iobuf #( // spi_cs
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) spi_cs_i (
.O (), // output - currently not used
.IO (spi_cs), // inout I/O pad
......@@ -437,10 +500,10 @@ module sens_lepton3 #(
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) gpio_i (
.O (gpio_in[i]), // output - currently not used
.IO (gpio[i]), // inout I/O pad
......@@ -453,10 +516,10 @@ module sens_lepton3 #(
// for debug/test alive
iobuf #( // lwir_mrst
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) lwir_mrst_i (
.O (), // output - currently not used
.IO (lwir_mrst), // inout I/O pad
......@@ -465,51 +528,51 @@ module sens_lepton3 #(
);
iobuf #( // lwir_pwdn
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) lwir_pwdn_i (
.O (), // output - currently not used
.IO (lwir_pwdn), // inout I/O pad
.I (lwir_pwdn_pclk[0]), // input
.I (lwir_pwdn_pclk[1]), // input
.T (1'b0) // input - always on
);
// MIPI - anyway it is not implemented, IOSTANDARD not known, put just single-ended input buffers
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) mipi_dp_i (
.O(mipi_dp_int), // output - currently not used
.I(mipi_dp) // inout I/O pad
);
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) mipi_dn_i (
.O(mipi_dn_int), // output - currently not used
.I(mipi_dn) // inout I/O pad
);
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) mipi_clkp_i (
.O(mipi_clkp_int), // output - currently not used
.I(mipi_clkp) // inout I/O pad
);
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) mipi_clkn_i (
.O(mipi_clkn_int), // output - currently not used
.I(mipi_clkn) // inout I/O pad
);
iobuf #( // senspgm
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) senspgm_i (
.O (senspgm_int), // output (detection of the SFE
.IO (senspgm), // inout I/O pad
......@@ -518,10 +581,10 @@ module sens_lepton3 #(
);
iobuf #( // sns_ctl
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) sns_ctl_i (
.O (sns_ctl_int), // output - currently not used
.IO (sns_ctl), // inout I/O pad
......@@ -530,20 +593,20 @@ module sens_lepton3 #(
);
iobuf #( // sns_ctl
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
.DRIVE (VOSPI_DRIVE),
.IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.IOSTANDARD (VOSPI_IOSTANDARD),
.SLEW (VOSPI_SLEW)
) dp2_i (
.O (fake_dp2), // output - currently not used
.IO (dp2), // inout I/O pad
.I (dbg_running), // input
.I (dbg_combined), // input
.T (1'b0) // input - always on
);
/*
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) fake_dp2_i (
.O(fake_dp2),
.I(dp2)
......@@ -551,14 +614,14 @@ module sens_lepton3 #(
*/
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) fake_dn2_i (
.O(fake_dn2),
.I(dn2)
);
ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD)
.IOSTANDARD (VOSPI_IOSTANDARD)
) fake_dn6_i (
.O(fake_dn6),
.I(dn6)
......@@ -609,6 +672,9 @@ module sens_lepton3 #(
.exp_segment (exp_segment), // input[3:0]
.segm0_ok (segm0_ok_r), // input
.out_en (out_en_r), // input
.vsync (vsync_pclk[1]), // input
.vsync_use (vsync_use_pclk[1]),// input
.resync_disable (noresync_pclk[1]), // input
.spi_clken (spi_clken), // output
.spi_cs (spi_cs_int), // output
.miso (spi_miso_int), // input
......@@ -621,12 +687,15 @@ module sens_lepton3 #(
.sof (sof), // output
.eof (eof), // output
.crc_err (crc_err_w), // output
.sync_err (sync_err_w), // output
.id (segment_id), // output[3:0]
.dbg_running (dbg_running) // output debug output for oscilloscope
.dbg_running (dbg_running), // output debug output for oscilloscope
.dbg_vsync_rdy (dbg_vsync_rdy), // output[1:0]'
.dbg_segment_stb (dbg_segment_stb), // output
.dbg_will_sync (dbg_will_sync), // output
.dbg_state (dbg_state) // output[4:0]
);
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -660,35 +729,6 @@ module sens_lepton3 #(
);
// for debug/test alive kept for debug if it will be needed
/*
pulse_cross_clock pulse_cross_clock_vact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (vact_out_pre && !vact_r), // input
.out_pulse (vact_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_ext_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_ext && !hact_ext_r), // input
.out_pulse (hact_ext_a_mclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_hact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (mclk), // input
.in_pulse (hact_r && !hact_r2), // input
.out_pulse (hact_a_mclk), // output
.busy() // output
);
*/
endmodule
sensor/sensor_channel.v
View file @ 1434e8fb
......@@ -155,10 +155,14 @@ module sensor_channel#(
parameter SENS_LENS_POST_SCALE = 'h6a, // 01101010
parameter SENS_LENS_POST_SCALE_MASK = 'hff,
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
`else
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
......@@ -202,7 +206,7 @@ module sensor_channel#(
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`endif
`endif
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
......@@ -229,6 +233,11 @@ module sensor_channel#(
`ifdef HISPI
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
......@@ -242,13 +251,17 @@ module sensor_channel#(
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -259,18 +272,22 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7,
`endif
// start with comma!
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS25"
`else
// sens_parallel12 other parameters
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
,parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
......@@ -316,6 +333,9 @@ module sensor_channel#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
......@@ -981,10 +1001,13 @@ module sensor_channel#(
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
/*
.SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
*/
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
/*
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
......@@ -1024,6 +1047,11 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
*/
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1037,13 +1065,17 @@ module sensor_channel#(
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // pot used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......
sensor/sensors393.v
View file @ 1434e8fb
......@@ -156,9 +156,11 @@ module sensors393 #(
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
`else
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
......@@ -180,7 +182,6 @@ module sensors393 #(
`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
......@@ -191,7 +192,10 @@ module sensors393 #(
`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`ifdef MON_HISPI
`endif // `ifdef LWIR
`ifdef HISPI
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
......@@ -199,7 +203,8 @@ module sensors393 #(
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
`endif
`endif
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -225,6 +230,10 @@ module sensors393 #(
`ifdef HISPI
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25",
parameter VOSPI_SLEW = "FAST", // "SLOW",
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 2,
......@@ -238,13 +247,17 @@ module sensors393 #(
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_RESET_ERR = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_VSYNC = 24,
parameter VOSPI_VSYNC_BITS = 2,
parameter VOSPI_NORESYNC = 26, // disable re-sync
parameter VOSPI_NORESYNC_BITS = 2,
parameter VOSPI_DBG_SRC = 28, // source of the debug output
parameter VOSPI_DBG_SRC_BITS = 4,
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
......@@ -279,66 +292,79 @@ module sensors393 #(
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 4, // 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
parameter SENS_SYNC_MINPER = 130 // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
// start with comma
`ifdef LWIR
`else
,parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE"
`endif
// start with comma
`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
,parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter PXD_CLK_DIV_BITS = 4
`endif
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// start with comma
`ifdef LWIR
`else
.parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED" //"OPTIMIZED", "HIGH","LOW"
`endif
// start with comma
`ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS18"
`elsif HISPI
,parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18"
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
,parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25"
`endif
// parameter BUF_IPCLK = "BUFR",
// parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
// start with comma
`ifdef LWIR
`else
,parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
`endif
`ifdef HISPI
,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
......@@ -621,6 +647,8 @@ module sensors393 #(
.SENS_LENS_POST_SCALE_MASK (SENS_LENS_POST_SCALE_MASK),
.SENSIO_RADDR (SENSIO_RADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
`ifdef LWIR
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
......@@ -652,7 +680,8 @@ module sensors393 #(
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
`endif
`ifdef HISPI
`ifdef MON_HISPI
.SENSOR_TIMING_STATUS_REG_BASE (SENSOR_TIMING_STATUS_REG_BASE),
......@@ -682,6 +711,10 @@ module sensors393 #(
.NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifdef HISPI
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -695,13 +728,17 @@ module sensors393 #(
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......@@ -712,28 +749,38 @@ module sensors393 #(
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV) // 4
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY)
`endif
// start with comma
`ifdef LWIR
`else
,.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
`endif
// start with comma
`ifdef LWIR
`elsif HISPI
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......@@ -748,6 +795,8 @@ module sensors393 #(
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`endif
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
......
sensor/vospi_packet_80.v
View file @ 1434e8fb
......@@ -48,11 +48,14 @@ module vospi_packet_80#(
output spi_clken, // enable clock on spi_clk
output spi_cs, // active low
input miso, // input from the sensor
input will_sync, // discard packet detected, sync_end will follow (from resync module)
output [15:0] dout, // 16-bit data received,valid at dv and 15 cycles after
output dv, // data valid strobe
output packet_done, // packet received,
output packet_busy, // packet busy (same as spi_clken, !spi_cs)
output crc_err, // crc error, valid with packet_done
output sync_err, // synchronization error, valid with packet_done
output [15:0] id, // packet ID (0x*f** - invlaid, if packet index = 20, 4 MSb - segment (- 0 invalid)
output packet_invalid, // set early, valid with packet done
output reg id_stb // id, packet invalid are set
......@@ -66,6 +69,7 @@ module vospi_packet_80#(
reg [1:0] cs_r;
wire pre_last_w;
reg last_r;
reg [ 2:0] packet_end;
reg set_id_r;
reg set_crc_r;
......@@ -81,6 +85,11 @@ module vospi_packet_80#(
reg [15:0] id_r;
wire [15:0] dmask;
reg packet_invalid_r;
reg will_sync_d;
wire sync_end; // last bit in a packet (turn off CS/spi_clken) (from resync module)
reg sync_err_r;
assign sync_end = !will_sync && will_sync_d; // trailing edge, so will fire if disabled
assign packet_busy = cs_r[0]; // clk_en_r;
assign spi_clken = cs_r[0]; // clk_en_r;
......@@ -93,29 +102,37 @@ module vospi_packet_80#(
assign dmask = packet_header[1] ? (packet_header[0] ? 16'h0fff: 16'h0) : 16'hffff ;
assign crc_err = packet_end[2] && (crc_r != crc_w);
assign sync_err = packet_end[2] && sync_err_r;
assign dv = dv_r;
assign dout = d_r;
assign packet_invalid = packet_invalid_r;
always @ (posedge clk) begin
if (rst || packet_end[0]) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
will_sync_d <= will_sync;
/// if (rst || packet_end[0]) cs_r[0] <= 0;
if (rst || packet_end[0] || sync_end) cs_r[0] <= 0;
else if (start) cs_r[0] <= 1;
cs_r[1] <= cs_r[0];
if (rst || !cs_r[0] || packet_end[0]) bcntr <= 0;
else bcntr <= bcntr + 1;
else bcntr <= bcntr + 1; // keep running even for sync
if (rst || !cs_r[0] || packet_end[0]) lsb_r <= 0;
else lsb_r <= pre_lsb_w;
else lsb_r <= pre_lsb_w; // generate even for sync
copy_word <= !rst && lsb_r;
if (rst || !cs_r[0] || packet_end[0]) wcntr <= 0;
else if (lsb_r) wcntr <= wcntr + 1;
else if (lsb_r) wcntr <= wcntr + 1; // keep running even for sync
if (rst || !cs_r[0] ) packet_end[1:0] <= 0;
else packet_end[1:0] <= {packet_end[0], pre_last_w};
/// else packet_end[1:0] <= {packet_end[0], pre_last_w};
else packet_end[1:0] <= {packet_end[0] | sync_end, pre_last_w & ~will_sync}; // do not generate premature if running sync
if (rst) packet_end[2] <= 0;
else packet_end[2] <= packet_end[1];
......@@ -138,10 +155,18 @@ module vospi_packet_80#(
dv_r <= set_d_r && !(packet_invalid_r && VOSPI_NO_INVALID);
if (rst || start) packet_invalid_r <= 0;
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
if (rst || start) packet_invalid_r <= 0;
else if (will_sync) packet_invalid_r <= 1; // Will_sync disqualifies even started (erroneously) a good packet
else if (set_id_r) packet_invalid_r <= (d_sr[11:8] == 4'hf);
last_r <= pre_last_w;
if (rst || start) sync_err_r <= 0;
else if (sync_end && ! last_r) sync_err_r <= 1;
id_stb <= set_id_r;
if (rst || start || packet_done) packet_header <= 2'b11;
else if (copy_word) packet_header <= {packet_header[0], 1'b0};
......
sensor/vospi_resync.v 0 → 100644
View file @ 1434e8fb
/*!
* <b>Module:</b> vospi_resync
* @file vospi_resync.v
* @date 2019-04-24
* @author eyesis
*
* @brief Resynchronize vospi packets by discard packets signature
* First word starts with 0 bit, then 3 variable bits, then 0xfff
* CRC word is also 0xffff. Then ? zero words, group of 5 variable words and
* more zeros.
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* vospi_resync.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* vospi_resync.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module vospi_resync#(
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_RESYNC_ZEROS = 11 // number of 16-bit words of 0 to follow (14.6)
)(
input rst,
input clk,
input spi_clken, // enable clock on spi_clk
input spi_cs, // active low
input miso, // input from the sensor
// output sync_end, // last bit in a packet (turn off CS/spi_clken)
output will_sync, // discard packet detected, sync_end will follow
output [4:0] dbg_state
);
wire clken = spi_clken && !spi_cs;
reg [4:0] state;
reg [4:0] count_ones;
reg [8:0] count_zeros;
reg [10:0] count_tail;
// reg [1:0] ending;
wire [4:0] state_set;
wire [4:0] state_reset;
wire set_ending;
assign will_sync = state[4];
// assign sync_end = ending[0];
assign set_ending = state[4] && (count_tail == 0);
assign state_set[4] = state[3] && (count_zeros == 0) && !rst;
assign state_set[3] = state[2] && !miso && (count_ones[4:2] == 0) && !rst;
assign state_set[2] = miso && (state[1] || (state[3] && (count_zeros != 0))) && !rst;
assign state_set[1] = !miso && (state[0] || (state[2] && (count_ones[4:2] != 0)) ) && !rst;
assign state_set[0] = rst ||
(state[2] && miso && (count_ones[4:0] == 0)) || // too many ones
set_ending;
/*
assign state_reset = {state_set[0] | rst, // state[4]
state_set[4] | state_set[2] | rst, // state[3]
state_set[3] | state_set[0] | state_set[1] | rst, // state[2]
state_set[2] | rst, // state[1]
state_set[1]};
*/
assign state_reset = {|state_set[3:0] | rst, // state[4]
state_set[4] | |state_set[2:0] | rst, // state[3]
|state_set[4:3] | |state_set[1:0] | rst, // state[2]
|state_set[4:2] | state_set[0] | rst, // state[1]
|state_set[4:1]};
assign dbg_state = state;
always @ (posedge clk) if (clken) begin
if (state[2]) count_ones <= count_ones - 1;
else count_ones <= 5'h1e;
if (state[3]) count_zeros <= count_zeros - 1;
else count_zeros <= (VOSPI_RESYNC_ZEROS << 4) - 2; // 14 for VOSPI_RESYNC_ZEROS==1
if (state[4]) count_tail <= count_tail - 1;
else count_tail <= ((VOSPI_PACKET_WORDS - VOSPI_RESYNC_ZEROS) << 4) - 2; //
// if (rst) ending <= 0;
// else ending <= {ending[0], set_ending};
// if (rst) state <= 1;
// else state <= state_set | (state & ~state_reset);
end
always @ (posedge clk) begin
if (rst) state <= 1;
else if (clken) state <= state_set | (state & ~state_reset);
end
endmodule
sensor/vospi_segment_61.v
View file @ 1434e8fb
......@@ -45,7 +45,7 @@ module vospi_segment_61#(
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_LAST = 60, // with telemetry
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
......@@ -58,6 +58,10 @@ module vospi_segment_61#(
input [3:0] exp_segment, // expected segment (1,2,3,4)
input segm0_ok, // OK to read segment 0 instead of the current ( exp_segment still has to be 1..4)
input out_en, // enable frame output generation (will finish current frame if disabled, single-pulse
input vsync, // from GPIO[3], 70 usec on, period ~10ms (should be re-sampled to pclk
input vsync_use, // if set - wait for vsync to read a segment
input resync_disable, // disable re-synchronizing packets using discard signature @pclk
// input use_telemetry, // use 61- packets per segment (last segment = 60), 0 - 60 packets
// runs a single frame
// SPI signals
output spi_clken, // enable clock on spi_clk
......@@ -67,14 +71,19 @@ module vospi_segment_61#(
output in_busy, // waiting for or receiving a segment
output out_busy,
output reg segment_done, // finished receiving segment (good or bad). next after busy off
output discard_segment, // segment was disc arded
output discard_segment, // segment was discarded
output [15:0] dout, // 16-bit data received
output hact, // data valid
output sof, // start of frame
output eof, // end of frame
output crc_err, // crc error happened for any packet (valid at eos)
output sync_err, // sync error happened for any packet (valid at eos)
output [3:0] id, // segment number (valid at eos)
output dbg_running // debug output for segment_running
output dbg_running, // debug output for segment_running
output [1:0] dbg_vsync_rdy,
output dbg_segment_stb,
output dbg_will_sync,
output [ 4:0] dbg_state
);
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
......@@ -91,7 +100,7 @@ module vospi_segment_61#(
reg [ 7:0] segment_start_packet; // full packet number in a fragment for the start of the segment
reg [ 7:0] full_packet; // current full packet number in a fragment
reg [ 7:0] full_packet_verified; // next packet verified (will not be discarded later)
reg full_packet_frame; // lsb of the input frame // not needed?
/// reg full_packet_frame; // lsb of the input frame // not needed?
reg discard_set; // start discard_segment_r
wire segment_good_w; // recognized expected segment, OK to read FIFO
reg segment_good; // recognized expected segment, OK to read FIFO
......@@ -111,6 +120,7 @@ module vospi_segment_61#(
wire segment_stb;
// reg crc_err_r;
wire packet_crc_err;
wire packet_sync_err;
reg packet_start;
wire we; // write data to buffer
wire segment_done_w;
......@@ -118,6 +128,8 @@ module vospi_segment_61#(
reg segment_running; // may be discarded
reg [3:0] segment_id_r;
wire frame_in_done;
reg [1:0] vsync_rdy;
// reg packet_running; // may be discarded
assign is_first_segment_w = (exp_segment == VOSPI_SEGMENT_FIRST);
......@@ -127,7 +139,11 @@ module vospi_segment_61#(
assign segment_good_w = (segment_id == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment_r && packet_dv;
assign crc_err = packet_done && packet_crc_err; // crc_err_r;
// these errors appear as pulses
assign crc_err = packet_done && packet_crc_err; // crc_err_r;
assign sync_err = packet_done && packet_sync_err; // crc_err_r;
assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ;
assign id = segment_id_r;
assign frame_in_done = segment_done_w && last_segment_in;
......@@ -136,10 +152,33 @@ module vospi_segment_61#(
assign discard_segment= discard_segment_r; // segment was disc arded
assign dbg_running = segment_running;
assign dbg_vsync_rdy[1:0] = vsync_rdy[1:0];
assign dbg_segment_stb = segment_stb;
// To Buffer
always @ (posedge clk) begin
// if (rst) first_segment_in <= 0;
// else if (start) first_segment_in <= is_first_segment_w;
// if (rst) vsync_rdy[0] <= 0;
// else if (start) vsync_rdy[0] <= ~vsync_use; // bypass
// else if (!vsync) vsync_rdy[0] <= 1;
if (rst) vsync_rdy[0] <= 0;
else if (!vsync_use) vsync_rdy[0] <= 1;
else if (start) vsync_rdy[0] <= 0; // ~vsync_use; // bypass
else if (!vsync) vsync_rdy[0] <= 1;
if (rst) vsync_rdy[1] <= 0;
else if (!vsync_use) vsync_rdy[1] <= 1;
else if (start) vsync_rdy[1] <= 0; // ~vsync_use; // bypass
else if (vsync && vsync_rdy[0]) vsync_rdy[1] <= 1;
// vsync_rdy[1] <= !rst && !start && vsync_rdy[0] && (vsync_rdy[1] || vsync || (start_d && !vsync_use)); // 1 - OK to read packets
/// vsync_rdy[0] <= !rst && (!vsync_use || (!start));
/// vsync_rdy[1] <= !rst && (!vsync_use || (!start && vsync_rdy[0] && (vsync_rdy[1] || vsync ))); // 1 - OK to read packets
if (rst) last_segment_in <= 0;
else if (start) last_segment_in <= is_last_segment_w;
......@@ -181,15 +220,15 @@ module vospi_segment_61#(
if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
// packet_start <= !rst && !packet_busy && segment_busy_r;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
/// packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start && vsync_rdy[1];
if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr;
else if (we) waddr <= waddr + 1;
if (rst) full_packet_frame <= 0; // not needed?
else if (frame_in_done) full_packet_frame <=~full_packet_frame;
/// if (rst) full_packet_frame <= 0; // not needed?
/// else if (frame_in_done) full_packet_frame <=~full_packet_frame;
end
// From buffer, generating frame
reg out_request;
......@@ -215,7 +254,9 @@ module vospi_segment_61#(
reg [2:0] hact_r;
reg pend_eof_r;
reg [10:0] raddr;
// wire sync_end;
wire will_sync;
// wire [ 4:0] dbg_state;
assign start_out_frame_w = segment_good && is_first_segment_w && out_request;
......@@ -231,7 +272,10 @@ module vospi_segment_61#(
assign hact = hact_r[2];
assign eof = eof_r[2];
assign sof = sof_r;
assign out_busy = out_request | out_frame;
assign out_busy = resync_disable; // out_request | out_frame;
assign dbg_will_sync = will_sync;
always @ (posedge clk) begin
if (rst) hact_r <= 0;
......@@ -273,25 +317,51 @@ module vospi_segment_61#(
end
reg resync_disable_r;
wire will_sync_masked;
assign will_sync_masked = !resync_disable_r && will_sync;
always @ (posedge clk) begin
if (rst || !will_sync) resync_disable_r <= resync_disable;
end
vospi_packet_80 #(
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID) // 1
) vospi_packet_80_i (
.rst (rst), // input
.clk (clk), // input
.start (packet_start), // input
.spi_clken (spi_clken), // output
.spi_cs (spi_cs), // output
.miso (miso), // input
.will_sync (will_sync_masked),// input
.dout (packet_dout), // output[15:0]
.dv (packet_dv), // output
.packet_done (packet_done), // output
.packet_busy (packet_busy), // output
.crc_err (packet_crc_err), // output
.sync_err (packet_sync_err), // output
.id (packet_id), // output[15:0]
.packet_invalid (packet_invalid), // output - not used, processed internally, no dv generated
.id_stb (id_stb) // output reg
);
vospi_resync #(
.VOSPI_PACKET_WORDS(80),
.VOSPI_RESYNC_ZEROS(11)
) vospi_resync_i (
.rst (rst), // input
.clk (clk), // input
.start (packet_start), // input
.spi_clken (spi_clken), // output
.spi_cs (spi_cs), // output
.spi_clken (spi_clken), // input
.spi_cs (spi_cs), // input
.miso (miso), // input
.dout (packet_dout), // output[15:0]
.dv (packet_dv), // output
.packet_done (packet_done), // output
.packet_busy (packet_busy), // output
.crc_err (packet_crc_err), // output
.id (packet_id), // output[15:0]
.packet_invalid (packet_invalid), // output - not used, processed internally, no dv generated
.id_stb (id_stb) // output reg
// .sync_end (sync_end), // output
.will_sync (will_sync),
.dbg_state (dbg_state) // output[4:0]
);
ram_var_w_var_r #(
.COMMENT("vospi_segment"),
......
simulation_modules/simul_lwir160x120_vospi.v
View file @ 1434e8fb
......@@ -48,6 +48,7 @@ module simul_lwir160x120_vospi # (
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter SEGMENT_PERIOD = 5100, // min 05063? // 10000, // 236742, // 26.4 fps @25 MHz
parameter SEGMENTS_SEQ = 8, // 12 With ITAR
parameter SEGMENT_START = 7, // 0,
parameter FRAME_DELAY = 100, // mclk period to start first frame 1
parameter MS_PERIOD = 25 // ahould actually be 25000
......@@ -275,16 +276,26 @@ module simul_lwir160x120_vospi # (
`endif
`endif
integer i;
localparam DISCARD_GAP = 14;
initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0);
// reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
packet_bad[0] = 'h0f00;
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[0] = 'h0f00;
// packet_bad[1] = 'h5220; // calculate and put crc?
packet_bad[0] = 'h0fff;
packet_bad[1] = 'hffff; // calculate and put crc?
for (i = 2; i < PACKET_WORDS; i = i+1) begin
packet_bad[i] = 0;
if (i == (DISCARD_GAP + 0)) packet_bad[i] = 16'h0137;
else if (i == (DISCARD_GAP + 1)) packet_bad[i] = 16'hb7c2;
else if (i == (DISCARD_GAP + 2)) packet_bad[i] = 16'ha004;
else if (i == (DISCARD_GAP + 3)) packet_bad[i] = 16'hdd9d;
else if (i == (DISCARD_GAP + 4)) packet_bad[i] = 16'h0001;
else if (i == (DISCARD_GAP + 5)) packet_bad[i] = 16'h0001;
else packet_bad[i] = 0;
end
packet_bad[1] = 'h5220; // calculate and put crc?
// packet_bad[1] = 'h5220; // calculate and put crc?
end
always @ (posedge mclk) begin
if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
......@@ -350,7 +361,7 @@ always @ (posedge mclk) begin
if (segment_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
if (rst) segments_cntr <= 0;
if (rst) segments_cntr <= SEGMENT_START;
else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1);
......
x393.v
View file @ 1434e8fb
......@@ -1788,26 +1788,28 @@ assign axi_grst = axi_rst_pre;
.SENS_LENS_POST_SCALE_MASK (SENS_LENS_POST_SCALE_MASK),
.SENSIO_RADDR (SENSIO_RADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
`ifdef LWIR
`else
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`else
`else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif
`endif
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
`ifdef HISPI
`ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
`else
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif
`endif
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
......@@ -1815,10 +1817,11 @@ assign axi_grst = axi_rst_pre;
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI
`ifndef HISPI
.SENSIO_WIDTH (SENSIO_WIDTH),
`endif
`endif
.SENSIO_DELAYS (SENSIO_DELAYS),
`endif
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
......@@ -1836,6 +1839,10 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI
`elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
.VOSPI_IOSTANDARD (VOSPI_IOSTANDARD),
.VOSPI_SLEW (VOSPI_SLEW),
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
......@@ -1849,13 +1856,17 @@ assign axi_grst = axi_rst_pre;
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_RESET_ERR (VOSPI_RESET_ERR), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_VSYNC (VOSPI_VSYNC), // 24,
.VOSPI_VSYNC_BITS (VOSPI_VSYNC_BITS), // 2,
.VOSPI_NORESYNC (VOSPI_NORESYNC), // 26,
.VOSPI_NORESYNC_BITS (VOSPI_NORESYNC_BITS), // 2,
.VOSPI_DBG_SRC (VOSPI_DBG_SRC), // = 28, // source of the debug output
.VOSPI_DBG_SRC_BITS (VOSPI_DBG_SRC_BITS), // = 4,
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
......@@ -1887,20 +1898,30 @@ assign axi_grst = axi_rst_pre;
.SENS_SYNC_LBITS (SENS_SYNC_LBITS),
.SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT),
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER),
.IDELAY_VALUE (IDELAY_VALUE),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER)
// start with comma
`ifdef LWIR
`else
,.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
`endif
// start with comma
`ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS)
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......@@ -1922,6 +1943,9 @@ assign axi_grst = axi_rst_pre;
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
`endif
`ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
......
x393_vospi.bit
View file @ 1434e8fb
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x393_vospi.timing_summary_impl 0 → 100644
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x393_vospi_utilization.report 0 → 100644
View file @ 1434e8fb
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 25 19:12:25 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_vospi_utilization.report
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
-------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42007 | 0 | 78600 | 53.44 |
| LUT as Logic | 38653 | 0 | 78600 | 49.18 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| LUT as Shift Register | 552 | 0 | | |
| Slice Registers | 54028 | 0 | 157200 | 34.37 |
| Register as Flip Flop | 54028 | 0 | 157200 | 34.37 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 34 | 0 | 39300 | 0.09 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 8 | Yes | - | Set |
| 672 | Yes | - | Reset |
| 1025 | Yes | Set | - |
| 52323 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16758 | 0 | 19650 | 85.28 |
| SLICEL | 11056 | 0 | | |
| SLICEM | 5702 | 0 | | |
| LUT as Logic | 38653 | 0 | 78600 | 49.18 |
| using O5 output only | 4 | | | |
| using O6 output only | 30042 | | | |
| using O5 and O6 | 8607 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 |
| LUT as Distributed RAM | 2802 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | |
| LUT as Shift Register | 552 | 0 | | |
| using O5 output only | 284 | | | |
| using O6 output only | 216 | | | |
| using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24321 | 0 | 78600 | 30.94 |
| fully used LUT-FF pairs | 4523 | | | |
| LUT-FF pairs with one unused LUT output | 17611 | | | |
| LUT-FF pairs with one unused Flip Flop | 17555 | | | |
| Unique Control Sets | 4740 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 89 | 0 | 265 | 33.58 |
| RAMB36/FIFO* | 58 | 0 | 265 | 21.89 |
| RAMB36E1 only | 58 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 1 | 0 | 5 | 20.00 |
| IBUFDS | 2 | 2 | 155 | 1.29 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 18 | 18 | 250 | 7.20 |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 16 | 16 | 163 | 9.82 |
| ISERDES | 16 | 16 | | |
| OLOGIC | 48 | 48 | 163 | 29.45 |
| OUTFF_ODDR_Register | 5 | 5 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL | 11 | 0 | 32 | 34.38 |
| BUFIO | 1 | 0 | 20 | 5.00 |
| BUFIO only | 1 | 0 | | |
| MMCME2_ADV | 1 | 0 | 5 | 20.00 |
| PLLE2_ADV | 2 | 0 | 5 | 40.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 4 | 0 | 20 | 20.00 |
+--------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52323 | Flop & Latch |
| LUT3 | 11324 | LUT |
| LUT6 | 10228 | LUT |
| LUT2 | 8361 | LUT |
| LUT4 | 7952 | LUT |
| LUT5 | 7803 | LUT |
| RAMD32 | 4126 | Distributed Memory |
| CARRY4 | 2725 | CarryLogic |
| LUT1 | 1592 | LUT |
| RAMS32 | 1392 | Distributed Memory |
| FDSE | 1025 | Flop & Latch |
| FDCE | 672 | Flop & Latch |
| SRL16E | 496 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory |
| IBUF | 99 | IO |
| OBUFT | 97 | IO |
| DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 62 | Block Memory |
| RAMB36E1 | 58 | Block Memory |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 34 | MuxFx |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| ISERDESE2 | 16 | IO |
| BUFG | 11 | Clock |
| PULLUP | 8 | I/O |
| FDPE | 8 | Flop & Latch |
| ODDR | 5 | IO |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| BUFR | 4 | Clock |
| OBUF | 3 | IO |
| INV | 3 | LUT |
| PLLE2_ADV | 2 | Clock |
| OBUFTDS | 2 | IO |
| IBUFDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| MMCME2_ADV | 1 | Clock |
| IDELAYCTRL | 1 | IO |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
| BUFIO | 1 | Clock |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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