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Commit 0a580f98 authored by Andrey Filippov's avatar Andrey Filippov
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address_map.txt
View file @ 0a580f98
//0x1080..10ff - 8- bit data - to set various delay values
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h380, // address mask to generate delay load
0x1000..103f - 0- bit data (set/reset) 0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel) parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h3f0, // address mask to generate sequencer channel/run
...@@ -53,6 +57,17 @@ ...@@ -53,6 +57,17 @@
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?) parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
0x1100..11ff - 16-bit per-channel memory control
0x1100..110f - control of memory channels 0,1 - PS-controlled sequences
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
0x1100 - MCNTRL_PS_EN_RST
0x1101 - MCNTRL_PS_CMD
0x1102 - MCNTRL_PS_STATUS_CNTRL
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
// Status read address // Status read address
parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
...@@ -60,6 +75,7 @@ ...@@ -60,6 +75,7 @@
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough? parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2
================================ OLD ======================================================= ================================ OLD =======================================================
Control addresses (in original ddrc_test01) Control addresses (in original ddrc_test01)
......
memctrl/memctrl16.v
View file @ 0a580f98
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util_modules/fifo_same_clock.v
View file @ 0a580f98
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
`define DEBUG_FIFO 1 //`define DEBUG_FIFO 1
module fifo_same_clock module fifo_same_clock
#( #(
parameter integer DATA_WIDTH=16, parameter integer DATA_WIDTH=16,
...@@ -28,6 +28,7 @@ module fifo_same_clock ...@@ -28,6 +28,7 @@ module fifo_same_clock
( (
input rst, // reset, active high input rst, // reset, active high
input clk, // clock - positive edge input clk, // clock - positive edge
input sync_rst, // synchronously reset fifo;
input we, // write enable input we, // write enable
input re, // read enable input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data input [DATA_WIDTH-1:0] data_in, // input data
...@@ -72,27 +73,38 @@ module fifo_same_clock ...@@ -72,27 +73,38 @@ module fifo_same_clock
always @ (posedge clk or posedge rst) begin always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0; if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
else fill <= next_fill; else fill <= next_fill;
if (rst) wem <= 0; if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
else wem <= we; else wem <= we;
if (rst) ram_nempty <= 0; if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
else ram_nempty <= (next_fill != 0); else ram_nempty <= (next_fill != 0);
if (rst) wa <= 0; if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (wem) wa <= wa+1; else if (wem) wa <= wa+1;
if (rst) ra <= 0; if (rst) ra <= 0;
else if (sync_rst) ra <= 0;
else if (rem) ra <= ra+1; else if (rem) ra <= ra+1;
else if (!ram_nempty) ra <= wa; // Just recover from bit errors else if (!ram_nempty) ra <= wa; // Just recover from bit errors
if (rst) out_full <= 0; if (rst) out_full <= 0;
else if (sync_rst) out_full <= 0;
else if (rem && ~re) out_full <= 1; else if (rem && ~re) out_full <= 1;
else if (re && ~rem) out_full <= 0; else if (re && ~rem) out_full <= 0;
`ifdef DEBUG_FIFO `ifdef DEBUG_FIFO
if (rst) wcount <= 0; if (rst) wcount <= 0;
else if (sync_rst) wcount <= 0;
else if (we) wcount <= wcount + 1; else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0; if (rst) rcount <= 0;
else if (sync_rst) rcount <= 0;
else if (re) rcount <= rcount + 1; else if (re) rcount <= rcount + 1;
`endif `endif
end end
......
util_modules/mcont_from_chnbuf_reg.v
View file @ 0a580f98
...@@ -29,6 +29,8 @@ module mcont_from_chnbuf_reg #( ...@@ -29,6 +29,8 @@ module mcont_from_chnbuf_reg #(
input ext_buf_rd, input ext_buf_rd,
input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2 output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn, output reg buf_rd_chn,
output reg [6:0] buf_raddr_chn, output reg [6:0] buf_raddr_chn,
...@@ -45,6 +47,9 @@ module mcont_from_chnbuf_reg #( ...@@ -45,6 +47,9 @@ module mcont_from_chnbuf_reg #(
if (rst) latency_reg<= 0; if (rst) latency_reg<= 0;
else latency_reg <= buf_rd_chn | (latency_reg << 1); else latency_reg <= buf_rd_chn | (latency_reg << 1);
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end end
always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr; always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn; always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
......
util_modules/mcont_to_chnbuf_reg.v
View file @ 0a580f98
...@@ -29,6 +29,8 @@ parameter CHN_NUMBER=0 ...@@ -29,6 +29,8 @@ parameter CHN_NUMBER=0
input [6:0] ext_buf_waddr, // valid with ext_buf_wr input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
output reg buf_wr_chn, output reg buf_wr_chn,
output reg [6:0] buf_waddr_chn, output reg [6:0] buf_waddr_chn,
output reg [63:0] buf_wdata_chn output reg [63:0] buf_wdata_chn
...@@ -37,8 +39,13 @@ parameter CHN_NUMBER=0 ...@@ -37,8 +39,13 @@ parameter CHN_NUMBER=0
always @ (posedge rst or negedge clk) begin always @ (posedge rst or negedge clk) begin
if (rst) buf_chn_sel <= 0; if (rst) buf_chn_sel <= 0;
else buf_chn_sel <= (ext_buf_wchn==CHN_NUMBER); else buf_chn_sel <= (ext_buf_wchn==CHN_NUMBER);
if (rst) buf_wr_chn <= 0; if (rst) buf_wr_chn <= 0;
else buf_wr_chn <= buf_chn_sel && ext_buf_wr; else buf_wr_chn <= buf_chn_sel && ext_buf_wr;
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end end
always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
buf_waddr_chn <= ext_buf_waddr; buf_waddr_chn <= ext_buf_waddr;
......
x393.v
View file @ 0a580f98
...@@ -149,17 +149,17 @@ module x393 #( ...@@ -149,17 +149,17 @@ module x393 #(
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
parameter NUM_CYCLES_04 = 5, // 5-cycle - not yet used parameter NUM_CYCLES_04 = 4, // 4-cycle 100.013f
parameter NUM_CYCLES_05 = 6, // 6-cycle - not yet used parameter NUM_CYCLES_05 = 4, // 4-cycle 140.017f
parameter NUM_CYCLES_06 = 6, // parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 6, // parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, // parameter NUM_CYCLES_08 = 6, //
parameter NUM_CYCLES_09 = 6, // parameter NUM_CYCLES_09 = 6, //
parameter NUM_CYCLES_10 = 6, // parameter NUM_CYCLES_10 = 6, //
parameter NUM_CYCLES_11 = 6, // parameter NUM_CYCLES_11 = 6, //
parameter NUM_CYCLES_12 = 6, // parameter NUM_CYCLES_12 = 6, //
parameter NUM_CYCLES_13 = 6, // parameter NUM_CYCLES_13 = 5, // 5-cycle - not yet used
parameter NUM_CYCLES_14 = 6, // parameter NUM_CYCLES_14 = 6, // 6-cycle - not yet used
parameter NUM_CYCLES_15 = 9, // single-cycle parameter NUM_CYCLES_15 = 9, // single-cycle
// parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers // parameter STATUS_ADDR = 'h1400, // AXI write address of status read registers
...@@ -492,6 +492,7 @@ end ...@@ -492,6 +492,7 @@ end
wire channel_pgm_en0; wire channel_pgm_en0;
wire [31:0] seq_data0; wire [31:0] seq_data0;
wire seq_wr0; wire seq_wr0;
wire seq_set0;
wire seq_done0; wire seq_done0;
wire buf_wr_chn0; wire buf_wr_chn0;
wire [6:0] buf_waddr_chn0; wire [6:0] buf_waddr_chn0;
...@@ -502,6 +503,7 @@ end ...@@ -502,6 +503,7 @@ end
wire channel_pgm_en1; wire channel_pgm_en1;
wire [31:0] seq_data1; wire [31:0] seq_data1;
wire seq_wr1; wire seq_wr1;
wire seq_set1;
wire seq_done1; wire seq_done1;
wire buf_rd_chn1; wire buf_rd_chn1;
wire [6:0] buf_raddr_chn1; wire [6:0] buf_raddr_chn1;
...@@ -512,6 +514,7 @@ end ...@@ -512,6 +514,7 @@ end
wire channel_pgm_en2; wire channel_pgm_en2;
wire [31:0] seq_data2; wire [31:0] seq_data2;
wire seq_wr2; wire seq_wr2;
wire seq_set2;
wire seq_done2; wire seq_done2;
wire buf_wr_chn2; wire buf_wr_chn2;
wire [6:0] buf_waddr_chn2; wire [6:0] buf_waddr_chn2;
...@@ -522,6 +525,7 @@ end ...@@ -522,6 +525,7 @@ end
wire channel_pgm_en3; wire channel_pgm_en3;
wire [31:0] seq_data3; wire [31:0] seq_data3;
wire seq_wr3; wire seq_wr3;
wire seq_set3;
wire seq_done3; wire seq_done3;
wire buf_rd_chn3; wire buf_rd_chn3;
wire [6:0] buf_raddr_chn3; wire [6:0] buf_raddr_chn3;
...@@ -759,7 +763,8 @@ end ...@@ -759,7 +763,8 @@ end
.channel_pgm_en0 (channel_pgm_en0), // output reg .channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_data0 (seq_data0), // input[31:0] .seq_data0 (seq_data0), // input[31:0]
.seq_wr0 (seq_wr0), // input .seq_wr0 (seq_wr0), // input
.seq_done0 (seq_done0), // input .seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.buf_wr_chn0 (buf_wr_chn0), // output .buf_wr_chn0 (buf_wr_chn0), // output
.buf_waddr_chn0 (buf_waddr_chn0), // output[6:0] .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0] .buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
...@@ -769,7 +774,8 @@ end ...@@ -769,7 +774,8 @@ end
.channel_pgm_en1 (channel_pgm_en1), // output reg .channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_data1 (seq_data1), // input[31:0] .seq_data1 (seq_data1), // input[31:0]
.seq_wr1 (seq_wr1), // input .seq_wr1 (seq_wr1), // input
.seq_done1 (seq_done1), // input .seq_set1 (seq_set1), // input
.seq_done1 (seq_done1), // output
.buf_rd_chn1 (buf_rd_chn1), // output .buf_rd_chn1 (buf_rd_chn1), // output
.buf_raddr_chn1 (buf_raddr_chn1), // output[6:0] .buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0] .buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
...@@ -779,7 +785,8 @@ end ...@@ -779,7 +785,8 @@ end
.channel_pgm_en2 (channel_pgm_en2), // output reg .channel_pgm_en2 (channel_pgm_en2), // output reg
.seq_data2 (seq_data2), // input[31:0] .seq_data2 (seq_data2), // input[31:0]
.seq_wr2 (seq_wr2), // input .seq_wr2 (seq_wr2), // input
.seq_done2 (seq_done2), // input .seq_set2 (seq_set2), // input
.seq_done2 (seq_done2), // output
.buf_wr_chn2 (buf_wr_chn2), // output .buf_wr_chn2 (buf_wr_chn2), // output
.buf_waddr_chn2 (buf_waddr_chn2), // output[6:0] .buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0] .buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
...@@ -789,7 +796,8 @@ end ...@@ -789,7 +796,8 @@ end
.channel_pgm_en3 (channel_pgm_en3), // output reg .channel_pgm_en3 (channel_pgm_en3), // output reg
.seq_data3 (seq_data3), // input[31:0] .seq_data3 (seq_data3), // input[31:0]
.seq_wr3 (seq_wr3), // input .seq_wr3 (seq_wr3), // input
.seq_done3 (seq_done3), // input .seq_set3 (seq_set3), // input
.seq_done3 (seq_done3), // output
.buf_rd_chn3 (buf_rd_chn3), // output .buf_rd_chn3 (buf_rd_chn3), // output
.buf_raddr_chn3 (buf_raddr_chn3), // output[6:0] .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0] .buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
......
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