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Commit 043d4849 authored by Andrey Filippov's avatar Andrey Filippov
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working on boson implementaion, fixed old bug in python code

parent 28848f7a
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cocotb/x393_dut.v
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...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
`include "system_defines.vh" `include "system_defines.vh"
module x393_dut#( module x393_dut#(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used `include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
`include "includes/x393_simulation_parameters.vh" `include "includes/x393_simulation_parameters.vh" //SuppressThisWarning Veditor UNUSED
)( )(
output dutm0_aclk, output dutm0_aclk,
output reset_out, output reset_out,
...@@ -409,7 +409,7 @@ module x393_dut#( ...@@ -409,7 +409,7 @@ module x393_dut#(
parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 8; // 1; //8; parameter BLANK_ROWS_AFTER= 8; // 1; //8;
`endif `endif
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8; //SuppressThisWarning Veditor UNUSED
parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used
`ifdef PF `ifdef PF
...@@ -422,21 +422,21 @@ module x393_dut#( ...@@ -422,21 +422,21 @@ module x393_dut#(
`endif `endif
parameter WOI_MARGINS = 0; // 4; parameter WOI_MARGINS = 0; // 4;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK; parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK; //SuppressThisWarning Veditor UNUSED
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS; parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS; parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
// ========================== end of parameters from x353 =================================== // ========================== end of parameters from x353 ===================================
reg [639:0] TEST_TITLE="abcdef"; //SuppressThisWarning VEditor reg [639:0] TEST_TITLE="abcdef"; //SuppressThisWarning VEditor
// Sensor signals - as on sensor pads // Sensor signals - as on sensor pads
`ifdef LWIR
`elsif BOSON
`else // PAR12 od HISPI
wire PX1_MCLK; // input sensor input clock wire PX1_MCLK; // input sensor input clock
wire PX1_MRST; // input wire PX1_MRST; // input
wire PX1_ARO; // input wire PX1_ARO; // input
...@@ -485,8 +485,9 @@ module x393_dut#( ...@@ -485,8 +485,9 @@ module x393_dut#(
wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
`endif
// for LWIR - // for LWIR -
`ifdef LWIR
wire LWIR1_SPI_MISO; wire LWIR1_SPI_MISO;
wire LWIR1_SPI_MOSI; wire LWIR1_SPI_MOSI;
wire LWIR1_SPI_CS; wire LWIR1_SPI_CS;
...@@ -550,7 +551,7 @@ module x393_dut#( ...@@ -550,7 +551,7 @@ module x393_dut#(
wire LWIR4_MIPI_DN; // not implemented wire LWIR4_MIPI_DN; // not implemented
wire LWIR4_MIPI_CLKP; // not implemented wire LWIR4_MIPI_CLKP; // not implemented
wire LWIR4_MIPI_CLKN; // not implemented wire LWIR4_MIPI_CLKN; // not implemented
`endif
...@@ -596,8 +597,8 @@ module x393_dut#( ...@@ -596,8 +597,8 @@ module x393_dut#(
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock
`else `else
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
`endif `endif
`ifdef HISPI `ifdef HISPI
localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT
...@@ -695,6 +696,8 @@ module x393_dut#( ...@@ -695,6 +696,8 @@ module x393_dut#(
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7]; // same as GP[3] assign PX4_ARST = sns4_dn[7]; // same as GP[3]
assign PX4_ARO = sns4_dn[5]; // same as GP[1] assign PX4_ARO = sns4_dn[5]; // same as GP[1]
`elsif BOSON
`elsif LWIR `elsif LWIR
// connect LWIR sensor to x393 // connect LWIR sensor to x393
assign LWIR1_SPI_MOSI = sns1_dn[0]; assign LWIR1_SPI_MOSI = sns1_dn[0];
...@@ -777,7 +780,7 @@ module x393_dut#( ...@@ -777,7 +780,7 @@ module x393_dut#(
assign sns4_clkn = LWIR4_MIPI_CLKN; assign sns4_clkn = LWIR4_MIPI_CLKN;
assign sns4_clkp = LWIR4_MIPI_CLKP; assign sns4_clkp = LWIR4_MIPI_CLKP;
`else `else // only PAR12
//connect parallel12 sensor to sensor port 1 //connect parallel12 sensor to sensor port 1
assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT}; assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
...@@ -1093,6 +1096,11 @@ module x393_dut#( ...@@ -1093,6 +1096,11 @@ module x393_dut#(
.sns1_dn (sns1_dn[3:0]), // inout[3:0] .sns1_dn (sns1_dn[3:0]), // inout[3:0]
.sns1_dp74 (sns1_dp[7:4]), // inout[3:0] .sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
.sns1_dn74 (sns1_dn[7:4]), // inout[3:0] .sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns1_dp (sns1_dp[3:0]), // inout[3:0]
.sns1_dn (sns1_dn[3:0]), // inout[3:0]
.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
`elsif LWIR `elsif LWIR
.sns1_dp40 (sns1_dp[4:0]), // input[4:0] .sns1_dp40 (sns1_dp[4:0]), // input[4:0]
.sns1_dn40 (sns1_dn[4:0]), // input[4:0] .sns1_dn40 (sns1_dn[4:0]), // input[4:0]
...@@ -1116,6 +1124,11 @@ module x393_dut#( ...@@ -1116,6 +1124,11 @@ module x393_dut#(
.sns2_dn (sns2_dn[3:0]), // inout[3:0] .sns2_dn (sns2_dn[3:0]), // inout[3:0]
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0] .sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0] .sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns2_dp (sns2_dp[3:0]), // inout[3:0]
.sns2_dn (sns2_dn[3:0]), // inout[3:0]
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`elsif LWIR `elsif LWIR
.sns2_dp40 (sns2_dp[4:0]), // input[4:0] .sns2_dp40 (sns2_dp[4:0]), // input[4:0]
.sns2_dn40 (sns2_dn[4:0]), // input[4:0] .sns2_dn40 (sns2_dn[4:0]), // input[4:0]
...@@ -1141,6 +1154,11 @@ module x393_dut#( ...@@ -1141,6 +1154,11 @@ module x393_dut#(
.sns3_dn (sns3_dn[3:0]), // inout[3:0] .sns3_dn (sns3_dn[3:0]), // inout[3:0]
.sns3_dp74 (sns3_dp[7:4]), // inout[3:0] .sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
.sns3_dn74 (sns3_dn[7:4]), // inout[3:0] .sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns3_dp (sns3_dp[3:0]), // inout[3:0]
.sns3_dn (sns3_dn[3:0]), // inout[3:0]
.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
`elsif LWIR `elsif LWIR
.sns3_dp40 (sns3_dp[4:0]), // input[4:0] .sns3_dp40 (sns3_dp[4:0]), // input[4:0]
.sns3_dn40 (sns3_dn[4:0]), // input[4:0] .sns3_dn40 (sns3_dn[4:0]), // input[4:0]
...@@ -1164,6 +1182,11 @@ module x393_dut#( ...@@ -1164,6 +1182,11 @@ module x393_dut#(
.sns4_dn (sns4_dn[3:0]), // inout[3:0] .sns4_dn (sns4_dn[3:0]), // inout[3:0]
.sns4_dp74 (sns4_dp[7:4]), // inout[3:0] .sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
.sns4_dn74 (sns4_dn[7:4]), // inout[3:0] .sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
`elsif BOSON
.sns4_dp (sns4_dp[3:0]), // inout[3:0]
.sns4_dn (sns4_dn[3:0]), // inout[3:0]
.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
`elsif LWIR `elsif LWIR
.sns4_dp40 (sns4_dp[4:0]), // input[4:0] .sns4_dp40 (sns4_dp[4:0]), // input[4:0]
.sns4_dn40 (sns4_dn[4:0]), // input[4:0] .sns4_dn40 (sns4_dn[4:0]), // input[4:0]
...@@ -1705,6 +1728,9 @@ simul_axi_hp_wr #( ...@@ -1705,6 +1728,9 @@ simul_axi_hp_wr #(
); );
`endif `endif
`ifdef LWIR
`elsif BOSON
`else // PAR12 od HISPI
simul_clk_mult_div #( simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT), .MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV), .DIVISOR (PIX_CLK_DIV),
...@@ -1744,53 +1770,8 @@ simul_axi_hp_wr #( ...@@ -1744,53 +1770,8 @@ simul_axi_hp_wr #(
.en (1'b1), // input .en (1'b1), // input
.clk_out (PX4_MCLK) // output .clk_out (PX4_MCLK) // output
); );
`endif
/*
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
.WINDOW_WIDTH (160),
.WINDOW_HEIGHT (120),
.TELEMETRY (2), // 1),
.FRAME_PERIOD (946969),
.FRAME_DELAY (100),
.MS_PERIOD (25) // 1us instead of 1 ms
) simul_lwir160x120_vospi_i (
.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
.mrst ( PX1_MRST), // input
.pwdn (1'b1), // input
.spi_clk ( 1'b0), // input
.spi_cs ( 1'b0), // inout
.spi_miso ( lwir1_miso), // output
.spi_mosi ( 1'bz), // input
.gpio0 (), // inout
.gpio1 (), // inout
.gpio2 (), // inout
.gpio3 (), // inout
.i2c_scl (), // input
.i2c_sda (), // inout
.mipi_dp (), // output
.mipi_dn (), // output
.mipi_clkp (), // output
.mipi_clkn (), // output
.telemetry_rev ( 16'h7654), // input[15:0]
.telemetry_status ( 32'h137f1248), // input[31:0]
.telemetry_srev (64'h0123456789abcdef), // input[63:0]
.telemetry_temp_counts ( 16'd59000), // input[15:0]
.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
.telemetry_agc_roi_top ( 16'd0), // input[15:0]
.telemetry_agc_roi_left ( 16'd0), // input[15:0]
.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
.telemetry_agc_roi_right ( 16'd159), // input[15:0]
.telemetry_agc_high (16'd19200), // input[15:0]
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
*/
`ifdef LWIR `ifdef LWIR
simul_lwir160x120_vospi #( simul_lwir160x120_vospi #(
.DATA_FILE (LWIR_DATA_FILE1), .DATA_FILE (LWIR_DATA_FILE1),
...@@ -1965,6 +1946,187 @@ simul_axi_hp_wr #( ...@@ -1965,6 +1946,187 @@ simul_axi_hp_wr #(
); );
`elsif BOSON
wire boson_single = 1;
wire [BOSON_OUT_BITS-1:0] boson_pxd1;
wire [BOSON_OUT_BITS-1:0] boson_pxd2;
wire [BOSON_OUT_BITS-1:0] boson_pxd3;
wire [BOSON_OUT_BITS-1:0] boson_pxd4;
wire boson_pclk1;
wire boson_pclk2;
wire boson_pclk3;
wire boson_pclk4;
wire boson_dvalid1;
wire boson_dvalid2;
wire boson_dvalid3;
wire boson_dvalid4;
wire boson_vsync1;
wire boson_vsync2;
wire boson_vsync3;
wire boson_vsync4;
wire boson_hsync1;
wire boson_hsync2;
wire boson_hsync3;
wire boson_hsync4;
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_1_i (
.mrst (sns1_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns1_ctl), // input
.pxd (boson_pxd1), // output[15:0]
.pclk (boson_pclk1), // output
.dvalid (boson_dvalid1), // output
.vsync (boson_vsync1), // output
.hsync (boson_hsync1), // output
.uart_in (sns1_dp[4]), // input sns_txd
.uart_out (sns1_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_1_i (
.red (boson_pxd1[ 7:0]), // input[7:0]
.green (boson_pxd1[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync1), // input
.vs (boson_vsync1), // input
.de (boson_dvalid1), // input
.pclk (boson_pclk1), // input
.dp (sns1_dp[2:0]), // output[2:0]
.dn (sns1_dn[2:0]), // output[2:0]
.clkp (sns1_clkp), // output
.clkn (sns1_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_2_i (
.mrst (sns2_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns2_ctl), // input
.pxd (boson_pxd2), // output[15:0]
.pclk (boson_pclk2), // output
.dvalid (boson_dvalid2), // output
.vsync (boson_vsync2), // output
.hsync (boson_hsync2), // output
.uart_in (sns2_dp[4]), // input sns_txd
.uart_out (sns2_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_2_i (
.red (boson_pxd2[ 7:0]), // input[7:0]
.green (boson_pxd2[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync2), // input
.vs (boson_vsync2), // input
.de (boson_dvalid2), // input
.pclk (boson_pclk2), // input
.dp (sns2_dp[2:0]), // output[2:0]
.dn (sns2_dn[2:0]), // output[2:0]
.clkp (sns2_clkp), // output
.clkn (sns2_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_3_i (
.mrst (sns3_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns3_ctl), // input
.pxd (boson_pxd3), // output[15:0]
.pclk (boson_pclk3), // output
.dvalid (boson_dvalid3), // output
.vsync (boson_vsync3), // output
.hsync (boson_hsync3), // output
.uart_in (sns3_dp[4]), // input sns_txd
.uart_out (sns3_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_3_i (
.red (boson_pxd3[ 7:0]), // input[7:0]
.green (boson_pxd3[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync3), // input
.vs (boson_vsync3), // input
.de (boson_dvalid3), // input
.pclk (boson_pclk3), // input
.dp (sns3_dp[2:0]), // output[2:0]
.dn (sns3_dn[2:0]), // output[2:0]
.clkp (sns3_clkp), // output
.clkn (sns3_clkn) // output
);
simul_boson640 #(
.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
.WIDTH (BOSON_WIDTH), // 160), 640),
.HEIGHT (BOSON_HEIGHT), // 120), 513),
.OUT_BITS (BOSON_OUT_BITS), // 16),
.FPS (BOSON_FPS), // 60.0),
.HSW (BOSON_HSW), // 8),
.FP_BP (BOSON_FP_BP), // 22), // 102),
.FP (BOSON_FP), // 12), 52),
.VSW (BOSON_VSW) // 7) 87)
) simul_boson640_4_i (
.mrst (sns4_dp[7]), // input
.single (boson_single), // input
.ext_sync (sns4_ctl), // input
.pxd (boson_pxd4), // output[15:0]
.pclk (boson_pclk4), // output
.dvalid (boson_dvalid4), // output
.vsync (boson_vsync4), // output
.hsync (boson_hsync4), // output
.uart_in (sns4_dp[4]), // input sns_txd
.uart_out (sns4_dn[4]) // output sns_rxd
);
simul_103993_serializer #(
.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
) simul_103993_serializer_4_i (
.red (boson_pxd4[ 7:0]), // input[7:0]
.green (boson_pxd4[15:8]), // input[7:0]
.blue (8'h17), // input[7:0]
.hs (boson_hsync4), // input
.vs (boson_vsync4), // input
.de (boson_dvalid4), // input
.pclk (boson_pclk4), // input
.dp (sns4_dp[2:0]), // output[2:0]
.dn (sns4_dn[2:0]), // output[2:0]
.clkp (sns4_clkp), // output
.clkn (sns4_clkn) // output
);
`else `else
......
fpga_version.vh
View file @ 043d4849
...@@ -35,7 +35,9 @@ ...@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation
//BOSON
// parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode // parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output // parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq // parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq
......
includes/x393_parameters.vh
View file @ 043d4849
...@@ -429,6 +429,8 @@ ...@@ -429,6 +429,8 @@
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period) parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8, parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter SENSI2C_STATUS = 'h1, parameter SENSI2C_STATUS = 'h1,
...@@ -500,8 +502,16 @@ ...@@ -500,8 +502,16 @@
//`endif //`endif
parameter SENS_CTRL_LD_DLY = 10, // 10 parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI //`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12 parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15 parameter SENS_CTRL_GP1= 15, // 17:15
//`elsif BOSON
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
//`else //`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6, parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
...@@ -589,15 +599,15 @@ ...@@ -589,15 +599,15 @@
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`endif `endif
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`ifdef SIMULATION `ifdef SIMULATION
parameter VOSPI_MRST_MS = 1, // master reset duration in ms parameter VOSPI_MRST_MS = 1, // master reset duration in ms
parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer parameter VOSPI_MRST_AFTER_MS = 5, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync parameter VOSPI_SPI_TIMEOUT_MS = 3, // Wait to tymeout SPI when needed to re-sync
`else `else
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap) parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`endif `endif
//`else //`else
//sensor_fifo parameters (for parallel12) //sensor_fifo parameters (for parallel12)
...@@ -658,6 +668,7 @@ ...@@ -658,6 +668,7 @@
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW" parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL // parameters for the sensor-synchronous clock PLL
// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
`define TWEAKING_IOSTANDARD `define TWEAKING_IOSTANDARD
`ifdef HISPI `ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
...@@ -668,12 +679,18 @@ ...@@ -668,12 +679,18 @@
`ifdef TWEAKING_IOSTANDARD `ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
`else `else
parameter PXD_IOSTANDARD = "LVCMOS18", parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18", parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`endif `endif
`elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
...@@ -686,17 +703,15 @@ ...@@ -686,17 +703,15 @@
`endif `endif
`ifdef TWEAKING_IOSTANDARD `ifdef TWEAKING_IOSTANDARD
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25" `else
parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25" parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
`else parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE", `endif
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 // parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
......
includes/x393_simulation_parameters.vh
View file @ 043d4849
...@@ -53,8 +53,8 @@ ...@@ -53,8 +53,8 @@
parameter FCLK0_PERIOD = 41.667, // 24MHz parameter FCLK0_PERIOD = 41.667, // 24MHz
`endif `endif
parameter FCLK1_PERIOD = 0.0, parameter FCLK1_PERIOD = 0.0,
// for python (export to C header) all parameters should be defined
`ifdef LWIR //`ifdef LWIR
parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat", parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat", parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat", parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
...@@ -83,7 +83,17 @@ ...@@ -83,7 +83,17 @@
parameter LWIR_GPIO_IN = 4'b0000, parameter LWIR_GPIO_IN = 4'b0000,
`endif parameter BOSON_DATA_FILE = "/input_data/pattern_160_120_16.dat",
parameter BOSON_WIDTH = 160, // 640
parameter BOSON_HEIGHT = 120, // 513
parameter BOSON_OUT_BITS = 16, // 16
parameter BOSON_FPS = 60.0, // 60.0
parameter BOSON_HSW = 8, // 8
parameter BOSON_FP_BP = 22, // 102 (FP+BP)
parameter BOSON_FP = 12, // 52
parameter BOSON_VSW = 7, // 87, // in scan lines
//`endif
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks // parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
...@@ -192,9 +202,16 @@ ...@@ -192,9 +202,16 @@
parameter HISTOGRAM_START_PAGE = 20'h12345, parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
`ifdef LWIR
parameter WOI_WIDTH= 160,
parameter WOI_HEIGHT= 122,
`elsif BOSON
parameter WOI_WIDTH= 160, // 640,
parameter WOI_HEIGHT= 120, // 513,
`else
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64, parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32, parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
`endif
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2 parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000 parameter SENSOR_PRIORITY = 1000
input_data/pattern_160_120_14.dat
View file @ 043d4849
// //
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff // autogenerated from ../input_data/pattern_160_120_14.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
// //
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4 160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41 31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
......
input_data/pattern_160_120_14.dat0 0 → 100644
View file @ 043d4849
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
//
160e 3189 3348 3256 3201 31ef 3258 324e 32e9 333d 3365 3427 3690 2714 13d1 0e40 11f6 3293 334b 31f1 31d0 31e8 3210 31bb 3173 31ec 3255 3264 3301 33d1 3568 16c0 0dd6 103b 1092 10fa 10e2 115e 1206 11f6 1123 10d7 0ff5 10e3 2c2c 3435 3288 33c3 3738 252f 0dcf 0dc3 0e3e 0eab 0f5b 104b 1008 0ebb 0cd8 0b4f 0f2c 2a2e 3436 3257 3241 31f4 321c 3376 340f 207a 093e 0c08 0ec9 0f59 0fac 0fb8 102f 0e98 27f6 3774 34b2 33be 3369 3325 3349 33f8 34eb 3591 35d4 35f8 362f 366f 3610 35c1 3555 34b1 3452 3429 33d1 33a5 32a8 326d 321a 322b 356e 1fed 09cc 0d1a 0d85 0d33 0dca 0e00 0e5e 0db4 0ed4 0ec7 0e85 0e54 0dfe 0e97 0e35 0e42 0e84 0f0b 1005 100b 10d7 1104 112c 125b 283b 37fd 34f5 3507 34f9 354c 34ee 3454 343d 3432 3483 34d9 34c3 3505 34fb 3458 3437 33f4 3443 3403 33ad 3308 1ffc 0d7a 073e 09b4 0c84 0c16 0b3e 0be4
31bf 338b 329a 32f6 3291 329b 32c0 3300 3379 33a2 341d 363c 21a5 0fbb 0f56 0fbf 0e6c 2a60 35fe 3208 31a3 31b9 31ff 316b 318f 323c 3218 31c5 3230 347b 2f16 0df8 0ef1 1035 1042 0ffc 1028 1038 10a3 115b 10c8 1022 0f16 0b78 1eeb 37bd 364d 3456 21fd 0d92 0d53 0eac 0f8c 0fc1 0fb5 0f6c 0ea7 0cd1 0b4f 0d9b 2c75 3440 31cc 324a 3242 3280 3288 3287 329b 35d3 223f 09b4 0ea6 1048 10fa 1141 0fee 1185 3265 36a2 34a1 3464 33d9 3394 33a2 345e 34ee 358f 35c7 364a 375e 38d5 3907 385b 365e 352f 3503 3483 3407 33bd 3344 32bd 32eb 3249 3533 24d2 0a3c 0c79 0dc0 0e67 0ee4 0f46 0f25 0f4c 0f85 0e7d 0e98 0d7a 0d89 0e5a 0edb 0f35 0fc2 0fa5 1081 1059 10b6 1124 10d6 1141 15b1 33d9 3766 35e0 3564 356c 34c7 34ac 3484 34a5 34a2 34de 350b 34cc 3505 345c 343c 3417 3411 3416 339f 33c0 353e 317b 2298 0cc7 0946 0be2 0c17 0c41
332f 3299 32af 330c 32f1 3301 3348 3347 33b4 3370 3607 27fe 0d4d 0f79 107c 0fb3 0e4e 18cd 35f5 33be 325b 31cb 31a3 317a 321d 3292 3295 3210 3208 3666 1f5a 0c62 0ebe 0efd 0e99 0e97 0ebe 0fba 0f21 0fd1 106e 0ea9 0f2e 16fa 2532 2dca 24ee 155b 0c89 0e14 0f1a 0fba 0f88 0fc5 0f1b 0e6b 0d9a 0c9a 0ad8 2603 3551 3175 315c 31c0 31fa 3220 324c 322e 32a8 3345 3602 198e 0b92 1037 1040 106a 0d3f 1fa2 3790 347f 33df 344d 3421 33d8 33ed 34a2 352e 3580 37f0 39d3 3321 2b5f 296f 2d11 348f 3841 35f4 34c6 341d 33fc 338b 3300 32b5 3205 3495 2446 0a9f 0ccb 0d21 0ddb 0e47 0e4f 0ee2 0e84 0e6a 0e07 0ee1 0f0c 0e5a 0e49 0e0e 0e8e 0f0e 0f23 0ef7 1011 10c7 1128 1134 119b 1172 281c 397d 35ed 355d 35a0 356c 34f1 34c7 34fa 3510 354a 3566 3521 356b 3485 33ff 33f4 339c 3359 33b1 3335 32ed 3346 357f 2e1e 102a 0948 0bb4 0c01
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334f 331e 334e 338e 33cc 3400 3465 345d 34de 370a 3360 1323 11fc 141c 146b 1114 1ee3 38af 36cc 35b5 3577 35a3 3618 35fe 369e 3753 37fb 39fc 36d8 277a 1c61 18ce 191d 1b3d 222a 311b 3b0d 38d5 37cb 376c 36bd 3698 371d 36b0 3a0f 278f 132d 151a 163a 15b9 1563 14da 161d 1537 1559 1614 1733 166d 153f 1523 1595 167c 1700 17bc 1873 1904 1898 18a5 1910 18e2 197c 18a9 3388 3a7c 38e6 3965 3927 38b7 38f8 3909 38df 38fd 390c 392b 393f 394d 38c9 3855 3822 384e 38a4 390e 391b 3955 394b 3937 3c82 30c7 158e 1657 1565 1570 16bb 1675 14f9 152b 1519 14ff 143d 14b1 14d6 1499 1447 142c 156c 1501 1481 1588 19ae 2913 353b 3b42 3a20 3843 380f 37ff 3819 37f0 37b3 376f 37b6 37e4 3743 3658 367a 371f 3793 3790 3772 37c3 3851 3980 330e 128f 1138 136b 1349 1599 1368 111a 1279 1406 15ff 1726 1777 1691 14bb 14a8 1458 130f
32e5 3301 33f4 3405 3408 3491 34aa 3462 34de 3526 38f9 2185 10d1 1363 1014 1c27 3650 3720 3634 359b 363b 3630 367f 3636 36d7 3770 3a67 31b1 1958 1429 14f5 1517 1702 1640 1508 171c 274a 3a47 38c2 374c 36f5 36d4 36b5 3734 3ab9 1efc 12e9 1490 161d 15af 148f 1521 1511 146c 14e4 155a 15a3 13a2 1133 1193 12ba 1433 1625 16d5 16fb 170e 17ec 18d2 1824 1927 198c 17bf 2efc 3bec 39a2 3985 38f6 38fc 38f9 38f3 38e3 38a6 3904 3997 39ac 3985 3965 38ea 387a 38ee 38ff 38bc 38ff 38fd 382e 384d 3985 3d5c 21d2 1526 15dc 15d1 16e6 1612 14c8 146d 1473 153a 14f5 1568 1555 1544 1582 153d 15b9 15af 14df 154a 14f8 163e 18cc 22e8 37b5 3b42 38cc 38a1 382c 37e3 3759 377b 37e8 3811 3791 3756 37c5 373e 372d 371a 36e4 3761 379a 37f8 3a2e 2a0e 1067 10bd 135c 14ca 14f6 1131 1166 1275 152d 170a 18be 182d 1685 1563 1519 1423
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347b 345a 3403 3492 3565 35e2 365f 36b0 38b0 3a8c 3475 2e59 307f 36e5 3940 370d 36eb 3668 3639 35f3 35b8 359e 35c4 3635 370e 3981 1cfb 125c 1523 1500 15f2 1698 16b1 165e 1729 1775 181f 1925 333c 3b56 38f1 3815 399d 3c3e 21a3 153d 1723 1833 1813 1637 148e 14e2 1505 154f 128f 2006 3419 3a8f 3b83 3b8e 3c1a 3ac7 2fb6 19d3 14d4 1844 1870 18e0 184c 179d 16b0 17f2 359f 3b90 3a26 39e4 3955 3944 38fb 3974 396a 399f 3a3a 3a6d 39e4 3aad 3a80 3ae6 3a4e 39f6 3952 38b3 386a 38ba 3841 3850 38e0 3a74 3513 15a3 15e3 15a2 167b 15f6 168e 16ab 15ac 13ff 1457 1539 1624 1495 1486 15c4 1646 14d1 12e2 135b 1451 1527 153b 1561 15d9 213e 3b7e 3934 388b 3855 3842 37b6 378f 3743 36ea 37a1 38c9 3881 37ac 37b9 3714 369d 36e6 375f 382d 3871 3a95 39d5 30a9 1f93 1292 1302 122a 11a8 12ea 159c 1616 163b 1653 15a4 155f 148c
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34d1 3532 3565 3617 3691 368d 39f2 2cfc 15df 1408 14cc 1756 349b 38da 360d 35e0 35e2 35fd 358c 35e5 3623 363c 364a 36a9 39c1 22c3 111d 13ba 1559 14d2 14db 14f5 14b6 1669 1706 1723 15fd 127b 189a 3a66 3bb3 32cf 20b3 15ec 1686 179a 17fb 16d2 1543 14c2 1401 14f2 1450 2404 3c77 3940 3841 37d4 3824 381a 3853 38c0 38c7 3b95 37fb 194f 174d 1899 18e4 1933 160a 2e7b 3bc3 391a 3918 39c1 3988 3980 39ee 3a35 3b13 3c94 3e50 3947 3085 2b1c 2b3b 3047 3948 3dbf 3baa 3a72 3a38 39ba 3907 38ce 3926 3b3c 3565 1681 16b0 16f4 16ea 1653 167c 16a9 1571 147e 143d 14fa 1647 143b 13af 1489 1605 1679 159a 14b7 1530 1653 16ef 179f 1700 16b9 2537 3cb6 39b8 3999 38e3 3877 3819 381d 379d 3845 38b6 38f7 390c 3850 389b 3861 3848 386b 3817 3812 383b 36b0 36ff 37d4 3b92 277a 1270 12e1 131e 1518 1636 1557 15a8 15ee 1692 15b2
34fa 35b4 35df 3656 368e 3929 31ea 14de 1435 15fa 1629 1488 260b 3b62 3704 3660 3573 3501 34ba 356d 360f 364d 369b 390b 3703 15dc 1307 144c 1574 1587 1514 149a 144b 14e6 15e3 13cf 1893 259a 313d 2893 1d6e 1758 1718 17f4 17da 18af 187c 17c3 1571 141e 14ac 1611 1a5f 386e 3a5f 38ad 3835 3864 3851 37ef 381c 38e6 39ac 3995 3ce0 2955 14b5 179d 1777 1584 2449 3b50 399d 3869 3871 38e0 3926 397f 39d3 3a6d 3c5e 3c62 2a32 1d70 1a49 19d9 1a66 1a7a 1e3e 2bf6 3c17 3be2 3a48 3902 3823 37fe 38e3 3c9c 2ef9 1555 16af 171f 1781 1713 1684 16f2 15db 1443 1482 15d6 1583 13a1 12f3 1364 14cb 1600 160f 14e1 13f8 15a3 176a 188b 1865 1822 2093 3c14 3ad1 39b0 38d5 3868 3819 37d2 37bf 3839 3879 3922 3922 38ca 38f9 388b 389e 3855 3827 37d6 37e2 3754 372a 3787 38d7 3976 18e4 12ee 1343 149c 16bd 1695 1615 15c0 15cc 1587
361d 3656 36f8 3743 3702 3979 1d68 12e4 156e 167a 1641 1488 17a6 2efd 3ad9 365a 3593 358f 35b6 35e2 36f2 37d8 3983 3bba 22e6 139e 151c 150a 155f 1568 149e 150e 15bb 1548 122a 226e 386b 3cb4 3dcd 2669 147a 1919 1944 1906 1820 1879 1731 168b 14ae 1515 170a 167a 2645 3c84 3922 38ef 3833 3863 3879 38ad 38a4 3951 3979 3989 3b19 36f4 15b7 159b 16a2 2563 3aa8 3a20 3941 387f 3837 38b7 38ef 3915 398a 3b2e 3b20 22b0 18e9 1a76 19b7 1998 19c6 199c 1a35 193b 2699 3c36 39a2 3834 375c 3747 384e 3c1a 2098 1514 1586 159e 16a8 164b 16e8 16dc 1617 151d 1457 1234 1428 182d 19c0 1724 1269 1341 164d 15b7 1536 14c9 1698 1785 18cf 181c 201b 3bdc 3af9 3a0d 3944 38f6 3831 37f5 37fe 3876 3889 3901 392a 38e1 38e6 38af 381e 3770 37cd 3812 37e7 377f 3741 3716 37b1 3b7e 263e 1199 13f1 155a 1742 1775 164e 155f 162e 1601
3642 374e 37e8 3768 38c0 30d2 1234 13d4 141c 15e3 1625 15de 1641 180c 2d85 3ad9 38f5 379d 3702 37b1 3960 3b96 3b0e 252c 1402 1530 154b 14ea 15ac 1619 1539 155c 1509 12e9 23b5 3a9b 398a 389b 3a73 3386 151c 18ca 19b9 194a 180b 180b 186f 176c 159a 16cb 1869 180a 3358 3b85 391b 38d7 38a3 3897 38a7 38dc 395f 3a25 3a95 3c39 3de7 3b2b 2043 2419 33c5 3c35 3a0d 38f9 389e 3887 37e8 37fe 3881 3839 38d8 3bf7 2525 16ed 17dc 185f 1a57 19cd 1a0f 1996 1897 194b 1904 2e8b 3c04 3875 37f6 3873 3bc8 3138 1461 14e9 1580 155c 165e 16d6 1786 18bf 1600 137e 17d5 2903 3578 38ef 393e 37c8 2fb8 1df1 1227 158c 1534 1491 1640 1739 18b7 1845 243a 3d03 3a63 39f0 3956 38c4 3829 3808 37b6 3893 38d7 3920 396c 39dc 39a0 3972 3883 37c7 3788 3795 376f 3745 36f2 3643 3763 3acf 2f0a 1219 13a0 1420 163d 16ad 1672 1691 169f 15eb
36d8 37c3 374f 3756 39be 271f 0f7e 13dc 14c4 1586 1555 15a2 15b0 1524 1637 2365 3272 392f 39a7 3a28 37ff 2d9f 1cfc 1493 157c 158d 14f6 1450 15f7 162d 15df 1521 13f4 1d90 3a7e 386e 379f 3809 3873 3bd6 23d5 162e 1a9f 1a45 1981 187d 1882 17c0 1748 169c 1472 23ce 3b40 38d7 3840 3884 38b7 38ec 38a6 3902 398c 3a9f 3d8d 389b 2ab2 21d5 37ab 3de7 3bdc 39b0 38d9 38da 387c 3871 385b 37ec 3828 38b1 3b0b 33c9 175d 17d7 17f7 18c6 1a6e 19e7 18b7 18d4 1820 18e8 181c 1e2f 3a8b 3ad3 3a39 3d21 3689 1929 1443 1556 1747 169d 164b 15ff 16e9 173f 13fd 1f31 3730 3bd1 39b5 3844 378b 3815 3a91 3aa1 26ec 110e 14dd 15b7 1612 1766 1852 1814 2e2a 3cc9 3a65 3a30 39af 38bd 389e 3826 37e2 38db 3971 3a7b 3bed 3ca9 3cd9 3be9 3a01 385c 37ff 37cd 379d 3769 36cb 35f3 376f 3a08 313e 12f2 13a2 143e 14f0 16d1 1651 1606 15d5 15d8
371d 3746 36cd 3713 39f5 234e 0fa4 13a3 1668 1756 1569 168f 151c 14b6 1535 1522 17be 1ad2 1c45 1d85 1a0f 1683 15c0 15b2 15c2 1650 1513 14de 1528 1403 1392 1420 1435 2fe9 3b0c 3846 37f0 380a 38e0 3a9e 394b 1de8 14fe 18a6 18b0 1874 173b 1619 1482 1442 1eea 38be 3995 37c6 3796 3865 3919 394c 394e 39ff 3ada 3d1a 2d9f 1b80 17ea 17d3 3465 3c39 38b4 38f8 3914 3903 38e3 38e3 3863 37b6 3831 3969 3d3f 2653 15ec 17c7 18bf 1952 1974 1958 190d 18ca 1948 187b 183e 17fd 32ec 3fa0 3d47 32dd 1c0d 16c4 1779 18f8 18a4 1848 177e 170a 15d9 14d6 1dba 3a80 3aae 3872 3864 37e3 37ce 375d 3818 38bd 3bce 24ad 11ec 15d6 1795 1856 1840 1e0a 3b22 3c36 3abb 3a25 3981 38bd 38bd 388f 3857 3904 3bb3 3b70 3401 2ebd 2e9e 3385 3ae5 3c68 398e 3888 3811 3777 36ae 3666 3708 3a95 2fd1 1316 1387 1534 15e1 16fe 166b 1558 155d 168d
3678 36a2 36a3 36df 398d 25c2 0f92 13a8 15e9 1558 1504 1541 14e5 15c7 14f2 13b2 1333 1318 13d8 1524 1581 1614 15c1 167b 169e 1701 16c5 15fd 1567 1429 146f 14ea 1987 38cb 394b 3857 3743 3807 3911 3a0f 3bd1 3978 25b1 16bf 1446 1481 12de 1203 156d 250d 3934 3a9e 38ed 384e 37e5 382c 38c7 3904 3a10 3ac8 3df1 2c0a 17d6 1884 17aa 1745 2706 3c60 3859 3871 37f0 3843 389f 3888 387b 3871 386e 3ab4 39fb 1a78 16fe 17ee 18bd 1947 1880 1825 1893 178c 17db 15a9 179b 2128 2ea2 2d66 22e2 1845 165a 1703 17dc 1912 1862 17fd 17d4 1799 177d 175e 336d 3bc1 38bf 386e 381d 3836 3890 3811 37dc 3812 3965 38b0 16df 13eb 1659 16d3 182d 32f2 3cbb 3a95 3a68 3a04 396e 3861 38c2 38c1 3987 3bbc 309a 1da0 16e7 173c 1703 17bf 1e62 304e 3ca8 39ae 3892 376d 36fb 36c3 36a5 3b6c 275b 122b 13bb 14f4 15f2 1588 15cc 158b 1569 1589
362d 3656 3659 3696 3857 2e4a 0f12 1346 15b1 14d0 1553 1493 1471 13f4 138d 123f 12da 1260 128c 13c6 1453 13b6 1405 15c7 14fa 16e8 165f 154b 15ea 15fb 15f8 14f6 1f81 3b57 3882 380d 3750 3894 391b 39b9 3a58 3aab 3c30 3690 2b97 2684 26e0 2b23 359b 3b7d 3a29 3994 38be 3843 37fa 382d 38de 3957 3a67 3c84 3555 1951 1912 18e9 17cd 174a 194b 34cf 3c19 38a3 383f 3841 3845 383c 38cb 3893 39dd 3d7c 26dd 1604 16a6 1714 1862 18f6 18a2 18d1 1761 1617 155c 25cb 373e 3da8 30e0 13d6 166f 1848 174a 1693 1676 167a 162d 15a6 1538 1570 1614 21e6 3ce3 39f1 38e4 386b 388b 3881 3852 3831 3837 3888 3962 3d40 246c 11dc 1340 176a 2f5b 3c84 3994 3913 3930 390e 3926 390a 3913 39e8 3c56 2902 14b3 150c 1695 1710 16a3 1735 1718 1812 2c23 3c9a 38dc 37eb 374d 36d5 37d8 39dd 1995 11f1 12d4 1401 155f 161f 1570 152c 146a 13e1
3618 365f 3641 364e 36ce 371a 1642 1229 1591 1578 1591 14a8 13ae 13d5 14a1 1490 1445 1425 14e4 1554 1663 16d2 15db 153f 154d 1615 15b9 1615 15b2 169e 15d1 1580 22e1 3cac 38c1 385a 383c 38bf 38fc 39b0 39ee 3a06 3983 3a5c 3b65 3be8 3b91 3b61 3a24 3909 3920 3921 391b 3814 387e 388c 3915 397d 3a9f 3d33 2358 18f6 1a5e 19ac 19c0 1900 1825 1f4f 38c1 3d25 3a6d 3988 3907 38db 395c 3b05 3d25 2b13 1716 1756 1614 169a 175f 1768 1752 1744 16e2 160d 2e5b 3d55 3bab 3aa2 389e 175e 156d 18eb 18f5 182e 1745 1788 16f6 1606 1509 15d2 1636 2fe5 3d1f 39dd 392c 3936 3902 38ee 38f8 3934 38a3 38c0 3a90 3ed8 2dbc 1569 234c 357e 3bdf 3974 3921 3902 38e8 38da 3916 3917 398a 3cb0 2ee1 13dd 151a 165e 1698 1679 168b 186e 17dc 1720 187a 32cb 3adc 3774 36e3 3683 3ab5 2bf7 1187 1334 13d5 151e 16a0 15a3 15b7 1492 1486 12a6
35b9 35d2 35ec 3602 366f 3985 2bd6 10a0 14bd 15b3 1505 1459 14e3 1579 1630 1597 15ce 158d 156b 16da 1776 16f0 160b 15a2 161f 1784 17a2 1685 1656 16a2 1673 16c2 217b 3c27 38d8 388e 388d 38ec 38aa 38b3 3864 3852 3869 38cf 38dc 38d1 38cd 384c 3894 38c7 38fa 3964 38c8 389f 390a 38e3 3934 38ff 3a5d 38d3 19ee 199d 1a51 1ac0 19f1 19a7 1a23 19b2 1e90 30cc 3b97 3d50 3d2d 3d1a 3cd2 3761 2531 16d9 17fa 182b 1805 18a4 17cb 17ea 177a 171e 15b6 29a1 3da6 39e2 399f 393a 3c3e 263e 13fc 17e5 18b1 1947 18a6 18b9 1885 17fa 17f0 15bf 1fa9 3c42 3b4c 3a05 39b8 394c 3977 39f5 3a08 3a22 3a09 3c2e 362b 2946 2a1c 3a2f 3bda 3a76 38b9 3942 3951 3928 3928 3974 395b 3922 3a2e 390e 1983 1503 163b 16df 177c 179c 1779 1801 1796 173b 1658 2280 3b79 3751 3809 3b5d 32f2 1598 1387 14cc 14dc 16ac 171b 1709 1624 15d6 12dd 21c7
3558 360e 3633 3645 3711 37af 3a30 260a 11eb 142c 1493 1385 13f0 14b2 1620 1585 1570 14d5 159d 16cc 1690 15ed 15f2 15c4 16c8 1780 173e 16a9 1577 15f8 1639 1730 1b90 38b9 39d7 38ab 384e 384d 38b6 38e5 3860 382d 383c 37fd 37ed 380d 37f3 37fc 383b 3867 3990 398a 3906 38ae 388a 38d2 3985 39ce 3b87 3446 172a 1a2b 1a25 19b0 1905 196e 1899 19d0 1917 1a34 200b 272d 2ae6 28b0 22f6 1b32 17a0 173b 17b9 17f1 1869 185f 18cf 18dd 18c1 1816 1de0 3bb4 3b98 39b4 3959 39b1 3a98 398c 1cfd 15ba 1818 182c 17a5 1858 1898 183c 15b6 1941 35be 3cab 3b00 3a82 39b7 3964 39e6 3a47 3a99 3b07 3c21 2900 17d8 151b 22c0 3dba 39fc 38da 385b 3825 385c 38a8 3911 38e8 391d 3921 3c02 2c43 12ac 15cf 16a0 16ad 1738 161f 16c9 16ff 1653 166c 15cc 1758 370c 3c45 3ba2 2ff1 1719 12ca 15ed 14fb 148b 161c 17d0 16d2 170c 1536 23f4 3bef
3587 361f 3608 3642 36ad 376a 3813 39f2 2995 151c 108e 1140 138e 13c7 14ed 1572 15c8 1453 156c 1682 16ad 157c 15b7 1689 16c9 1718 16ec 16a9 155f 1613 163b 1720 17a0 2e2b 3c41 389c 3865 3890 38da 38c1 385f 38b1 383c 37d0 381e 380b 37e9 37ef 37e0 3895 397a 3943 3915 38bd 38d9 3983 399a 3a69 3c14 3446 16d3 19ae 1a83 197f 197b 194e 189c 1989 18de 192d 1969 184c 17b8 183e 1874 18b3 172c 16bf 178c 16d6 166e 1729 1779 17e0 177a 1757 2bc9 3d5f 3a0a 3a78 39df 3a43 3a2b 3bfc 389a 210b 169c 1637 16bf 171c 1562 14f7 1d44 3422 3c56 3a2c 3a54 3a5a 3a5d 39c5 39ec 3a4c 3b57 3cb8 25e2 15cf 167f 17f8 1ccc 396c 3b49 3923 383e 3831 37c5 37fe 385d 3866 38fa 3a44 3bf5 1c64 1346 1582 16bc 1701 1881 164f 1546 1476 13fc 127d 15d0 1f51 3014 2b2f 1e1a 146f 1429 154c 15ef 1552 1445 1557 1667 1729 168c 1d0c 3b0f 3ab5
3532 3582 3574 361f 36bc 374d 376f 37c0 3a13 36d2 2ab9 1bb0 10ab 12d7 14aa 14e3 150a 14fd 1605 15e4 158b 15ab 1609 16bf 17d1 175d 170a 1693 15f8 16ab 15e0 169d 1863 1d1d 38aa 3af3 3895 38e3 388b 382b 37e2 37e3 3796 3757 377f 381f 3836 37f7 37eb 383a 385b 3829 37c5 3826 38e1 3990 39ab 397c 3a51 378c 1810 1838 196f 1a44 19b3 199c 1a25 19ff 18d4 1893 183c 1780 16ab 15b7 164e 17a6 1895 1748 171d 173d 1681 159e 16a3 176c 17fd 1871 343a 3b09 3917 3952 395d 3999 39f0 3a2b 3b59 3ba8 30af 2497 1eb4 1e8f 22ab 2df4 3a1d 3ad8 38c2 3901 38e3 38eb 396a 3939 39a2 3a94 3d9b 2af0 159c 187c 1885 1908 1973 2b59 3e6a 3a88 3929 38cd 3886 38a8 3895 38fa 39fa 3d98 2b7c 1232 142b 1647 160f 16bb 18d5 17c4 163a 157b 15b6 26b0 378e 3e54 29b4 10ff 1269 13da 1555 15be 1616 1641 158d 1589 161c 1656 170e 2e19 3da0 399e
3543 3546 3573 3605 363e 3690 3708 3744 36c0 379a 3916 399d 2bea 1430 1295 14c2 1500 1572 160f 1607 160d 154a 15c8 15ca 167a 1591 164b 1652 15d3 16e7 1665 1588 16d6 16d2 20d1 391c 3bda 3917 37e5 3821 37ce 36e1 3683 368d 3715 374e 375b 375b 376d 37d5 37ce 37e1 3795 37a9 3800 3898 38ca 3971 39e4 3bfc 1f84 15fc 18d9 1957 1880 1826 1881 17f6 1785 171a 1693 17b2 1759 15d2 156e 174e 181c 178f 17b4 176c 170c 15a7 1581 15b2 1775 1956 368a 3ab7 38f4 38c0 38bb 38a4 389c 38f6 3935 3a36 3aef 3bb8 3b4b 3b1d 3c0d 3be0 3a66 3904 37e9 379b 37d8 37fd 3825 382f 38ff 3ae5 38c4 1a36 16f4 1738 1966 18e3 18e9 1b78 31df 3e47 3b12 38ea 38fe 3944 38e2 3a5c 3d12 3022 15c6 139f 13cb 1589 162d 1686 175b 173e 1641 17bd 31e5 3d5a 3a56 3bca 328b 146b 154c 169a 15f6 16a5 1788 1783 1751 172f 1680 164b 1ae8 39d4 3af7 391e
343e 34d4 34f3 3531 35c4 3648 3671 35c6 3607 3604 35f5 36d1 3a97 3151 13e3 145b 146a 1465 150b 1793 17d8 1547 1575 14bc 153e 1587 162c 1614 15dc 1651 1699 1610 15c0 168a 15c4 1d3b 2fe0 39f8 3b62 3990 37a1 3685 35e9 3689 36bb 3677 3650 3649 36a1 36cf 377b 3743 3701 3772 37f9 37ea 3844 38cd 397b 3bd7 30b2 15c9 16a7 17a4 1686 1663 1715 1808 1824 17ae 16ff 1682 1651 155a 15ab 15b6 1707 16c7 16f0 16e3 16ef 1590 14fe 154f 1602 1797 356f 3aa2 3909 38a8 3853 380d 3809 37cb 37fb 3870 385b 387b 3932 3985 3935 38dc 3846 37b9 374e 3721 3775 3772 378a 376c 3867 3b80 2d16 16ba 1811 16f8 1846 181d 175c 17ed 1af3 2d16 3b11 3d7f 3c9a 3c70 3c6b 390a 2817 156a 13e3 1452 1471 1597 15fa 165e 1617 1656 1549 306f 3d2c 396b 3886 397b 3afe 1de3 132b 161e 180e 1816 1751 17dc 1737 1787 1774 15e1 2a59 3cfc 3953 38de
3453 3474 34d7 34d7 350c 3612 35df 35bc 3596 35a1 3574 35a2 3680 3a65 2909 11c7 140a 149d 1586 1601 153b 141e 14ea 1595 1622 16aa 15e9 156c 151a 156a 15d8 1634 1540 1589 15ac 163a 1690 1bfd 2852 381c 3a20 36c4 365c 36df 36f8 36bc 36aa 3691 366c 36fc 3777 372e 36e0 3716 37aa 37d5 37f7 3790 388f 396d 3bf0 2742 1523 1761 172f 171e 1771 1910 18e5 18d6 175f 1642 16b6 15d8 1583 1607 1692 167b 1735 16d7 1706 1654 17c5 16c6 163c 1695 306f 3a77 37c4 37f5 3793 3775 3764 37bc 37b6 37a8 37bd 37e5 3867 38d2 38cc 389d 382b 37cd 37aa 37b5 37a0 37b9 37fd 37f5 38c3 3bbf 2481 164a 16de 162c 1695 16cb 1718 16dc 177f 1868 1e1b 270b 2a5b 28d8 233b 1a13 1536 14f9 155e 159e 156c 15c1 1667 1641 1610 1471 223e 3cbd 394f 3841 3835 38b3 3a71 33e6 15cc 1145 14da 16af 1736 176c 16a0 15d8 14c2 23a1 3b21 39f1 38b0 3836
3498 34ac 349e 34ba 34e5 3595 3585 3566 3526 3529 34e7 3529 357a 3726 3885 17f3 1387 14ec 14fe 1575 1430 13ee 15a9 16f6 165f 152b 1475 1421 143a 1572 1504 14f1 15c2 1636 15ba 15d3 1549 1621 157b 1bdd 327a 3a55 377f 376e 3748 374b 37a2 3772 3707 37aa 378e 3799 37b3 37a5 3807 3811 386c 38f7 38ec 390e 39ae 3bab 295f 1615 140d 1584 16d4 168a 173f 176b 1723 1755 1778 1709 1627 165a 1653 1615 16bc 1768 16e2 17af 180b 17ea 1686 1611 24f7 3cc0 38ed 387a 37a2 3802 37f5 387b 3889 3874 381b 381e 389c 3859 38c6 3857 386c 37ea 382b 3806 382e 3820 3856 38ab 393b 3c37 21c4 16b0 1803 16bf 16f7 161a 16de 175b 16b9 15f9 167c 16af 1637 1581 1531 14f3 1467 13cc 151f 1539 14d7 158c 15f9 16e5 17a2 149b 31b0 3b50 3823 37c6 37b0 37d5 37f3 3b03 3270 18c9 1153 12f2 153b 1611 1549 174a 27e8 3b2a 39dc 38ba 37ff 3833
33dc 3448 348a 3484 3450 3538 34ec 350d 3546 352d 34e5 34d4 3587 3610 3a44 2396 1206 14c0 1502 1612 14e9 15fb 1695 161c 155f 13d8 1308 1345 141d 1462 1488 1501 1670 1647 155c 1506 1606 163d 1780 1690 1afc 36f3 3a3b 3898 380f 37d9 3839 388e 3854 3853 3864 383e 387f 3854 37f4 385b 38bf 3938 3956 3951 3996 39b6 3bd5 352f 278b 1993 12fc 1482 1586 162b 178b 189d 180f 1707 166d 1660 16b1 174c 170e 16af 167d 1623 16ac 1791 168f 16af 1860 3521 3c48 38ca 38c2 3920 38f1 38bc 391e 38c1 38eb 3903 395a 38ff 38f5 38ca 3904 38dc 381b 37cd 37ff 38ab 38c8 3912 3975 3c7e 26b9 15f7 17ca 175b 1630 169a 17c4 179e 17ce 16ca 15d0 16e4 165f 15fc 15dd 16a0 1615 1533 1561 153a 1503 15b6 160a 16ca 178c 19b7 38b2 39ab 3825 381e 37d9 380a 3875 3949 3bd0 39a5 2c38 219e 1f00 21c3 2a4b 36cf 3d9f 3ad8 39a0 38dd 388d 3862
33c9 3490 3535 34b4 3520 35b5 35a9 3540 35a7 356f 357e 35aa 364a 3663 39a0 2af7 129e 156c 169c 166c 1597 162e 1632 15dc 16ca 1682 15dd 1433 149f 15b3 15e6 173d 1742 176b 16ea 176e 189a 180c 1821 17d3 1753 2449 3c48 39e5 39b2 399c 3934 396b 3935 3916 38fa 38dc 3930 395f 3912 38eb 3938 3986 38e2 38cc 38d5 38bc 38fa 3aaf 3cbd 3a85 28f8 1548 1559 1602 16c0 17a8 1828 1778 16d7 178b 17ec 1883 182c 17c3 172d 1731 16ff 165e 1646 157b 1698 1e47 38bf 3ca5 3a4c 3a1f 3a50 39c7 39fb 395e 392b 3921 3984 3936 394e 3920 390a 3916 38b4 384d 386f 38b8 38d8 392b 39d0 3b94 3114 1596 174b 17a7 166b 15a5 1663 160b 1731 16d7 1600 17ad 1730 1601 1631 1622 1609 15b9 15e4 1592 15bb 15ee 15cf 167a 176a 1db0 3b07 396f 3857 387e 38b7 38e7 395e 395a 39a4 3a77 3c8a 3cc1 3cd6 3d68 3dbc 3c85 3b3a 3b03 3a6f 39bf 3944 393d
367f 3567 3596 37ad 3916 37ab 3699 3676 35e5 363a 36ac 369d 36fa 374a 3a5c 2d79 138a 1662 16d4 157c 1508 154a 150a 1499 1581 15a6 14fe 1489 15dd 1745 176d 186b 1808 17d6 176f 16e1 180f 17f5 1815 1786 18a0 1a7d 366b 3bc3 3a87 3a9d 3a09 39b9 3975 396c 39a3 39d3 39fe 3a51 39f2 39cf 3986 3981 395a 3907 386c 38b2 394f 399d 3a2e 3b3a 3e6a 2d5a 17b3 1799 1664 1603 16ff 176f 1831 1881 183a 1802 17d8 178a 173e 1758 178d 183f 18b9 1810 1756 17c5 1df9 3206 3c98 3e64 3cc7 3ae9 3a29 39fd 399b 39cc 399e 395f 399e 39b8 39ed 396a 397d 393a 38e6 38c2 38cf 390b 3a0f 3aaa 3b40 1dcc 1613 182b 1746 16c0 16f2 1728 16b1 1704 15f6 1736 16d3 160e 1652 16bc 158c 1524 1569 15c6 154a 1573 1585 16fc 16b7 1d75 3b64 3a4e 38d9 38a5 3881 38d2 38e6 38f2 396f 39b8 3a1a 3a69 3ad4 3ae2 3b20 3b16 3b5c 3b2f 3acd 3a0f 3a1e 3a3b
1895 1509 1596 1af6 2659 34cd 39e3 3733 370f 3670 362b 363f 36e4 36b1 3adc 299f 13c5 155e 1480 1484 1449 1482 1461 13f0 142e 1469 14d0 15b7 1663 175f 15cb 15db 15b2 1563 1640 16a6 16d0 1754 17d6 18b2 196f 1849 2e81 3c7f 3a84 3a5b 39fe 39af 3970 399b 39f1 3a56 3a97 3ab9 3a09 3a53 3a35 3989 3926 394a 3929 3962 397f 39ca 3a2e 3a13 3b02 3e15 25b7 17db 1883 17b1 1724 17ae 186b 1866 1840 17c8 180d 17e5 1730 1792 16d0 1768 1890 1918 188a 17f7 181d 1acc 211e 2c36 3aca 3dfd 3b72 3ae7 3a87 3afe 3aa2 3a4c 3a32 39b1 39e2 39e0 39a5 39fd 39d2 394b 397d 392e 39c8 3a69 3bff 3411 16f0 15dc 17c0 181e 182b 1847 1742 17a0 1663 16b3 173f 1659 1636 1712 15e2 157f 1515 14cb 1536 153f 1572 16af 16a6 1aa0 37f7 3b1e 38d5 3907 390d 38e0 38ed 38d8 38ba 38f1 38ec 39ce 39ca 3a3b 3aab 3ab9 3a77 3ab6 3ac3 3a05 39be 3a3b
0d54 0e1c 0f11 1141 1290 17a3 2b75 3a3b 37a5 369f 35ef 362c 36db 37af 3b33 201e 140e 14f2 1406 14fb 1515 147b 1461 13ef 13ce 146c 13eb 128a 121c 131d 12ae 12c9 14d2 15d1 1604 1758 17f0 175c 1814 18eb 193e 1847 2c3e 3cfc 3a22 3a0f 39c0 39c3 39ea 3a0c 3a0b 3a77 3ace 3aa4 3a70 3a96 3a1f 39c8 39fa 3a1d 3a03 3a9d 3a3b 3a19 3a44 39f3 3a23 3c9d 35f3 1857 189d 184d 16fe 1724 17b6 183d 1809 188d 18a5 1900 1845 1831 17fe 18ad 17ad 189a 190d 19bf 1916 19b2 19af 194f 2038 355a 3d4a 3ae2 3ac7 3af3 3b43 3b22 3a88 3a2c 39cd 39e6 39c9 39b2 399c 3a21 39ee 39d2 399c 39f7 3a7b 3cae 3313 1b61 13a4 15dc 1828 1841 17cb 1714 160a 162e 1659 1739 1726 1746 1658 1671 1568 1516 15a7 15e7 1643 17c8 17d6 174f 2d8b 3ce2 3859 3856 38e0 38bb 38e1 38cf 389d 3909 3934 397e 39ea 3a1c 3a09 3a96 3a61 3a61 3a74 3a0f 39f4 3a15
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0f27 0f48 0ff5 123b 13de 1646 16bb 17a6 32e5 38dd 368e 3775 392c 3be8 21f3 151b 170d 17ac 1825 18b1 1938 1983 18c8 169f 146f 23a6 3720 3c08 3b82 3b14 3bc8 3c43 3801 2496 13e5 16ea 182d 19b2 193e 1936 1a40 19b0 343d 3c49 3ac1 3a54 3a19 39ee 3a37 3a33 3a66 3adc 3b70 3c26 3c23 3cd2 3d09 3cc5 3c31 3be7 3bc4 3b22 3a74 3a5f 39cb 3966 3a07 3a2a 3d73 21e7 16f8 198a 18dc 1877 186c 192c 19f9 191b 193d 1a9c 1a25 19d6 1af5 1a5b 1aa1 1a0a 19df 1a61 1b12 1bed 1c60 1c81 1b43 1a9d 2767 3e6d 3be8 3ba4 3ae1 3a8b 3aa1 39f3 3993 39b6 39b7 3999 39a0 39b7 39ec 39a2 39e5 3a2a 3a34 3a71 3b18 3b4a 3c79 3d33 30b2 1a86 168b 17f6 16b3 1567 167d 1728 1729 1723 185f 18b3 17b5 158f 1492 14ef 156c 175e 1866 18f5 1929 2418 3b90 3d5b 3ac2 39a2 3960 38f0 38d1 3927 3987 39c9 39b4 39a5 39bb 399e 398c 3993 39b3 3a2e 3a0e 3a5f
0fa2 0f99 10b2 1222 135b 149b 16cd 1688 23f3 3ad2 3878 3b10 3c30 26ef 15f7 1732 17f7 180e 18d5 183a 1879 17d5 1690 1452 2905 3c39 3ab0 38c3 3852 387c 38a2 3873 39d4 3ca8 2898 13fa 1888 1a2a 198c 19fa 18ef 1f72 3b8d 3a58 39f1 3a0c 3a28 3aac 3a15 3a79 3baa 3c31 3c9c 3edd 3e80 3cbf 3c6a 3d0d 3ee7 3e64 3cd4 3c52 3ba8 3ad0 3a32 394c 39fe 39e8 3cda 229f 17fa 1982 1965 18e5 18ef 19fc 1a49 18e1 1836 186f 18aa 17f4 1875 1851 1839 19e1 19e6 18e8 1aa2 1add 1adc 1c09 1c49 1c05 1dd5 3961 3ce9 3af8 3ae2 3ad9 3a4c 3a0d 39ff 3a05 3a68 3a55 3a21 3a7e 3a8a 3a32 3a6b 3a6b 3aa9 3ac3 3a5c 39e8 39e8 3a0a 3d3a 343d 17bf 1713 184b 165c 1698 17bd 18c9 1842 18a0 18e2 17c4 1648 150c 15ca 15fa 15a6 1730 17f1 18d5 1957 2193 332f 3c4d 3d2c 3a8d 39aa 39aa 39d1 3a0f 39fc 3a02 39e4 39d1 39cb 397d 3949 39ea 3a57 3a83 3a59
0e6b 1026 1062 10fe 12c8 148a 14b8 14bb 1887 39e7 3cf0 34e3 2223 1600 17dd 18b5 191b 190d 18b4 188c 1726 15fd 1552 2470 3c5b 399a 3893 3871 38ab 383d 3893 38f7 38da 3a3e 3c8e 2036 151d 19a6 19e8 19a4 17f5 31c8 3cae 3a39 3a3e 3a2c 39ee 39fe 3a28 3b96 3be5 3ddb 3d51 31e6 25c6 21a1 214d 2241 2968 36f1 3ec5 3d1d 3c20 3aef 3a11 39d7 3a9e 3af1 3cf3 1fea 184c 1905 1906 1895 186b 192b 19ec 1a31 1a02 19e9 1881 187f 1803 1833 1816 186b 195b 1908 1933 1b3e 1b09 1bbc 1c0a 1b8e 1b2c 3244 3d92 3b05 3a7d 3a25 3a7c 3a98 3a54 3a79 3a75 3a4d 3a9a 3a8f 3b15 3ae8 3b01 3aa1 3ac6 3acf 3a04 39ff 39e2 39c0 39f1 3df9 29e7 1557 18e2 17aa 1673 175e 1914 19cb 197d 1867 1798 15f5 1581 15d3 15dd 14ca 15e9 1651 1739 18d1 186c 1a0d 1f40 2c66 3b83 3ba9 3a8f 3a35 3a05 3a0b 3a40 3a59 3a4b 3a3d 3a22 3991 39c6 3a47 3a45 3aa8
0dec 0f09 0f8f 11b3 138b 12c4 15fb 213d 2d1a 2a72 1fb5 19c0 1756 17d6 1953 1a55 19c5 1980 18c9 17f5 17d7 169f 1930 3711 3a59 3814 37d8 3835 3881 3876 38b8 3921 38e4 38f8 3bcc 3359 1596 1930 1987 17de 2b4e 3d74 3b38 3a82 3a31 3a24 3a6a 3a2b 3a79 3be8 3e05 381c 22f8 1ae1 1af6 1bb5 1c69 1bce 1b5f 1d19 2e1f 3e64 3c47 3afc 3a33 39f4 3a43 3ca2 3811 18be 196b 193d 1941 1940 19cb 1a53 1a21 1ab0 1b73 1af9 183a 164b 15f9 151e 15b5 1770 1918 19bf 19c6 1b58 1c0e 1c58 1bb2 1c5c 1b87 2f24 3da5 3acc 3a37 3a54 3a7b 3a83 3ad5 3acb 3a1f 3a73 3a9b 3ad4 3b3a 3b43 3b0f 3aa4 3a71 3a7c 3a80 3a17 3977 3a0c 3a1c 3c40 380f 184f 17f9 16a2 164d 1801 18c5 1941 195b 189a 189d 171c 16ee 1769 171c 172b 176a 1848 1850 1887 18a1 1868 17af 17fc 2321 3aa4 3bb6 3a56 3a31 3a4d 3aa0 3ae9 3ac3 3a88 3a70 3a08 3a19 3a60 3a3a 3ac6
0d56 0e44 1035 11d7 108f 1f2a 349d 3b9b 3dd0 289d 1444 17a1 1814 1959 19ea 18cd 174f 1787 17fa 1784 176d 15e0 22e9 3bf9 38eb 387b 3879 38a4 3889 3899 38e7 3949 39be 393d 3aa9 3cb5 1c19 1449 1c64 30d0 3d70 3aca 3a84 39ed 39b2 39d0 39c6 39fe 3ac4 3cf0 39af 1e7b 19af 1bac 1c32 1d74 1d04 1bfb 1b91 1b35 1b69 2f2c 3db5 3ae3 3a4a 3a1a 3a9c 3ea8 28b2 170d 1946 1989 18d9 1910 18c0 1965 18c0 18c3 177a 1937 2540 2dda 3230 3121 29d0 1d89 163a 1779 1877 1993 1a98 1aad 1bb4 1b4e 1b67 326d 3e18 3bb3 3abc 3a9c 3a3e 3a61 3af6 3aa9 3ab1 3abe 3a77 3aed 3ade 3b4f 3b0b 3ac8 3a5b 3a65 3ac7 3a2f 3949 39b0 3a6f 3a83 3c56 1eb5 165e 166b 164d 1887 195f 1985 19dd 17c3 1747 1792 178f 173c 1703 1693 17c5 1837 1808 1814 18d5 183b 1737 17db 18a3 2608 3cbf 3a8f 3a19 3a78 3ab6 3a8b 3a6d 3a5a 3a2b 3a37 3a79 3a81 3aaa 3a8e
0d81 0ee7 10a3 0f3b 204f 39cc 3964 3783 3949 34c7 169a 182e 1932 1a14 1a08 1906 1863 18ed 19fb 19d6 1910 17aa 3195 3c2a 398e 3958 3963 3918 389e 392d 3956 399a 3a34 3ca6 3d44 391f 2c11 2e79 3a0a 3caf 3a95 39f1 3a09 3a1b 3a43 39c1 398f 39f1 3acd 3dbd 25b1 17d8 1b69 1d4a 1c51 1c69 1ca8 1bea 1c38 1b91 1b29 1d48 3840 3b8c 39ad 3a5b 3e00 3460 1989 1823 197c 1a35 1956 196c 194f 1963 1a50 1812 24ea 391d 3ea3 3dc4 3d29 3d9b 3e42 3c0c 2b1f 1658 1824 1a0a 1aa5 1b5d 1b5e 1aec 1c98 3962 3dad 3c44 3b73 3b1b 3aee 3b88 3be7 3b8e 3bc3 3b72 3b63 3b81 3cad 3d52 3c2a 3ae9 3aea 3ab5 3aaf 3a72 39b5 3990 39af 39ec 3d30 215d 14ac 160e 1712 1882 1983 19a8 1931 178f 159d 15eb 1617 168a 16e1 172d 16f4 177a 1764 17cf 1964 186b 17a5 17f0 1911 1ab7 345a 3c53 3ad5 3abe 3a6c 3a26 3a2e 3a68 3a08 3a29 3a4e 3ac7 3af2 3aab
0ce6 0de8 0e9b 185a 384c 37c5 3686 3706 378b 3c10 2656 14c0 1925 1993 1a73 1a50 19bc 18e5 1881 1948 15ff 242c 3c9d 3ab5 3a14 3a50 39ad 3957 3986 39b3 39ea 3ab0 3d37 3405 22e6 1a43 33a4 3e0f 3a94 39be 39ad 39c7 3aba 3aec 39ae 398a 39da 39ce 3bf0 371d 1917 1961 1a85 1af9 1ae9 1adc 1a29 1a8b 1a7a 1aa2 1bc2 197f 2b21 3e2a 3c7f 3e75 346e 1abd 18d1 1a3f 1a7a 1a2f 1aa4 1afd 1abb 1a08 187b 2722 3dbb 3dae 3b8b 3b48 3b65 3b75 3b81 3bec 3e8a 2e32 16b5 18bf 1948 1b33 1ca0 19c1 26cc 3ef8 3d4f 3c93 3c1c 3c6a 3bbf 3c39 3cc1 3c95 3cd7 3e00 3d8a 3927 35d1 36d7 3b7e 3dcf 3c25 3b10 3aa7 39df 3971 38ae 38c1 3998 3cb8 20f4 13fd 1575 1660 17d5 1939 1948 194b 185f 16db 15e4 14d8 14c9 1551 1702 1798 17a9 1752 17f3 18a9 194d 18f0 1944 1942 19dd 2944 3dd5 3b7f 3b1c 3a5c 3a43 3a92 3ab3 3a71 3a89 3ad6 3b44 3b56 3b4a
0beb 0d11 0eba 2bbf 3925 35e1 35ce 368a 37a4 3a32 3aba 208d 157f 19ae 1afc 1b29 1944 17cd 15fe 1436 2048 3a16 3b47 39f4 39ac 39e5 398c 3a2a 3a4f 3a2d 3b23 3d83 2adc 1928 1866 179b 2903 3d28 39aa 3966 39a9 3a73 3a36 3a17 3a0f 3a76 3a92 3af3 3e6f 2b02 17bf 1a87 1a3b 1a1d 19b6 1917 19ac 1a7a 1ad8 19fb 193e 16ed 2242 3d56 3800 291e 19bd 178b 19bb 1ac6 1a9d 1af4 1a98 19ac 19b9 1908 1fa5 3bfd 3bee 3a8b 3a15 3a57 3aa0 3a48 3ab6 3aee 3c0b 3ee1 2510 179b 1a48 1b58 1b06 1cad 387a 3e06 3d29 3cb4 3c23 3bf1 3c5b 3c93 3cbb 3d43 3e8d 3445 2438 1c0b 1aaa 1b0d 1ed3 2b75 3b38 3cc8 3aa5 39a7 38f6 38b5 3978 3a10 3ad7 1bea 157a 16bc 1736 18c7 1946 1915 17df 1749 165c 1641 15b7 1575 1470 1561 16a2 16a7 1659 1738 17de 188c 1939 19df 197a 192e 2317 3cf8 3a8a 3ab1 3afd 3a9b 3acd 3b18 3ab8 3b08 3b07 3b4d 3b34 3b0f
0bdd 0c78 13d4 35e2 36ae 3604 3628 36cc 37d3 390e 3b04 3b73 2950 1a4b 1742 16d7 1556 1477 1746 26c9 3a41 3b34 39fb 39ae 39ab 39d1 39f1 3a80 3aba 3b16 3e0f 2d87 1892 1a48 189e 1761 1c41 3954 3b6e 3964 38d6 3941 3916 3961 39dd 39ff 3a4f 3c77 3a91 1c4c 190e 1a52 1ae5 1ae0 1a83 19ba 1a38 19e1 192a 18ba 21e6 301f 3665 21ad 1ad0 1893 19eb 1a6d 1b11 1afd 1ae3 1b94 1b40 1a8c 1abb 1966 3208 3df3 3af9 3a7c 3a5d 3ab0 3ab5 3b0e 3af4 3b35 3b96 3e25 3669 17b2 193a 17db 1c61 354e 3e15 3ca2 3ca8 3bc1 3b8e 3be0 3c87 3d2d 3d97 3d92 294d 1b18 1a9d 19c6 19cb 19a8 194d 18fc 2284 3a2d 3be1 3a38 3986 3917 39e6 3d42 3390 15b5 16de 1768 17fc 18cf 19f8 195c 1877 17b0 156d 13d0 1454 16b4 1627 1560 1370 1402 1672 1710 1825 17e7 1a08 1b60 19a3 19ef 2386 3d31 3a62 3a56 3adb 3ade 3a9e 3aec 3acc 3b0f 3b37 3b3d 3b32 3b67
0c05 0b5e 1a88 38b7 3619 3642 3633 372f 37ae 38dd 397d 3b08 3d5a 390e 3002 29f2 290d 2d48 372e 3c69 3a46 3959 390e 3916 39d0 39bc 39f5 3a3a 3b4f 3cae 380b 1b17 1957 1985 18c4 17c9 173d 2572 3d11 3bab 397f 387f 384a 389b 3944 396d 3b66 3cfc 2513 1734 187c 198c 1aeb 1b97 1b69 1b17 1a63 1900 1956 2f6e 3d5c 3d87 3e67 213a 16e3 19cb 19f1 1986 1965 19de 1aa6 1aa7 1a94 1a69 1a2d 1e97 3bf7 3c79 3ba6 3bec 3c0c 3b87 3bb6 3be8 3b88 3bea 3c2c 3d84 3e20 1b36 1766 25e3 38b1 3e76 3c78 3c4d 3c27 3bd2 3be4 3c1e 3cac 3d76 3e58 28be 1935 1c74 1c28 1b1b 1a38 1999 19f6 1a03 18c1 2406 3cca 3b95 3ac4 3a3e 3bb5 3e1d 220f 1622 185b 16e6 1818 1885 19e2 1a85 1943 1764 1631 2427 326a 387a 396a 37a3 2ebd 1d57 12f2 165e 1788 1787 19bd 1c09 1afd 1a58 27c5 3e5f 3baa 3ad4 3a52 3ad9 3ad0 3b09 3b1e 3b8a 3bd5 3c3d 3c1a 3bd4
0c2c 0cc2 1daf 391e 3635 3638 3606 36e2 37a1 38c5 39be 3a63 3aea 3c61 3ca9 3d17 3c54 3b62 3a3e 3979 3908 392d 3928 392a 3957 393d 398e 3a0e 3ac1 3d83 292a 17c1 19ef 1a02 1a34 1948 183c 17c1 26c3 3b14 3d2d 3b2e 3a64 3abc 3be9 3dcb 3aab 250c 1764 194e 1a86 1aae 1b40 1b49 1a40 1b77 1a40 188a 3212 3ea2 3b3a 3af4 3d33 2fd6 1663 1999 1be4 1b45 1b26 1a7d 1be7 1c28 1c25 1b83 18ed 2b88 3ed8 3c8f 3c1e 3bc0 3beb 3bc7 3b25 3b7e 3c19 3cff 3ead 3b25 327e 30fe 37c6 3dcc 3d5b 3bf7 3b4e 3b87 3b9f 3b4c 3b5f 3bb3 3c72 3e92 32b7 1a42 1b2b 1ca7 1c40 1b06 1a82 1a89 1a1b 195a 1a14 19f7 3169 3dd0 3b6a 3c55 3f06 2ab0 1672 1808 19b4 18c7 193b 192a 1a00 1a2f 190b 1be6 33d1 3e41 3c5e 3b2f 3a5d 3b4a 3c99 3c56 2828 12c0 1624 180b 1900 1a38 1b68 19e5 32e1 3e7a 3bb3 3ab8 3a33 3aa6 3ad9 3b64 3b9c 3be2 3cb6 3cf7 3d87 3e63
0ce3 0d44 1af4 3965 36c0 370c 3690 373a 3833 3920 395e 398f 39ce 39a9 39d4 3970 391d 38f1 38b8 38c5 387d 38b5 392a 3965 3966 3994 39bb 3a14 3ad0 3c6d 1fe6 18af 1a38 1a80 1aa4 1a42 1925 1825 172c 1ebf 2dd1 3733 3ac9 3aec 36e5 2beb 1d14 1681 17bc 1802 17e7 17be 1887 1805 1795 17c7 16b1 2804 3e36 3b10 3a4d 3a5c 3b13 3c43 20f8 166c 1a2f 1b01 1aed 1afa 1aa1 1ad6 1a87 1802 2037 3b9c 3cbf 3bec 3b46 3b3d 3bc6 3c48 3bfc 3c13 3dbe 3db5 2c8b 1df9 199c 35ea 3ea0 3b73 3b4a 3b34 3a57 3a40 3a7e 3a84 3aea 3b49 3c57 3e0d 22e1 1a60 1af5 1b5a 1bba 1a96 1a98 1ab8 19f7 18db 1986 1999 2483 3f45 3f00 3c93 2969 1719 1771 17b7 1857 182c 16af 1768 1804 1831 1c33 3693 3e10 3a88 39fe 39a8 394b 398f 3991 3ab2 3d55 24d5 12de 169b 17e4 1961 197e 224b 3d5f 3c94 3bca 3b96 3b59 3a98 3afa 3b82 3bd9 3cd4 3f21 3d28 3662 30a5
0da7 0e24 14f7 3636 383b 36f1 36fa 37b0 3839 3885 38cc 3931 39aa 398f 39f6 39b1 3937 38e7 38ea 38ec 38f8 38b9 394a 391a 390e 396a 39c9 3a17 3b14 3ad0 1c32 1941 1b1f 1ab3 1a6d 19f2 1911 17f9 1774 17b0 18bf 1c09 1e5d 1cf6 1a22 181d 17d2 17f1 185c 18e5 18b7 181b 180f 17dd 16ad 16a0 1919 3782 3ba7 39aa 397e 3a48 3a9e 3bc4 396e 1f44 16cd 1a06 1a69 1b51 1a2e 186a 1711 1f3c 3783 3db2 3bce 3b55 3b5d 3b9c 3bc6 3ca4 3cd9 3d8b 3c79 25a6 19f4 1a89 1976 2c4c 3ef1 3b23 3ad7 3ad4 3ab9 3ac8 3a5c 39df 3aa1 3aec 3dcd 3620 1a19 1aa4 1b91 1acf 1b49 1b80 19c5 1a91 1abf 194d 176c 1b8e 2744 3612 2d53 1ef5 172d 183c 1965 191d 18b9 18ab 1669 16f6 190b 1896 3169 3ed7 3adc 39e4 39be 39f0 39de 3997 39d3 3a07 3b7a 38e3 17f5 1558 16ec 1691 1b8c 36d4 3ded 3c58 3c01 3c10 3b9c 3b10 3b9a 3bdc 3ca6 3dc3 306f 2132 1aa6 18d6
0df2 1035 114e 2af0 3b55 376c 376d 37f7 38d4 38ec 3954 39a9 39c4 395c 393c 3914 393a 38e6 393c 3937 3912 3924 397c 3962 3936 39c0 39ff 39ca 3a73 3b5e 1d6c 18cb 188f 1851 18d7 18e4 183c 1849 185d 17d1 17ab 188f 1846 180b 18c6 1849 17f1 189c 19c6 19ba 19ba 1959 1978 18ce 17f9 1892 2166 3d0d 3ada 3a3c 39e4 3a65 3aca 3b66 3d54 3c60 2c62 1d60 18aa 18f2 1873 1cb8 2ad6 3b68 3d65 3ba5 3b0a 3ae6 3b2e 3b98 3bf5 3c54 3ce8 3e2a 26a2 19c6 1bf3 1b4c 1a0c 1f3a 3b68 3dde 3b70 3b80 3b42 3b25 3a98 3a86 3ad8 3c1a 3dd3 23c5 1903 1b16 1bb9 1aff 1b11 1a68 19dd 1954 18bb 1bdb 2f02 3b5f 3da9 1f05 183e 196d 19bc 1a76 1b07 1ac2 1a41 19e9 1843 1685 17f4 204c 3d6e 3c9e 3a5c 39dc 3a38 3a39 3a00 39e9 3a6f 3a74 3aa6 3dec 2368 1219 14e9 1cac 354f 3e09 3bd6 3bc2 3b98 3b80 3b62 3b7e 3c88 3d73 3da2 2772 1870 18d7 1947 1873
0e38 107e 1268 1a11 379c 3ac8 37d1 38ad 38bf 38fb 3967 392f 393c 391f 3953 38fb 393f 38fd 3921 38d1 3884 38f6 3985 3949 3936 39a6 39b5 3977 3a05 3cb4 225d 1629 19bd 1906 19c1 1a23 196b 1945 193d 18b3 1818 17d5 1814 185d 1a1b 1b2e 1b1f 1aa3 1aae 1a9f 1a24 1a29 1adf 1984 1994 19d4 26fe 3df0 3b5e 3a8b 3a6b 3a5a 3a42 3b84 3be0 3c8f 3e23 3b71 3620 3451 365d 3bed 3e95 3ca9 3bef 3b57 3af6 3a71 3aaa 3ad4 3b93 3c07 3e64 32eb 1ab7 1d84 1cc6 1cdc 1aec 1921 26b0 3db2 3dde 3c37 3bb5 3b3d 3b4f 3bb8 3d38 3e47 289a 177b 199c 1a33 1c14 1c3d 1a9d 19da 19f1 18f5 1fcf 3974 3f37 3d6d 3eeb 25a8 17f8 1a67 1af7 1b6b 1b7f 1c48 1ba2 1a4e 1989 17b0 17e8 2db9 3ec4 3bd7 3abb 3aac 3a89 3aa4 3a40 3a59 3ac4 3b15 3cc5 3fbe 2ce5 1b8e 2b70 3b05 3d72 3bad 3b6c 3ab8 3acf 3b2a 3b2a 3b58 3c7f 3eaa 2903 17c4 195d 186b 1854 1796
0e18 101f 1345 15a1 2004 38c1 3c3d 3a9e 3965 3a09 3a3c 39c0 3900 38db 391d 38b6 38c3 38c7 38b7 3890 38d0 38ed 38f8 38ba 38f3 3940 3943 38f6 396d 3b6d 3031 15a2 1945 18d3 1883 18ff 1936 18f0 19c2 1910 18d9 18e5 1984 1996 1a3e 1ab4 1b18 1b39 1aa5 1a0e 197f 19d8 19c2 18fb 1af2 1a57 27ca 3e27 3b65 3a7c 3a38 3a9e 3aff 3b1d 3af8 3b28 3b55 3c29 3d36 3d71 3ceb 3c80 3c50 3ba2 3b04 3a5f 3a94 3a1a 3a61 3ac9 3b2b 3bc8 3e83 2540 1a1b 1cd3 1d63 1d4c 1b24 18d3 1941 25e9 3964 3ebb 3e64 3dd5 3e54 3f00 3a3d 26a0 17e1 19a1 1944 1975 1a55 1b9b 1a9f 19e9 195c 1bf0 38b9 3dca 3ae1 3b52 3d51 34b0 17c9 1a52 1a07 19f6 1a38 1b09 1bae 1b4f 194f 1876 1df0 3b11 3c47 3b6a 3ad3 3b19 3afc 3b35 3b12 3b15 3c4b 3d7d 357f 2748 2d52 3db2 3dfe 3bb6 3a8d 3a95 3a9b 3a0a 3a1e 3a4c 3a81 3aab 3cfd 3558 194e 1aaa 1974 16f5 1794 1841
0e15 1076 1414 1690 15df 1dca 3069 3b00 3d00 3c44 3aa0 39ea 3897 38f1 394e 38ba 386b 384e 385a 3838 3881 38cb 38cf 38c7 38d9 390b 38fa 3901 3949 39e3 3be0 2081 15d1 195a 18f7 199a 19a5 1a24 1938 1898 18df 18f7 1826 1985 1a1f 19b9 1a17 1a14 19f6 190a 1969 1913 1896 1961 1ae1 19fa 254f 3e3f 3b77 3abb 3afa 3b2a 3b2c 3ae2 3ab6 3ac0 3aa6 3af4 3b57 3bc5 3bc9 3bd2 3bd0 3b67 3ae0 3a0b 3a49 39d8 39d6 3a69 3aaf 3bb0 3bfa 1d65 19f4 1b3d 1b12 1b93 1abf 1925 1917 18ba 1d31 2753 2f6d 31ec 3007 27cd 1c92 187a 18f9 18fd 189e 17e3 18dc 193a 1a41 19fc 185f 2de5 3ead 3aeb 398d 3a4f 3b6b 3e5b 2adf 17c0 19be 1abf 1b06 19d2 1a59 19e2 17c7 19ef 34ac 3d2e 3b43 3a41 3a28 3a8e 3b26 3b69 3bb2 3d02 3c51 27d2 1819 150a 247f 3ed8 3b9b 3a32 39c4 3a15 3a12 39c1 39fa 3a10 3a87 3b1b 3e12 2595 17fb 198d 184c 17fe 18ad 17e1
0f0e 11a5 149e 1661 1762 183c 19fc 1ee3 280a 365a 3cbb 39f1 3984 38f0 38d7 385b 3823 3857 38a1 387b 38ad 38a9 3889 38ee 38cf 38be 388d 394c 3a06 3ac2 3c0d 38de 1d6c 170f 196d 1997 19c8 19a3 19fa 19c8 1989 194f 18e8 19c9 1928 1911 192b 1995 1906 1905 1927 1911 1944 1981 1a24 1a5b 1e83 3a73 3c89 3b3e 3c08 3be4 3b25 3b24 3aa3 3a80 3a72 3ab1 3b1f 3b48 3b74 3b71 3b9f 3b44 3b2e 3ad3 3a3d 39e0 39ff 3a53 3afe 3bd2 3b18 1c17 1aaf 1b20 1c6b 1b33 1a2e 19f3 1960 1968 195c 1936 1a15 1af7 1981 1a0b 19b8 1964 193c 18cc 1961 1870 1889 1865 18b2 18cf 1ce9 3a74 3cac 3acb 3a98 3a3a 3b1e 3cdc 3e2f 2d0d 1a4e 193a 1991 1909 1850 174a 1ecc 34b1 3da9 3af5 3a8e 3a43 3a23 3a83 3abf 3b2c 3ca4 3cf9 23b5 16d4 188e 1836 1c3e 3a44 3c58 3a19 39e6 3a2e 3a26 39f2 3a5e 3a3e 3af7 3d66 37fe 18f9 184c 1813 17a1 17f8 16f3 1621
0fed 1134 14f4 1750 17ff 188d 19a3 1a23 1974 1bb7 2ebf 3d05 39b1 3908 387a 37fb 3820 3808 38ae 387e 3877 388a 38b0 3896 389d 3903 3920 39a1 3a25 3ac1 3acb 3c57 39a0 267c 17f0 14dd 178a 18e2 18f9 196b 1931 192b 1847 18b9 1924 19c9 19b0 19d3 199a 199e 1ab8 1932 1964 1988 197d 1aa2 1a7e 2e30 3f35 3caa 3c40 3c40 3b16 3ad6 3af8 3ac2 3a8f 3a94 3ace 3b19 3b9e 3b59 3b6d 3b2c 3ad4 3a8b 3a69 3a50 3a37 3a42 3b02 3ba7 3bf5 1d45 19b6 1acd 1c80 1b5f 19c5 19d8 1a4a 1933 18ad 18b4 187f 194f 19ba 1ae6 1ae3 1a9d 198c 1962 197e 186e 1846 185f 185d 18b4 23c7 3e35 3b56 3aa7 3ab4 3a51 3a97 3b52 3cb6 3ec3 390a 2c27 2378 21e4 255e 30ac 3c72 3d53 3b39 3a72 3a03 3a5a 3a20 3a54 3a7c 3b38 3e1d 2948 16f4 19b9 19bb 18cb 17d6 2a68 3e30 3afc 3a46 3a3c 3a91 3aea 3a8a 3aad 3cae 3d8d 2284 16ab 195d 189c 176e 16c8 15db 14db
109d 11b4 157c 1721 170b 17cd 18fa 194a 18cf 18e1 19cc 304a 3bdf 3935 37e7 380b 3830 382a 3854 384c 3851 3889 38a1 3897 38f7 3953 3968 39d6 3a7e 3a75 3a2d 3a75 3b88 3cdd 37cf 2ce5 1ca3 149d 17a7 1866 1834 197e 192d 18c7 19af 1a95 19ed 1a7c 1a11 1a6c 1a09 184f 199a 196c 199c 1a6d 1b00 1f2b 36ea 3fcf 3cdc 3b7e 3b91 3b33 3b1d 3b13 3aff 3b23 3b54 3bb8 3bbb 3b5a 3ba7 3aeb 3a50 3a2c 3a5d 3a7c 3a76 3a52 3a99 3af9 3ddf 2482 17ad 1ad5 1c06 1ab4 1940 1a62 1a1d 19a5 191e 1950 1823 18c3 19dc 1a99 1a1d 19ee 1997 1a42 1995 1933 18c0 183e 18ab 18e3 2681 3e50 3af5 3a68 3a5b 3a99 3ae1 3b14 3bae 3c7c 3da4 3ec0 3e33 3dfe 3ecd 3e95 3cdb 3b83 3b1c 3a99 39f4 3a25 3a02 3a7c 3afc 3c4c 3823 19af 18a9 197a 186a 179f 17bd 1930 2e78 3e37 3cd7 3b53 3b4d 3bc5 3ce0 3e46 3b97 250a 15d9 1856 18ae 18c1 1761 163b 1586 145c
1114 1283 1598 16e3 1738 184e 19e4 1986 190c 19b2 1979 1d0f 387a 3999 382b 3857 3883 3872 3844 3870 38a7 3875 38f1 38f1 3944 395a 3980 39c6 39fb 39d9 391f 396b 3990 39a5 3af9 3cc8 3ac6 2661 14bb 17d6 1859 1897 190e 18d4 19d8 1b53 1b60 1c70 1b44 1b16 1af5 1a17 1a94 1a32 1a16 19fc 1a41 1b4c 2036 342b 3ed6 3e2e 3ced 3bc9 3ba9 3bb9 3ba6 3b7a 3b8e 3c31 3c02 3bc0 3bc0 3ae0 3ae0 3aae 3a65 3adb 3b18 3b0f 3b64 3b78 3d8d 33e0 17bd 1a18 1c23 1bd9 198e 1a7a 1a78 19a7 199b 1a4e 189a 1907 1a11 1a7d 19b9 19d2 1984 1a17 19c2 1a66 19b6 1906 189f 189f 25d3 3dea 3ac9 3a68 3a55 3a16 3a24 3a77 3aa6 3b38 3b8c 3c06 3c50 3c88 3c78 3c2b 3c22 3bad 3b2a 3ad3 3a53 3a55 3a3f 39ec 3aba 3d87 2e15 1726 1910 198d 1942 17c9 16ab 1644 1900 2607 3602 3c28 3d6b 3d57 3a5c 2fcd 1e15 1720 1887 170a 17b8 1780 174c 16d7 14e9 1441
1174 1368 15bf 1712 17a4 18a1 1a91 19b1 1a12 1a0f 190d 16f9 2c92 3c10 398d 38f8 38fa 391a 38cd 389f 38b8 3932 3998 39c2 3a05 396c 39bb 39fb 39ce 397f 3935 38d7 3996 39a8 3969 39c8 3acd 3d2a 25f3 14a1 1803 1967 1a3c 1a20 1a70 1c13 1d0e 1c52 1bb0 1ad1 1af1 1a79 1a19 1abb 1bed 1a85 1a4b 1aa3 1b42 1d0b 26a4 3287 3c58 3ef6 3cd7 3c6b 3c30 3bfb 3b89 3c0f 3c64 3c79 3bff 3b60 3b44 3b0a 3b43 3b92 3b61 3b03 3b70 3baa 3bc8 3dc6 27f3 16e3 1a37 1ae0 1973 198e 1993 1924 19b7 1b5b 19c2 1978 1a52 19f2 1980 19ac 19d8 19b6 194f 197c 19da 193d 190a 193e 20f0 3cf1 3baf 3adf 3a52 3a51 3a6f 3a90 3a5f 3a60 3b49 3bc1 3bff 3c46 3c1d 3bb7 3bd0 3bcd 3b41 3b4c 3ae5 3a92 3a70 3a42 3af0 3de9 2962 1808 19c0 1a06 19ac 18f0 174c 15ba 1749 17d9 1a79 1f1d 216b 2113 1cfc 188e 1830 18cf 1912 188f 1898 175f 182c 1672 169f 1679
1048 132d 1602 1673 165d 1921 1a44 1928 19fc 1a3a 1965 172b 238a 3c68 3a10 3981 3964 3941 38eb 391f 3970 39b6 3a75 3af3 3ad2 3a37 3a75 3a64 3a2e 39be 39bd 3931 3964 39df 39f4 3a2f 3a12 3b65 3ad3 1b26 1739 1896 192e 1a02 19c4 1a8a 1a8a 1a67 19f1 1a60 1a15 1a63 19d2 19a0 1ab6 1b0c 1b82 1bee 1c4b 1c5a 1b1e 1c37 21f9 32f3 3ec2 3d28 3c9f 3c84 3c1a 3c3a 3cad 3c62 3c60 3c24 3bfd 3bf9 3c2f 3bc0 3bb9 3c0a 3bc6 3bc7 3beb 3ce1 3cc7 274d 170f 1746 1893 190c 1807 1859 1844 19e4 18d2 197c 1a98 1a5b 19cd 18be 1916 1996 18ad 17ef 1886 1806 17d4 1860 1a26 3618 3dca 3ac6 3a3b 39f9 3a74 3a2d 3a17 3a86 3ae4 3b04 3b2d 3ba5 3c31 3b57 3b1d 3ae9 3aef 3b10 3af6 3b03 3aab 3a54 3b19 3de9 28cd 1698 1985 1913 1853 181b 178c 1611 1624 17e9 18c7 1969 18c7 180a 1990 1985 18ba 1925 192d 175c 180c 1766 1754 15fb 15a3 1c3d
0d17 109a 14d6 1601 16c3 18e1 1928 18f6 19de 1aae 19c9 182f 20ba 3c1f 3a73 3a0b 3a37 39ae 3977 397e 3a23 3a52 3b13 3b5a 3b31 3ac2 3b3f 3ac8 3a57 3a63 3a53 3a44 3a01 3aa0 39e2 3a1c 3abf 3ad7 3dbd 2b39 166a 1781 182f 1964 18bd 1964 19f4 19c0 19d0 19d1 1996 193b 1975 1951 1a56 1b30 1bd4 1bb3 1bb6 1bcb 1bd1 1b66 1bb6 1c86 3039 3ec6 3ca5 3c45 3bc4 3bcb 3bd1 3b62 3b56 3ba8 3b74 3ba7 3bbe 3b21 3b6c 3bea 3be2 3bc9 3c04 3bcc 3c95 3db3 3346 2436 1904 15df 1853 17b6 1857 183a 1692 180c 1a1c 1a21 19ab 193b 1949 18bc 18b4 1884 17ba 178c 179c 17bb 17a8 2475 3d62 3bfb 3a25 3a6c 3a8f 3a80 3a32 3a77 3abf 3aa0 3aa5 3b16 3b53 3b6a 3b1a 3aa1 3a3b 3a76 3a57 3ad9 3a7d 3a62 3acc 3cf0 2da8 14f3 1738 17a7 1720 1706 17b7 170d 1756 1719 188e 1927 18bd 1711 1877 19ba 192c 1926 1894 1708 1789 17a2 16ab 15a6 152f 24bb
28e2 220b 1849 12f5 15be 18d0 192b 1967 19b8 1a17 1992 17cf 21db 3c5e 3a4d 39d7 39bd 3975 3971 39a3 3a63 3abf 3ac8 3b1a 3b38 3afd 3b07 3b33 3acd 3a42 3a55 3ace 3aa5 3a65 39bf 3a06 3ae9 3ac9 3cd1 342f 180d 1a4d 1910 199e 19bb 1981 1a33 19a8 19a3 1a42 1999 1986 1902 1984 1a3b 1b73 1ba6 1b3e 1b91 1c24 1baf 1af4 1c40 1c90 1dc8 3726 3d7b 3c3b 3b38 3b2f 3b13 3aec 3aef 3ae0 3af1 3b29 3afb 3b13 3b73 3bae 3c02 3bee 3b8d 3b81 3b86 3bd1 3d45 3e00 3908 260a 1534 170e 183f 17e5 1586 16f5 18c0 194b 198e 1a21 1983 18b0 182b 18a1 18c7 189c 18cc 17fe 17c7 19b2 2aca 3da4 3dd8 3c17 3afe 3ac6 3aa9 3a6c 3a26 3a62 3a56 3a82 3aa6 3ac3 3a6f 3a7d 3a1e 3a1d 39cf 3a0e 3a37 3a5a 3abf 3bb1 378f 16d9 1642 1703 1770 16f2 1685 1695 16d3 1755 177d 1835 1756 16ec 1788 1930 184f 1724 183e 17f0 16f9 1795 1698 14ee 14ae 27f4
38e2 3a8c 3866 2808 14ae 1730 1861 18a4 1947 19a5 1969 1634 287e 3c2b 394a 395a 396a 3964 3966 3985 3a0b 3a6e 3a61 3ae5 3ba2 3c59 3cb4 3d49 3c9a 3bee 3b7f 3b44 3ab0 3a15 3a2f 3a2d 3a35 3a62 3c56 3640 1890 1a15 1941 1978 191d 1915 1a1f 19d1 18b0 186b 17f6 184e 1901 19fd 1b1b 1ad4 1b1f 1b6e 1ba7 1b8b 1b73 1b39 1b44 1b4f 1b1b 28af 3e2d 3c52 3b36 3af8 3af6 3a8d 3a5c 3a4e 3aad 3b09 3b5d 3b76 3b9d 3b9f 3c02 3b97 3ac3 3b24 3b27 3b11 3b33 3ae4 3c2f 3e23 2a31 13ce 16b6 1764 15e4 1617 1700 176e 183e 1926 18e8 188e 16d4 16cd 1760 17c3 18b8 179d 1662 17f1 1a30 2586 3563 3cbf 3e1f 3bdd 3ad8 3ac5 3a6a 39ce 39bd 39da 3a39 3a49 3a41 3a62 3a50 39c2 3967 39ab 3a0c 3a17 3a1f 3a98 3d42 260b 1220 162d 16a3 15b8 14ab 14d3 154b 16c4 16b3 16f5 1696 16a7 1664 162f 16ae 15b8 1770 17a2 158f 1693 14f9 132f 13cf 254b
35e1 3688 3879 3c2d 2ede 1525 16ed 1698 1841 192e 17b6 174f 34bc 3af0 394e 391c 38de 3896 3896 38f1 39a6 3a5d 3a9e 3d02 3bfe 370f 341a 34f2 38fe 3d85 3d7a 3b20 3af6 3a2b 3a2f 39c8 39ea 3a24 3c00 358d 17c6 193b 187b 1911 18e4 184e 18a0 18e5 182d 18a4 181a 1805 1882 1949 1949 18a0 1823 17fd 18cd 19a3 1a2f 1ae0 1a88 1aa1 1b42 202d 3baa 3bf0 3b25 3aef 3a87 3a89 3a73 3aea 3b00 3b32 3b4c 3ba1 3bae 3b5b 3b73 3b56 3ad5 3b0b 3ab7 3aad 3ab6 3a57 3ab7 3b19 3d8f 2216 14a5 1738 16cc 161c 17b6 18ae 196d 19d3 1939 190d 18eb 1828 1792 18d5 1905 1856 1747 17d1 18a8 1901 1b85 21e1 2f7a 3d4b 3d28 3b74 3aa8 3a5f 3a83 39f4 3a5d 3a59 3a8c 3a7f 3a76 3a0c 398a 3965 39da 39b0 39f9 3a61 3b4d 3a45 1e29 127c 14ad 153d 13e7 1454 153f 1672 164a 16a0 160f 1699 16f6 1680 16b3 16ba 1749 1706 155d 1633 13d8 12ea 12d4 1c05
3570 3617 369b 371e 3bf3 291a 1420 17ec 18bd 18c7 1653 2697 3c51 39d1 395f 3932 3927 393f 3976 39b2 39d5 3bb7 3c6d 2e33 2044 1afb 1a95 1b5b 1d2b 2567 357c 3dac 3b77 3a83 3a11 39b5 39d4 39ec 3d39 3008 1769 1966 1a84 19d7 198f 18a6 1899 18eb 19b7 1a15 1961 188f 1745 17eb 1836 1834 18d3 1777 187b 1abd 1aec 1b0f 1a9e 1aae 1b3f 1d97 3994 3ca9 3b76 3b2c 3ae1 3a95 3ad3 3ba3 3b82 3b27 3b8b 3baa 3bec 3b91 3b0e 3acb 3aca 3ad9 3ab8 3a71 3ac7 3a7d 3adf 3afc 3ccc 342b 16c8 17ca 1756 15e8 17bd 19b6 1aa7 1ad8 1a70 1a46 1b1a 1abb 1979 1a56 1aa3 19ac 1a58 1b88 1b23 19f1 1963 19d1 1ad8 26e2 3cd6 3d1b 3bd2 3bfb 3bf7 3b41 3b31 3aaf 3ac9 3a7d 3a34 3a1f 39f3 39b5 3a08 3a34 39e8 3a05 3a83 3ba9 3abc 28af 16d4 11de 132e 147e 1503 1550 155d 15b6 16ad 1702 17a2 17a8 1824 186d 172c 16d6 1625 15c3 1477 12d4 1262 1578
35ae 35d0 3668 3748 38db 3944 1a27 17a1 1775 15bc 22c8 3a6e 3a32 395a 3945 3940 3968 39f4 3a0f 3a15 3b60 3c20 2523 18f3 1a3a 1ac5 1b85 1bdd 1cd9 1a9d 1c7d 3088 3d8c 3b5a 39d7 39af 39dc 3ad2 3df9 2333 189d 1a51 1b43 1b12 19e7 19d1 19e3 19c7 1a54 1884 1886 1dcb 22f7 247c 2195 1bd5 170d 1880 19eb 1a7d 1c4a 1c4e 1bae 1bf6 1c2d 1dca 3a27 3d12 3c25 3bce 3b21 3b45 3b96 3b95 3b97 3b74 3bdc 3c4a 3c94 3c65 3bf1 3bc2 3ba9 3b34 3b1f 3bab 3b95 3b12 3b5c 3b44 3c16 3c63 1d06 18bd 1787 16e1 1812 19d3 1ab1 1a31 1a37 1a24 1a4c 1b85 1a9f 19f3 19a5 19ad 1a2a 1ab7 1b12 1acd 1b6f 1b64 1c0c 1ba1 2a88 3ee6 3d49 3ccf 3c46 3c3c 3bba 3b3f 3b35 3b3f 3b86 3b00 3aba 3ad6 3aab 3af3 3a5b 3a80 3acb 3b0f 3bb1 3d05 39a9 2eb6 19c7 1131 1431 14bf 159a 1587 169b 173f 179e 1830 1862 18de 170a 165d 1615 162f 1528 12e0 11d0 144d
3673 36d1 37db 37ce 38a2 3e19 25bd 12eb 186a 296f 3aec 3ac1 398e 39b3 3986 396b 3984 3a39 3abb 3b14 3d2c 2554 17f7 1b17 19e2 1a26 1a68 1acb 1ae4 19db 1b7a 1b66 3432 3c80 3988 3a08 3abf 3e47 33a3 18b0 1a61 1af5 1c27 1b66 1ab9 1a78 19f4 1a0d 16e8 1fb4 32a5 3c41 3df0 3da6 3d2a 3a6d 2d94 1a00 177e 1a0f 1af3 1bc0 1b6e 1bbf 1b37 1fb7 3c6c 3c4c 3bb2 3b45 3b05 3b65 3b78 3b4e 3c58 3cb0 3cca 3cb5 3d2e 3d46 3d05 3cd4 3c40 3c2d 3bdb 3b90 3b31 3b47 3ba3 3bad 3c65 3e77 2117 1910 17aa 16bc 18a1 195c 1968 1969 18e6 189d 1885 1a86 1963 187d 18e2 199b 19f1 196b 1aa4 1a62 1b54 1be9 1b24 1b83 1e10 37db 3eab 3d30 3c7c 3c0c 3b60 3bc4 3b83 3bc7 3be8 3bd2 3c02 3be0 3b72 3b63 3af9 3aaa 3a9b 3b45 3abb 3a9a 3ac9 3c6f 3a52 212a 1218 1596 14d5 1606 16fa 16cc 1729 18b3 1935 18fd 1859 17aa 1693 1678 1543 1353 11cb 1240
3817 384b 3868 3acf 3bd2 37de 2f39 2eae 384c 3b70 39e5 398a 3953 3941 392a 394f 3975 3a09 3a90 3d23 30bd 180f 1a2c 1964 18c4 18e0 198e 1a4a 1a33 1a8b 1ac2 196b 21d1 3c10 3a54 3aad 3dfe 381d 1be0 1872 1abc 1c37 1b00 1ad7 1a78 1a51 1a3a 1727 2454 3bfd 3c9e 3a76 3a58 39e8 3a3d 3bb9 3e15 3807 1c8c 18dd 1a1f 1c0a 1c52 1b67 1982 2a58 3e17 3bcc 3b30 3aa9 3ac2 3af2 3b46 3bc7 3cbf 3d61 3e78 3eab 3cc8 3c1b 3cd2 3e9e 3e39 3cc2 3c6d 3b6a 3acd 3ad2 3b06 3b24 3c76 3e03 1fc3 1997 18aa 18ea 19e4 1a7d 1a3d 1961 197c 1902 1981 19f5 18f8 1890 1875 19f9 1b0e 1afc 1b16 1b91 1ae4 1cc0 1bce 1acf 1bb1 2ccc 3f5f 3d56 3c9c 3c4c 3bc2 3bea 3b91 3c13 3c64 3c3a 3c73 3c6f 3c59 3be9 3b76 3af3 3ad3 3b1b 3b64 3a99 3a42 39f8 3bc9 3b47 1be2 14cc 14e3 1609 177a 1789 17c3 1945 1a5c 19aa 1944 17de 16e3 16ad 167c 148d 1392 1279
38f8 3978 3c3c 3377 2204 17f6 28b2 3eaa 3a09 38ad 38dd 38e9 38ce 3945 3964 391b 395a 3988 3ac5 3d2c 21a7 18de 19b9 1a7d 1980 19c9 19c0 1a20 1ac7 1b64 1ab0 1a2f 1830 3584 3e93 3d75 33ac 1cab 17a5 1a0d 1adf 1bdb 1a9c 1994 196f 1a4d 17ff 2118 3c3c 3b82 39ea 3919 38f6 38ef 3960 3a6a 3b54 3da7 3670 199f 1b1c 1cc5 1c54 1a35 1d9d 399d 3d68 3c13 3b88 3add 3aea 3b21 3bc7 3c7b 3ce9 3ed9 35a9 2874 215e 204a 21fe 289b 34fd 3e93 3d80 3c49 3bde 3b25 3ad9 3ae6 3cef 3b6a 1c89 1a0d 180b 1991 1a06 1b04 1a2e 1a79 1a64 1976 19ad 19ce 198c 1839 1874 1aba 1a8b 1aa7 1b8e 1be6 1be9 1c28 1c7a 1c0e 1b85 268f 3eea 3d03 3c30 3baf 3b67 3b80 3b98 3c0f 3c7c 3c81 3c9c 3cae 3c91 3c31 3baf 3ad3 3b15 3aaf 3aef 3ab7 3a0e 3978 3a28 3d15 30a7 1344 1501 1600 16fa 168f 17b8 1a30 19c7 18e4 183e 181c 1754 176b 1698 151d 139d 131b
3967 3c71 2ab1 17fb 1720 1768 1fa0 3ba7 3a37 38e6 38be 3915 38bb 388f 390c 38e6 3943 3981 3c8c 367c 1963 1929 19e6 1b2c 19da 19f3 1956 1913 195f 18df 1713 182b 1f2e 2eeb 3042 2479 19dc 18f6 19ea 196c 1b47 1c0e 1b06 1abb 19d9 192f 191b 34c2 3d8c 3abe 3a28 39c2 395b 39bf 3a33 3a67 3b47 3bc6 3ec8 2734 1859 1b4a 1939 1b4b 3401 3e14 3cb7 3c2a 3bb2 3bc4 3baf 3bb7 3c99 3d79 3dfd 29d2 1be1 1b38 1c4c 1d0c 1d09 1d9a 1da9 29ac 3d1b 3d58 3c4a 3ba3 3b2a 3b82 3e6b 31eb 18f3 19db 1965 1a77 1a89 198d 1a02 18cb 1906 18be 16dd 174d 1a24 1a64 18ac 1586 17df 1a30 1aeb 1b84 1b87 1c07 1c12 1cdd 1b51 2592 3ed4 3d0f 3c21 3b83 3b5d 3b2a 3b18 3ba0 3c75 3c9c 3caa 3c94 3cb8 3c4a 3c0e 3bce 3b5c 3acc 3a86 3a79 3a31 39b6 3a01 3b92 3a49 1830 1485 14f0 1664 1738 1866 1a4d 19f2 17a6 1743 1797 175e 1673 15e0 1501 142d 12ec
3d00 2dce 1661 187c 189e 175a 1873 3047 3cf9 392d 38a4 3926 3950 392d 3968 39a5 3952 3aa9 3d58 240b 17a8 1954 1a22 1aca 19e2 1890 189d 179a 1781 176d 2557 36c3 3e69 3158 174e 1a11 1b59 1b0b 1ab5 1ab9 1be1 1c7f 1b72 1b9f 1a94 1905 228e 3dd0 3bfe 3b45 3b36 3ac1 3b0e 3b9d 3b83 3b24 3baa 3bcd 3e37 34cd 159a 17aa 20fe 3597 3dd6 3c5d 3cab 3c53 3c39 3c27 3c5e 3ce5 3d8d 3e94 2933 194a 1bb7 1c0f 1cc7 1e30 1d36 1d9d 1d8c 1ad5 2a81 3ece 3cc3 3bc7 3b4d 3cee 3d71 20a6 186f 1a71 1a20 1ace 1b01 1a89 1add 1a0f 18f1 19be 285d 3575 3a1b 3a90 3901 300a 1eee 163a 19ab 1a2b 1a4b 1bb2 1cac 1c2b 1bce 2931 3e8c 3cc4 3bdf 3bc6 3b87 3b1f 3aed 3b5a 3c86 3ce5 3d24 3cb1 3ca8 3cb1 3c74 3c00 3ba2 3b6d 3af6 3a87 3a18 3a3e 3a5e 3ac9 3cdc 1d00 1408 1565 169f 180f 18bf 1941 1ab7 18ae 1732 16ca 16cc 1614 1555 1526 1489 13e0
390a 1a58 18d8 1966 1968 1790 1712 1c87 3606 3d18 3a8d 3991 3983 39f5 39e8 3a7f 3c10 3e2b 2a2c 186a 19a4 1991 1a1f 1ac9 1944 17f8 1826 18fb 19ae 3073 3d90 3c24 3beb 3969 1b72 1ad5 1b87 1b2d 1b36 1c18 1c25 1bd7 1c26 1bdc 1bee 1aad 2fcd 3e6b 3bd5 3b30 3af2 3ab6 3b38 3bd5 3bd2 3c1c 3cfb 3ebf 3dfa 3690 280c 3287 3d3b 3dd1 3c89 3c5f 3c99 3c58 3c8a 3c58 3cd6 3d6c 3f5e 3313 1abf 1d55 1beb 1c10 1d42 1ce8 1dda 1ece 1e97 1b6f 1bdf 35d4 3e43 3bf6 3d37 3ef1 29b7 18b1 1ab1 1b90 1b14 1b90 1b79 1a5e 1adc 1987 1f16 3614 3ee8 3d5e 3c15 3bd7 3c47 3d67 3d01 2a13 168c 19f8 1a5e 1be0 1c5a 1c00 1bc9 3384 3e92 3c83 3c00 3bc5 3ba7 3b21 3ac6 3b3a 3c2b 3d18 3ee4 3f4f 3ee1 3f12 3f1d 3dc6 3c9a 3c1d 3adf 3a33 3a50 3a49 3ae9 3af7 3d20 1e5f 148d 1654 177a 18c9 1944 18f8 196b 17d5 16c8 1644 15d8 1682 1605 154a 1441 140d
2bf4 177a 1a0d 1a0c 1959 17b4 1750 1872 1dab 31a3 3ca1 3d49 3c08 3c1a 3ca5 3dae 3a0e 26a1 177f 1974 19bf 19df 1a0d 1a07 18e5 169e 1776 1784 2d46 3dde 39fd 39c6 39d4 3d6f 29a9 1763 1a77 1b53 1d43 1d1e 1c84 1c3f 1aa8 1a99 1a00 207e 3bc3 3bed 3b13 3aaa 3ae2 3b5e 3b6f 3c34 3ca8 3df5 3e57 31c5 2300 2112 3d2a 3efc 3cb8 3be7 3c3a 3c50 3c02 3c27 3ca3 3c8c 3cbb 3dcd 3edc 234a 1be1 1cdb 1c05 1d03 1e13 1d96 1d10 1d8c 1d8a 1d00 1a8e 2884 3f71 3f06 3d3e 296e 18ea 1aab 1b5b 1b78 1ba1 1c13 1b3e 1b18 1aa7 1e0a 390d 3e9a 3b61 3aee 3a8f 3a5d 3a7f 3aee 3b91 3e4e 28e2 174d 1a5e 1c0f 1bb6 1b01 22f1 3da9 3d28 3be8 3bb4 3bb6 3bae 3bc2 3b4f 3b89 3d93 3e49 3516 2b95 2790 28b3 2f8c 39da 3f20 3d40 3b62 3a78 3a82 3a32 3a7f 3ba5 3b3d 1a36 15c8 16de 18b9 18d1 18d1 19be 18ef 1719 15ad 16c7 173e 15ef 1568 1574 143f 13c3
217c 17f1 196b 18a0 18a6 1784 171f 1857 1900 1a9b 22f3 2da4 32eb 33e8 309a 27de 1cd6 17ae 1821 19b6 1a57 1948 1938 1927 17b8 15cf 175d 2067 3c20 3a1e 387d 388d 38a4 3a81 3aa8 2041 17f0 1bdf 1c2a 1ca8 1c8d 1b19 1a1d 1917 1ca3 369e 3d8f 3b8c 3abd 3abd 3b58 3bd5 3c48 3cbd 3dc8 3d81 27fd 1aba 1aeb 1c3b 3747 3e24 3c23 3bbe 3b90 3ba8 3b8b 3bab 3c69 3ca9 3c6f 3ec6 37f4 1bb6 1c99 1c43 1c43 1d12 1d8c 1d40 1d76 1d01 1cab 19ea 1ac4 2565 38d1 2fce 2059 198a 1a46 1ac0 1c2e 1bb8 1bf2 1cc3 1bff 1b2f 1abb 3206 3e70 3b74 3ac4 3b1f 3ae8 3ad9 3b53 3b48 3b62 3d33 3bb1 1aa8 17f1 1a01 1979 1d59 3750 3e8a 3c7a 3c12 3bb1 3b97 3be3 3c4e 3c2c 3e46 394d 24ae 19e1 1a1f 1b9d 1c13 1b13 1efe 2f56 3e78 3c50 3b1c 3a4b 3a42 3aa3 3dcb 3306 1591 16d5 16d2 185a 19e0 18d9 189f 1831 164e 15b7 15da 1424 138e 1390 115c 11e0 1308
1e34 17b8 1856 1869 179a 161a 1636 1951 19c8 1a00 1928 1965 1a2f 19cc 1919 188a 189f 1820 1862 1945 18fb 1917 1922 1883 16d4 178e 16c6 2dc4 3c87 38d0 37e6 37b6 3897 3a01 3bef 3ad8 275d 1954 191c 1a61 1a7c 18af 195c 23ac 37a2 3e30 3c72 3be2 3b7d 3b87 3bc7 3c9a 3cd8 3da6 3e35 27b7 1a5b 1d24 1d9f 1ade 29c4 3f3a 3ca5 3bd0 3bbc 3be7 3c1a 3c77 3ccb 3c87 3d73 3f7b 2748 1a2c 1bca 1bd6 1be4 1cf1 1c46 1cc5 1d12 1aea 1bd0 2995 37ce 3bc6 1ff7 19a0 1a60 1a7b 1b5e 1c90 1dca 1d08 1cf6 1da8 1cf0 1bc2 22b3 3d74 3ce5 3ba5 3a9d 3aca 3aeb 3b29 3b5a 3b96 3b97 3c08 3ed8 2723 1527 186f 1f2d 3626 3efc 3cca 3c5c 3c07 3b91 3ba3 3c7c 3cc6 3e1e 3904 1e0f 1921 1a5a 1b8e 1b99 1c14 1bae 1b3b 1b4d 2ded 3e23 3b33 3a67 3a77 3b6f 3de7 2143 166d 183c 184a 1947 19f3 1923 18a4 187e 15e8 1713 23a2 2f7c 3525 34b2 2f2b 20ff 119f
2096 16c5 1902 1828 174d 1609 1724 189f 198f 1a9e 19ab 1a3c 1a2f 19dc 198a 192e 191b 18d1 18cd 1998 1954 1a5e 19b2 17f6 179f 17d1 1863 3491 3a68 3821 37d2 3897 38f2 39cb 3b2f 3c1c 3e08 36cf 2c49 26c4 263f 2bc9 35ab 3df4 3dba 3c5b 3c36 3c48 3c26 3c57 3c82 3d0c 3cf9 3f15 324f 1b2b 1de7 1e83 1d3b 1b90 1cfb 339b 3e7f 3c99 3be1 3c0e 3c92 3ca9 3ce0 3d6c 3f87 30f8 1984 1ba1 1bf0 1be0 1bc3 1c90 1b6d 1b08 1b72 1e07 3557 4011 3eb8 3f23 250a 1a7c 1bd7 1c2a 1cd5 1dc3 1cd8 1d17 1c5d 1ca9 1c91 1ab2 2dc6 3f4d 3cf7 3c0a 3b01 3b46 3b61 3b1c 3bae 3c50 3cbd 3d17 3f03 312d 1f7f 2da3 3b92 3e50 3c6f 3c50 3c0b 3c25 3b96 3b79 3c86 3d9c 3d8a 2287 1925 1b4b 1afc 1a92 1af8 1afe 1a76 19f4 1984 1af9 3771 3ce6 3b14 3bac 3e37 2e64 160f 1823 1809 1900 1969 1826 1802 17a2 1735 1e16 3500 3e93 3d42 3c3d 3cda 3d86 3d7c 308a
input_data/pattern_160_120_16.dat 0 → 100644
View file @ 043d4849
//
// autogenerated from ../input_data/pattern_160_120_16.tiff
// GENERATOR = ./x393_tiff_verilog.py
// WIDTH = 160
// HEIGHT = 120
//
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ca7a cb69 cbc3 cb7b cc21 cc8f cd14 cd4b ce32 cf65 c21f 5f08 3a32 3bbe 3d08 3c65 3aa3 4907 8fb0 cce5 d048 cc7c c975 c7f8 c85b c99f cb39 cdd0 ce7f a78a 4cfb 373c 38b6 3abf 37bf 3697 3582 3839 3801 38a2 4112 7354 af3f cc3b c8e9 6b31 41c7 3cc0 3cb7 3da9 3ff8 3fd5 3e84 3e7a 3d9e 3cf3 3959 363c 5b43 c0ac ccd0 cb0f cb78 cbce cbd4 cb87 cc7c cc0e cbd3 cd99 d11e ab28 45bf 3c38 3de2 3d4c 665b be27 d1ef cefc ce4d ceab d01a d051 d0db d317 d667 d900 bfdc 86ad 5fb0 53c8 527b 573a 6919 925f c6b8 d750 d43b d1d4 cf87 ce1b cd00 cc14 cb27 7c17 3356 3295 35e8 384b 36a0 362c 36f9 353f 35fa 3681 3634 388f 37be 35ea 3449 33a7 370e 38ba 390f 3c90 4028 410a 4183 429f 4820 802e d677 d872 d511 d36d d165 d041 d00b d153 d3e0 d4c7 d4d9 d489 d4b8 d2fe d1c5 d088 ceaf cdfe cd71 cd97 ccb0 cb42 c95d c90c 9f1b 3dbb 2a0d 2dde
c928 ca43 cb4a cbb6 cc9e cd63 cdb0 cd2f cde4 cf87 a73f 435a 3add 3ef7 40b4 3fbb 3ccb 3f90 50b6 92b4 c7dc d258 cef5 cd3c cd5a ce64 d083 cfbb aae1 5bf7 39c4 3a0f 3c40 3dd6 3973 3662 3535 363e 3614 3e95 8071 c657 d424 d3de cfa1 7a9d 3a09 400b 41cb 41d9 42ea 4017 3e87 3d3d 3bc3 3b9b 3b22 3d10 883c cf36 ce6d ceb0 cff4 d01c d00f cf60 cec5 cf4e ceec d10f d586 cd4a 63e3 3e58 488a 7296 b8e6 d3cf d113 cf8c ced9 cfe2 d121 d15d d238 d4a9 d845 b37a 66d5 48c5 479c 47af 4891 49ce 4982 4f76 78b6 c1b9 d65a d170 ce6e ce0f cff4 d169 c639 5f6f 341c 366f 3aa9 3bb0 3c02 3a34 370e 3500 3550 3755 36d1 3676 34e7 338a 32a0 335e 371e 399d 3a63 3dda 40ea 43df 45d0 43c7 44b3 7086 d092 d6f3 d238 cfbc cee6 cf1d ce9c cf8c d248 d3b0 d3b0 d3bb d409 d34c d1fc cff9 cd8d ccc8 cbe4 cbd4 ca6a c80b c674 c791 c432 71ca 2ce0 2d72
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dbaa dca1 cf67 9e53 652b 5d4b 60d2 623c 64bd 6637 63ff 631e a487 e6fb e6b3 e587 e586 e549 e555 e60f e816 e9a5 ea17 ec77 ee47 ee81 eea7 f05c f016 ef8f ee4e ecc3 eacf e8c1 e889 e889 e903 ea5d edd0 cdef 6efb 670a 6518 6586 64b2 649f 675e 6681 634f 6263 60ec 61bf 63f6 6778 6acb 6aca 6b6e 6c38 6d42 6d8f 6d4f 6cc3 6d25 6d7b 7397 a81a ede4 f145 ed2f ec05 eb97 ea6f e9ca e9db eaf7 ec3b ed35 edc5 ee57 ee8c ef7e ee3a ebde ec88 ec93 ec8d ed43 ecf1 ee4c e5c4 a6bf 5fd7 5a8d 5cbf 5887 591a 5cce 5f28 6211 64d1 63fe 620b 5d5e 5cc3 5e31 6006 6242 5ee5 5ba0 616d 7253 9bd1 cb55 e590 efb3 ef5c ec85 eb2b e99c e7e6 e794 e7dc e902 e954 e947 e98a e911 e75b e618 e6c9 e809 e854 e8de eb42 e7a7 9ba8 584f 56f0 5979 5710 53a5 53f9 562b 5a92 5b1d 5be5 5aa8 5aa1 5a53 5a4e 5aeb 58f1 5d6a 5d8b 57fa 5978 5412 4e4c 5629 8b2c
d8eb dbe1 e0f6 e040 b19f 6713 5b89 5c5e 615d 63cd 6018 6e8e c81a e834 e5dd e492 e3d0 e312 e331 e478 e6eb e9d4 eb2d ebaa e30c d361 ca88 cd7d da16 e9ec f07f ede0 ebca e91c e88b e777 e7c9 e957 ecba cab4 6c67 6480 6389 6481 63cb 6217 6311 63a3 61ff 62b0 6114 60a0 61ed 6499 652b 6360 6224 61a1 6456 67a4 69a1 6b5e 6aa6 6b07 6f25 8c5a e37f efad ed05 ebcc ea91 ea2c ea23 eb8e ec1b ecb2 ed60 ee5f eea2 edc7 edc6 ed15 eb94 ebed eb22 ead6 eae6 ea04 eb92 ed5e e2f9 8ee5 5b11 5c09 5af9 594c 5e54 6286 6593 6707 656d 6482 6386 6132 5fb9 6327 6431 618d 5eba 60f8 6492 6ac1 792e 91bd bbc1 e6cb f200 ee72 eb3f ea17 ea15 e8b1 e992 e99b ea12 e9ee e988 e812 e66c e610 e756 e746 e802 e9be ebdd d7fa 858a 598a 547b 5364 5049 51bd 5509 58e6 5921 59f3 5916 5a87 5b96 5aa3 5b46 5b6f 5cda 5baf 56dd 578a 5094 4c32 4f96 6d38
d64d d878 db3a df5e e047 a1e5 5dd3 5e36 61d6 61bf 6611 9e69 e3e0 e7e4 e593 e4d2 e4a9 e50a e5bf e6ab e878 ecee e289 b699 8d06 7993 762f 791a 8275 9deb ccbd ec3f ee37 ea7f e84b e70d e766 e967 ed60 b8d5 693e 6583 68eb 679b 65eb 6349 6312 642d 6644 66bb 64da 6423 6320 654a 6512 62d6 61e8 5f60 630e 69b9 6bdd 6c6b 6b1e 6b70 6e46 826b dcb0 f0d1 ee5b ecd5 eb87 eaca ebaa ede2 edc6 ed07 ee20 eeef ef9f ee7c ecdb ebe4 eb96 eb8e eb0a ea92 eb2d ea6f eb86 ecce ee45 c4ad 690f 5edc 5ce2 596a 5f21 660d 69c5 6a70 693b 68dc 6abe 69c5 6660 6850 68fb 66ac 683d 6ba9 6b24 681a 67d6 6bfb 7863 a3af e48a f2f9 eff8 ef8c ef21 ed1e ec79 eb11 eb14 ea4c e980 e8ce e7f7 e762 e843 e8bc e806 e899 eaa1 ebd8 da27 a26c 6d31 56d1 5086 50cb 53a0 555c 5608 5760 5a3b 5c09 5e02 5e87 5ffd 6091 5d01 5b0f 5874 56e9 51c9 4bdf 4b40 569d
d70a d7fb da61 ddc1 e359 d429 75f9 5e73 5ecd 658d 93b9 d98b e823 e616 e544 e520 e5ba e779 e83b e916 ec4b df05 9c90 7227 6b97 6b39 6d27 6f0e 71e2 70a2 81e0 bd01 eb78 ed43 e7f2 e70a e833 ec93 e795 9402 6803 68e5 6c8d 6b96 682a 6720 6702 66f4 6756 66da 6ef6 8186 9124 95cb 8d05 7abc 684b 631c 6609 6a1e 6f64 7028 6e84 6f2b 70b5 8329 de58 f23d f056 ee9e ecaa ece8 ede0 ee40 ee8e ee6b efb0 f10e f215 f17c eff4 ef1a ee6e ed2f ecd5 edea edab ec6f ed31 ed88 f028 e1e5 7e9c 63fc 5e42 5bf0 6086 66ac 69b4 68d5 6862 6819 692b 6c6b 69a6 677f 66bf 66e2 68a4 6a98 6bd0 6b0b 6c9f 6d53 6f84 7901 ae85 ef7b f527 f30d f133 f04d ee91 ed1d eccf ecf6 ed6d ec11 eb3c eb3a eae5 eb56 e9c4 e9f2 eb07 ec8d ed63 e8c8 d656 b126 754c 5159 5042 537b 55c4 56ce 5a62 5ca3 5e5f 6097 61d5 6277 5d33 5a4f 58c0 5834 53e8 4c29 48ef 4fd6
da4f dbb6 decb e089 e537 e7f2 9993 6252 7266 a5a0 db86 e8e6 e6d2 e663 e5df e5a1 e63c e89b ea99 ecb4 e54b 9d0a 6c5d 69ec 67b4 685a 69c3 6b4e 6b99 6920 6e44 7e44 c77f ec44 e7ea e87b ec88 ef46 c319 71c6 6917 6c24 6f14 6d2f 6aa2 6974 67f6 668d 673b 8a45 c0a8 e0a7 e9d6 ea01 e6c7 d9de b161 78f3 63f3 67a3 6bee 6ee1 6e67 6e9a 6f2e 8c11 e595 f104 eed8 ed1f ec44 ed3f edc1 edf7 f0f8 f27b f35d f38c f42b f420 f396 f35f f1af f086 ef5c ee32 ecee ecf6 ee0a eea0 f1e2 eb50 8b8b 66f8 5f45 5cff 626f 65cf 666c 65db 6474 6365 6402 690f 6603 6313 63e0 667b 67ff 677b 6a6e 6a9b 6d22 6f3a 6d92 6f5a 8560 d664 f6ae f4f6 f208 f043 ee34 eeaf ee28 eef7 ef89 ef39 ef92 ef2e edf6 ed6c ebe7 ead1 eadb ec88 ebbb eb54 ea8c e927 d4b6 8b81 54b8 5495 5456 57e0 5b7f 5bdf 5d8e 6270 64a7 63f4 6137 5e17 5a9a 596c 5524 4dde 48c4 49c2
e024 e126 e333 e5f7 e1c4 d2ca b943 b903 d2d1 e361 e723 e665 e54f e52d e4f8 e53b e5fa e808 eb21 ed57 bd5c 7030 675e 6688 643a 649c 66b6 6906 696e 6a41 6aba 6b39 91af e2cc eb24 ec32 ee91 d005 7fc8 65c2 6a89 6f30 6c99 6b09 69ae 6930 6766 6842 9897 dc57 ebb0 ea59 ea19 e90e ea1e ed91 ecfe ced5 8256 674a 697e 6fa5 7073 6d27 7031 ac56 ee64 f014 ed25 eb3e eb47 ec1b ed72 ef68 f2ce f576 f4e1 eff1 e840 e5a0 e880 efce f39e f36b f1ae ee42 ec0c ebb6 ec41 ed37 f1f6 e9ab 8894 6872 628d 6355 66ed 694b 686b 6647 65da 6472 65bf 675c 6476 624f 62aa 67c7 6b1c 6b4d 6c63 6d8e 6d07 7163 6f39 6cd0 76c5 b57c f47a f5a5 f25f f0be ef04 ef38 ee95 f017 f135 f0ff f194 f18e f0fc ef83 edb3 ebd1 eb74 ec4a ecb9 ea97 e942 e94a ec08 d818 7c77 568a 53ff 5835 5ce6 5d90 5f51 64e8 680a 6620 63eb 5f94 5bf2 5ad8 58d0 5242 4da4 4a71
e400 e66d e3f8 c316 90c2 7668 a4b6 e8b0 e83b e452 e3df e3e8 e39e e4af e52a e49f e568 e6d0 ebca e603 9093 67ca 6707 6914 665d 66b6 66e5 6834 6a3b 6b9e 6962 67d3 73a0 cd4f ee65 e737 c3a7 81ed 64f4 6719 6b91 6eb4 6aef 679c 66b6 67b6 6666 8e7a dddc ec9e e90b e594 e4ab e4b3 e678 ea3d ee83 ef49 cadf 76c7 6bc3 711f 6f91 6cb2 86b8 d94f f2e8 f08f ee0a ec04 ebfc ece1 ef46 f1f5 f38d ee54 ce9a a7b1 9114 8c9f 930a a8f1 cd7c ed62 f465 f172 ef24 ecd0 ebc1 eccb f23f ded2 7dcc 684b 6253 6600 685e 6aa0 68f2 68b1 6842 65b4 6586 6629 65c7 6271 62a3 67cc 694d 6ac0 6d91 6f18 6f42 70b3 713a 6ffc 7342 a1b5 f0d1 f4a4 f10c ef02 ede7 ee04 ee57 f00c f1b2 f1fc f25d f284 f21b f0a6 eead ec27 ec21 eb32 eb8f ea91 e862 e6c2 e9f1 ec2b b7c4 5c00 53c6 579d 5b4f 5b7d 5fb7 6750 6719 638b 6126 5fe3 5d6f 5ca6 59b5 5434 4efc 4c5a
e749 e2f7 a9e4 7168 627e 61e5 873d df63 e95c e43b e331 e408 e347 e306 e442 e42c e526 e790 ed72 cc66 738c 6558 67ca 6b35 67c8 66f2 654d 645c 6506 641c 6519 7016 8a7c b92c b8e9 980b 75b3 67ca 66e8 6748 6cd0 6f89 6c69 6a99 67a0 65bb 72a4 c7a8 efce ec3e e90e e73e e644 e773 e8f0 ea31 ed38 f064 ecd6 a023 68f0 6ad7 6b68 7f3f c669 f0c7 f322 f0c3 ef1d eed6 eec2 ef6d f276 f4c1 e7f7 ab9f 7ea9 73cc 73c8 75da 76d7 7b37 8458 ac1e e662 f41a f158 ee80 ecf9 ef44 f1e8 bfc2 6f92 673d 6609 6937 69c3 67af 67e9 64e2 6487 63e0 64db 6b8f 74d8 75af 6fad 6503 640f 6756 6b34 6d6c 6dfa 6fdb 70dc 7209 72b4 9e45 efe5 f46f f097 ee65 ed89 ecd6 ecc4 eeb4 f196 f27b f2c2 f27e f296 f156 f034 eee0 ed60 eb86 ea83 e9eb e8a1 e749 e8c7 ecf9 d8c5 6d62 53ec 54bf 59a6 5d1c 61bf 67dc 6734 603e 5dc1 5e0b 5cfb 5a20 5779 541e 5084 4ca6
ea60 b2c6 6be5 6249 61ae 5ec3 6d19 b95c e954 e6f1 e3de e4a5 e505 e4e8 e5b1 e682 e700 eb2c e31c 973d 6638 6524 6867 6a93 6730 6315 6241 5ff4 60c0 6d3b 9a43 cd4e e48a c186 7415 6cb3 6cb7 6b70 6acc 6b60 6f20 70e6 6e51 6dc8 6a5d 69a9 92c4 e835 f076 ed29 ec28 eadc ebb1 ed80 ed88 ed05 eef3 f130 f373 c6e1 6c9b 6df4 903a cb6e eead f244 f275 f158 f0d1 f0a5 f17e f371 f606 ecd0 a99f 743d 6f09 7026 7343 76f1 7589 76bc 763d 78a3 ad8d ee60 f359 ef79 eeb9 f29f e363 8dca 6782 691a 690a 6b2a 6bb2 6a0e 6a8c 67c1 67e0 7695 a2ba c99b da21 dc50 d513 b7fc 8788 6715 65f4 68df 6a3b 6eca 71cb 70db 7547 aa6b f0b4 f377 eff2 eef5 ee05 ec98 ebfc edc2 f19d f388 f4cb f3ed f39a f37f f2a0 f0b2 eee9 ed9f ebab e9f9 e8b1 e8d1 e9ad ec0b e40b 7c8c 54c6 55c4 5acd 5fe9 62fe 6597 689f 6236 5d0e 5b65 5acd 589c 5605 5470 51df 4f75
d451 7af3 649f 652d 6488 5ed9 601c 7f39 ca62 ea47 ea57 e7de e73e e846 e8ce eb0c edb6 e5ee a928 6dfc 65fa 6678 687a 69f6 652c 6041 60a4 63ba 755b b94d e5cb ed2e ee3c d909 7d5b 6aed 6d0e 6ce3 6db5 6ffa 707e 6fe2 6f95 6ed6 6e33 757a bc09 f12c efc8 ecc2 ebdd eb68 ecfa ef23 efa2 f101 f39c f34f ea49 ce4f aa0d c432 e5d0 f1c4 f279 f1a6 f200 f176 f1e8 f1a3 f330 f612 f661 c652 7b56 72d9 7025 7107 749e 74c9 76e8 79bc 7856 7024 7eb9 cef6 f442 f233 f371 ea15 a905 6e51 6a2a 6d2c 6c86 6ddf 6d40 6a69 6adf 6bac 89c8 cb51 ed09 f0b7 eef8 ee4d eed3 edef e0cb a7b8 6b21 66c1 69ce 6f0a 70e8 701f 7bc1 c8da f427 f27e eff6 ef16 ee6e ecd3 ebb8 ed60 f151 f49b f618 f3a9 f10d f1e7 f455 f477 f2f7 f061 ebfb e95c e934 e954 eb18 ecc1 e57b 807d 5728 58f9 5e0e 6287 646c 648a 6520 5f99 5b2d 5987 58a1 593f 577d 54fc 5171 5020
a83a 68ea 6690 6714 64a9 5f30 5def 65c6 833f be74 e358 ec00 eb67 ebe8 ec30 ea64 d791 9ee0 6c27 65c4 6700 6732 67d0 6786 62d7 5bfa 5e3a 6aa3 b0fb e8cc e971 e7ba e8d9 e990 a875 6ae6 6909 6dae 730c 739c 71f3 6fed 6b84 6a5a 6d57 9011 e0e2 ef82 ecc0 eb2c ebd7 ed48 ee3f f0c7 f2fb f590 eb47 c28a 982a 9654 e080 f471 f2ea f0a8 f0bd f0df f03a f0a6 f22d f240 f343 f711 ed72 9837 735d 729b 70dc 73b9 7718 75fb 7511 7647 75cf 71bc 720d a90e f0c6 f3a4 e2f6 a887 71c2 6a71 6d29 6e02 6e95 6fd8 6d92 6c1a 6d0c 8687 d44b f1e3 ef3c ecd8 eb25 ea75 eb34 ecea eeb1 e7c8 a4a3 67fc 6842 6e6d 6e38 7168 97f5 e886 f424 f060 ef08 eed4 eed2 eece edbe ef7a f2ae ead7 cd40 b12a a4d3 a8d0 bd6b dc7d f23a f431 ee19 ea69 e9c5 e91a ea9b ee1c dced 7498 5968 5b86 619d 6384 63c8 659a 631f 5c97 581a 5a38 5a95 573c 5537 53b7 504d 4efb
8497 648c 6496 6337 61fc 5deb 5cee 61b6 6755 75d2 92f2 b2b5 c38e c688 bbb5 a147 7f41 6770 6191 6619 67f8 65a1 6527 6426 5ee6 5993 60d6 8a69 df3e e8cb e31d e272 e3d4 e968 dae8 8ecc 6bb9 6da9 6fe1 7196 70cb 6c15 68e5 6b85 8435 ce6b f0c5 eeda ebbb eb81 ed5d ef66 f110 f348 f557 e620 a698 7a1f 7128 7d3f d226 f514 f1b0 ef3b eeb3 eeed eeb8 ef71 f1af f272 f33d f6ab d3a4 7cd0 71ab 7126 7130 7403 7597 7518 7537 7385 7275 70d7 7af5 a262 d1d6 ba52 8d3d 7018 69c4 6c03 704d 6f98 7053 727b 700f 6d71 775d c09e f091 ef99 ebcc ec13 eb8d eb83 eccc ed28 ee63 f29d dc71 79eb 622a 6773 6b88 8629 d1e0 f4b9 f2aa f03f eed8 ee99 efbc f107 f1a0 f25b d712 9bda 770e 7132 737b 7571 7721 89d0 bba2 ec58 f11a ec79 e999 e94e ebdb f018 c10f 64d3 5b40 5c86 61dc 6626 63d3 62d6 6090 5a06 5855 5d08 5d96 5d89 5c3e 5463 4f31 4c34
782f 6200 61ac 615d 5e6c 59ab 5aba 639e 66ab 6867 6997 6e81 72b3 7211 6e6c 691e 6496 6125 61e7 64eb 64c4 64ee 6489 61bb 5cd8 5d48 65a1 b152 e911 e48c e030 dfec e2d2 e841 ec97 db3d a285 7752 6ead 6f96 6f6a 6cfb 7506 9875 d210 f11a f224 efa9 ee1d ee38 ef71 f20b f37a f610 eb48 a616 767f 73e7 7423 739d a9a1 ee75 f336 efe0 ef10 ef96 f06a f1a0 f2d6 f2ff f5f5 edc8 a249 7030 6efb 6f8f 7014 72fb 71aa 7289 7300 6fdd 7e29 a8fc d2d2 db7c 9342 7301 6cd7 6ae1 6dbc 71f5 755d 73cf 737c 7540 72f5 720f 93c9 e720 f35d eed7 eb33 eb75 ebe4 ec88 ed87 ee72 eefc f1c4 ef02 9ea1 630e 6c87 8b89 cd88 f30f f3d9 f17b f01b ee8a eeca f185 f385 f414 d5d7 88fd 6cd2 6a00 6ce9 6e39 6f79 6e2c 6ec5 7b49 b64e ed75 eddf ea4a eab3 ee59 e576 8e2f 5fa5 5fab 6131 6496 666e 6413 623b 60bf 5d59 6bc0 9355 b61f c74e c64e b341 88bc 59ff
7d4b 6067 628d 60b0 5d26 5927 5c73 6274 665c 6964 6717 6864 689a 676d 65fc 6499 641d 631c 635d 65c8 65ae 6844 661b 6090 5e76 5f42 6c79 c675 e690 e1ae dfc3 e1e1 e3d8 e77e ecbc ef68 eb2f ce04 aaf1 97a5 9634 a8c5 ca6a e9c4 f339 f248 f114 f0e3 f074 f103 f1e3 f3bd f4ae f601 c950 7c58 760f 78a2 74cb 6ff6 81ca cdcf f45f f288 efcf f049 f1ed f29a f391 f5f1 f6e4 c57c 7638 6de8 6f79 6f77 6f7f 7198 6e67 6d2c 6f36 7ed6 c639 f1dc f809 ef86 98ea 6e7c 6e55 701b 72d0 75d4 7421 73ff 7222 72da 71be 739c b2ab f391 f451 eff5 ec67 ecd3 ed2e ecc7 ee9b f0da f275 f499 f4bc bf37 86b4 ad9a de9c f353 f2fa f17b f074 f045 ee88 ee71 f211 f5a9 ebd3 9972 6c20 6b9e 6ba0 6af5 6c05 6c2e 6a5f 686b 6871 7e31 d6f9 f02a ecfb eef2 f0b6 bb86 67ed 5f97 608d 6386 64ee 61b9 6070 5ef7 6013 7b26 c2a6 ea93 eef2 ee3c efae ef42 e4c9 ba99
py393/.~lock.boson_commands.ods# 0 → 100644
View file @ 043d4849
,eyesis,eyesis-SH87R,26.12.2020 00:01,file:///home/eyesis/.config/libreoffice/4;
\ No newline at end of file
py393/cargs_test 0 → 100644
View file @ 043d4849
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-i
py393/generate_flir_boson_cs.py 0 → 100755
View file @ 043d4849
#!/usr/bin/env python3
# encoding: utf-8
'''
# Copyright (C) 2020, Elphel.inc.
# test for import_verilog_parameters.py
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2020 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
CRC16_XMODEM_TABLE =[
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0]
def create_with_parity (init_data, # numeric data (may be less than full array
num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
# start_bit, # bit number to start filling from
full_bram): # true if ramb36, false - ramb18
d = num_bits
num_bits8 = 1;
while d > 1:
d >>= 1
num_bits8 <<= 1
bsize = (0x4000,0x8000)[full_bram]
bdata = [0 for i in range(bsize)]
sb = 0
for item in init_data:
for bt in range (num_bits8):
bdata[sb+bt] = (item >> bt) & 1;
sb += num_bits8
data = []
for i in range (len(bdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + bdata[256*i+b]
data.append(d)
data_p = []
num_bits_p = num_bits8 >> 3
sb = 0
print ("num_bits=",num_bits)
print ("num_bits8=",num_bits8)
print ("num_bits_p=",num_bits_p)
if num_bits_p:
pbsize = bsize >> 3
pbdata = [0 for i in range(pbsize)]
for item in init_data:
# print ("item = 0x%x, p = 0x%x"%(item,item >> num_bits8))
for bt in range (num_bits_p):
pbdata[sb+bt] = (item >> (bt+num_bits8)) & 1;
# print ("pbdata[%d] = 0x%x"%(sb+bt, pbdata[sb+bt]))
sb += num_bits_p
for i in range (len(pbdata)//256):
d = 0;
for b in range(255, -1,-1):
d = (d<<1) + pbdata[256*i+b]
data_p.append(d)
# print(bdata)
# print(data)
# print(pbdata)
# print(data_p)
return {'data':data,'data_p':data_p}
def print_params(data,out_file_name):
with open(out_file_name,"w") as out_file:
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v), file=out_file)
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v), file=out_file)
def print_params(data):
print("Paste following to memory parameters in Verilog source file:")
for i, v in enumerate(data['data']):
if v:
print (", .INIT_%02X (256'h%064X)"%(i,v))
for i, v in enumerate(data['data_p']):
if v:
print (", .INITP_%02X (256'h%064X)"%(i,v))
rslt = create_with_parity (CRC16_XMODEM_TABLE, # init_data, # numeric data (may be less than full array
16, # num_bits, # number of bits in item, valid: 1,2,4,8,9,16,18,32,36,64,72
False) #full_bram): # true if ramb36, false - ramb18
print_params(rslt)#,"test.vh")
# from FLIR docs:
def crc16(data, crc=0x1d0f): #Note the new initial condition is 0x1d0f instead of 0.
# in C:return(USHORT)((crcin << 8) ^ ccitt_16Table[((crcin >> 8)^(data))&255]);
for byte in data:
crc = ((crc << 8) & 0xff00) ^ CRC16_XMODEM_TABLE[((crc >> 8) & 0xff) ^ byte]
return crc & 0xffff
py393/import_verilog_parameters.py
View file @ 043d4849
...@@ -517,7 +517,7 @@ class ImportVerilogParameters(object): ...@@ -517,7 +517,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not self.conditions.pop()) self.conditions.append(not self.conditions.pop())
continue continue
elif tokens[0] == "elsif": elif tokens[0] == "elsif":
self.conditions.pop self.conditions.pop()
self.conditions.append((tokens[1] in self.defines) and ( not False in self.conditions)) self.conditions.append((tokens[1] in self.defines) and ( not False in self.conditions))
continue continue
else: # enabled, process all directives else: # enabled, process all directives
...@@ -528,7 +528,7 @@ class ImportVerilogParameters(object): ...@@ -528,7 +528,7 @@ class ImportVerilogParameters(object):
self.conditions.append(not (tokens[1] in self.defines)) self.conditions.append(not (tokens[1] in self.defines))
continue continue
elif tokens[0] == "elsif": elif tokens[0] == "elsif":
self.conditions.pop self.conditions.pop()
self.conditions.append(tokens[1] in self.defines) self.conditions.append(tokens[1] in self.defines)
continue continue
elif tokens[0] == "else": elif tokens[0] == "else":
...@@ -748,4 +748,4 @@ class ImportVerilogParameters(object): ...@@ -748,4 +748,4 @@ class ImportVerilogParameters(object):
return self.parameters return self.parameters
def getDefines(self): def getDefines(self):
return self.defines return self.defines
\ No newline at end of file
py393/test.vh 0 → 100644
View file @ 043d4849
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
py393/test_mcntrl.py
View file @ 043d4849
...@@ -580,7 +580,8 @@ USAGE ...@@ -580,7 +580,8 @@ USAGE
print(" 'defines' command accepts regular expression as a second parameter to filter the list") print(" 'defines' command accepts regular expression as a second parameter to filter the list")
elif (lineList[0] == 'pydev_predefines'): elif (lineList[0] == 'pydev_predefines'):
predefines="" predefines=""
for k,v in ivp.parsToDict(parameters).items(): # for k,v in ivp.parsToDict(parameters).items():
for k,v in list(sorted(ivp.parsToDict(parameters).items(), key=lambda item:item[0])):
typ=str(type(v)) typ=str(type(v))
typ=typ[typ.find("'")+1:typ.rfind("'")] typ=typ[typ.find("'")+1:typ.rfind("'")]
if "None" in typ: if "None" in typ:
...@@ -664,4 +665,4 @@ if __name__ == "__main__": ...@@ -664,4 +665,4 @@ if __name__ == "__main__":
stats.print_stats() stats.print_stats()
statsfile.close() statsfile.close()
sys.exit(0) sys.exit(0)
sys.exit(main()) sys.exit(main())
\ No newline at end of file
py393/vrlg.py
View file @ 043d4849
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/vrlg_mod.py 0 → 100644
View file @ 043d4849
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Module to keep globals (Verilog parameters) accessible for all modules
# that import (not import from) this one
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
DEFAULTS={}
dqs_dqm_patt=None
def init_vars(d):
global DEFAULTS
if d:
globals().update(d)
for k,v in d.items():
DEFAULTS[k]=v
def set_name_field(vname,
fieldIndex,
value):
"""
Set specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
<value> value to set the specified byte to
"""
v=globals()[vname]
mask = 0xff << (8*fieldIndex)
val = value << (8*fieldIndex)
v = ((v ^ val) & mask) ^ v
globals()[vname]=v
def get_name_field(vname,
fieldIndex):
"""
Get specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return ( globals()[vname] >> (8*fieldIndex)) & 0xff
def get_default_field(vname,
fieldIndex):
"""
Get specified byte in the parameter default value (read at program
start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
global DEFAULTS
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
def get_default(vname):
"""
Get parameter default value (read at program start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
Return specified parameter default
"""
global DEFAULTS
return DEFAULTS[vname]
def save_default(vname=None):
"""
Save parameter default value (replace read at program start from Verilog
parameters) using current parameter value
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname and vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
else:
for vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
def restore_default(vname=None):
"""
Restore parameter value from default
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname:
globals()[vname] = DEFAULTS[vname]
else:
for vname in DEFAULTS:
globals()[vname] = DEFAULTS[vname]
#### PyDev predefines
PICKLE = str
PICKLE__TYPE = str
PICKLE__RAW = str
VERBOSE = int
VERBOSE__TYPE = str
VERBOSE__RAW = str
MCONTR_WR_MASK = int
MCONTR_WR_MASK__TYPE = str
MCONTR_WR_MASK__RAW = str
MCONTR_RD_MASK = int
MCONTR_RD_MASK__TYPE = str
MCONTR_RD_MASK__RAW = str
CONTROL_ADDR = int
CONTROL_ADDR__TYPE = str
CONTROL_ADDR__RAW = str
CONTROL_ADDR_MASK = int
CONTROL_ADDR_MASK__TYPE = str
CONTROL_ADDR_MASK__RAW = str
CONTROL_RBACK_ADDR = int
CONTROL_RBACK_ADDR__TYPE = str
CONTROL_RBACK_ADDR__RAW = str
CONTROL_RBACK_ADDR_MASK = int
CONTROL_RBACK_ADDR_MASK__TYPE = str
CONTROL_RBACK_ADDR_MASK__RAW = str
CONTROL_RBACK_DEPTH = int
CONTROL_RBACK_DEPTH__TYPE = str
CONTROL_RBACK_DEPTH__RAW = str
STATUS_ADDR = int
STATUS_ADDR__TYPE = str
STATUS_ADDR__RAW = str
STATUS_ADDR_MASK = int
STATUS_ADDR_MASK__TYPE = str
STATUS_ADDR_MASK__RAW = str
MCONTR_CMD_WR_ADDR = int
MCONTR_CMD_WR_ADDR__TYPE = str
MCONTR_CMD_WR_ADDR__RAW = str
MCONTR_BUF0_RD_ADDR = int
MCONTR_BUF0_RD_ADDR__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
MCONTR_BUF0_WR_ADDR = int
MCONTR_BUF0_WR_ADDR__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str
MCONTR_BUF2_RD_ADDR = int
MCONTR_BUF2_RD_ADDR__TYPE = str
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_BUF2_WR_ADDR = int
MCONTR_BUF2_WR_ADDR__TYPE = str
MCONTR_BUF2_WR_ADDR__RAW = str
MCONTR_BUF3_RD_ADDR = int
MCONTR_BUF3_RD_ADDR__TYPE = str
MCONTR_BUF3_RD_ADDR__RAW = str
MCONTR_BUF3_WR_ADDR = int
MCONTR_BUF3_WR_ADDR__TYPE = str
MCONTR_BUF3_WR_ADDR__RAW = str
MCONTR_BUF4_RD_ADDR = int
MCONTR_BUF4_RD_ADDR__TYPE = str
MCONTR_BUF4_RD_ADDR__RAW = str
MCONTR_BUF4_WR_ADDR = int
MCONTR_BUF4_WR_ADDR__TYPE = str
MCONTR_BUF4_WR_ADDR__RAW = str
AXI_WR_ADDR_BITS = int
AXI_WR_ADDR_BITS__TYPE = str
AXI_WR_ADDR_BITS__RAW = str
AXI_RD_ADDR_BITS = int
AXI_RD_ADDR_BITS__TYPE = str
AXI_RD_ADDR_BITS__RAW = str
STATUS_DEPTH = int
STATUS_DEPTH__TYPE = str
STATUS_DEPTH__RAW = str
DLY_LD = int
DLY_LD__TYPE = str
DLY_LD__RAW = str
DLY_LD_MASK = int
DLY_LD_MASK__TYPE = str
DLY_LD_MASK__RAW = str
MCONTR_PHY_0BIT_ADDR = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
MCONTR_PHY_0BIT_DLY_SET = int
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
MCONTR_PHY_0BIT_CMDA_EN = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
MCONTR_PHY_0BIT_CKE_EN = int
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
MCONTR_PHY_0BIT_DCI_RST__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__RAW = str
MCONTR_TOP_0BIT_ADDR = int
MCONTR_TOP_0BIT_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
MCONTR_TOP_0BIT_ADDR_MASK = int
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
MCONTR_TOP_0BIT_MCONTR_EN = int
MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MCONTR_TOP_0BIT_REFRESH_EN = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
MCONTR_PHY_16BIT_ADDR = int
MCONTR_PHY_16BIT_ADDR__TYPE = str
MCONTR_PHY_16BIT_ADDR__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK = int
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
MCONTR_PHY_16BIT_PATTERNS = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_16BIT_PATTERNS__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
MCONTR_PHY_16BIT_EXTRA = int
MCONTR_PHY_16BIT_EXTRA__TYPE = str
MCONTR_PHY_16BIT_EXTRA__RAW = str
MCONTR_PHY_STATUS_CNTRL = int
MCONTR_PHY_STATUS_CNTRL__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
MCONTR_ARBIT_ADDR = int
MCONTR_ARBIT_ADDR__TYPE = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_ARBIT_ADDR_MASK = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
MCONTR_ARBIT_ADDR_MASK__RAW = str
MCONTR_TOP_16BIT_ADDR = int
MCONTR_TOP_16BIT_ADDR__TYPE = str
MCONTR_TOP_16BIT_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MCONTR_TOP_16BIT_CHN_EN = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL = int
MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
MCONTR_PHY_STATUS_REG_ADDR = int
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
MCONTR_TOP_STATUS_REG_ADDR = int
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
CHNBUF_READ_LATENCY = int
CHNBUF_READ_LATENCY__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
DFLT_DQS_PATTERN = int
DFLT_DQS_PATTERN__TYPE = str
DFLT_DQS_PATTERN__RAW = str
DFLT_DQM_PATTERN = int
DFLT_DQM_PATTERN__TYPE = str
DFLT_DQM_PATTERN__RAW = str
DFLT_DQ_TRI_ON_PATTERN = int
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
DFLT_DQ_TRI_OFF_PATTERN__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
DFLT_DQS_TRI_OFF_PATTERN__RAW = str
DFLT_WBUF_DELAY = int
DFLT_WBUF_DELAY__TYPE = str
DFLT_WBUF_DELAY__RAW = str
DFLT_INV_CLK_DIV = int
DFLT_INV_CLK_DIV__TYPE = str
DFLT_INV_CLK_DIV__RAW = str
DFLT_CHN_EN = int
DFLT_CHN_EN__TYPE = str
DFLT_CHN_EN__RAW = str
DFLT_REFRESH_ADDR = int
DFLT_REFRESH_ADDR__TYPE = str
DFLT_REFRESH_ADDR__RAW = str
DFLT_REFRESH_PERIOD = int
DFLT_REFRESH_PERIOD__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
ADDRESS_NUMBER = int
ADDRESS_NUMBER__TYPE = str
ADDRESS_NUMBER__RAW = str
COLADDR_NUMBER = int
COLADDR_NUMBER__TYPE = str
COLADDR_NUMBER__RAW = str
PHASE_WIDTH = int
PHASE_WIDTH__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ = str
SLEW_DQ__TYPE = str
SLEW_DQ__RAW = str
SLEW_DQS = str
SLEW_DQS__TYPE = str
SLEW_DQS__RAW = str
SLEW_CMDA = str
SLEW_CMDA__TYPE = str
SLEW_CMDA__RAW = str
SLEW_CLK = str
SLEW_CLK__TYPE = str
SLEW_CLK__RAW = str
IBUF_LOW_PWR = str
IBUF_LOW_PWR__TYPE = str
IBUF_LOW_PWR__RAW = str
REFCLK_FREQUENCY = float
REFCLK_FREQUENCY__TYPE = str
REFCLK_FREQUENCY__RAW = str
HIGH_PERFORMANCE_MODE = str
HIGH_PERFORMANCE_MODE__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
CLKIN_PERIOD = int
CLKIN_PERIOD__TYPE = str
CLKIN_PERIOD__RAW = str
CLKFBOUT_MULT = int
CLKFBOUT_MULT__TYPE = str
CLKFBOUT_MULT__RAW = str
DIVCLK_DIVIDE = int
DIVCLK_DIVIDE__TYPE = str
DIVCLK_DIVIDE__RAW = str
CLKFBOUT_USE_FINE_PS = int
CLKFBOUT_USE_FINE_PS__TYPE = str
CLKFBOUT_USE_FINE_PS__RAW = str
CLKFBOUT_PHASE = float
CLKFBOUT_PHASE__TYPE = str
CLKFBOUT_PHASE__RAW = str
SDCLK_PHASE = float
SDCLK_PHASE__TYPE = str
SDCLK_PHASE__RAW = str
CLK_PHASE = float
CLK_PHASE__TYPE = str
CLK_PHASE__RAW = str
CLK_DIV_PHASE = float
CLK_DIV_PHASE__TYPE = str
CLK_DIV_PHASE__RAW = str
MCLK_PHASE = float
MCLK_PHASE__TYPE = str
MCLK_PHASE__RAW = str
REF_JITTER1 = float
REF_JITTER1__TYPE = str
REF_JITTER1__RAW = str
SS_EN = str
SS_EN__TYPE = str
SS_EN__RAW = str
SS_MODE = str
SS_MODE__TYPE = str
SS_MODE__RAW = str
SS_MOD_PERIOD = int
SS_MOD_PERIOD__TYPE = str
SS_MOD_PERIOD__RAW = str
CMD_PAUSE_BITS = int
CMD_PAUSE_BITS__TYPE = str
CMD_PAUSE_BITS__RAW = str
CMD_DONE_BIT = int
CMD_DONE_BIT__TYPE = str
CMD_DONE_BIT__RAW = str
NUM_CYCLES_LOW_BIT = int
NUM_CYCLES_LOW_BIT__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
NUM_CYCLES_00 = int
NUM_CYCLES_00__TYPE = str
NUM_CYCLES_00__RAW = str
NUM_CYCLES_01 = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_01__RAW = str
NUM_CYCLES_02 = int
NUM_CYCLES_02__TYPE = str
NUM_CYCLES_02__RAW = str
NUM_CYCLES_03 = int
NUM_CYCLES_03__TYPE = str
NUM_CYCLES_03__RAW = str
NUM_CYCLES_04 = int
NUM_CYCLES_04__TYPE = str
NUM_CYCLES_04__RAW = str
NUM_CYCLES_05 = int
NUM_CYCLES_05__TYPE = str
NUM_CYCLES_05__RAW = str
NUM_CYCLES_06 = int
NUM_CYCLES_06__TYPE = str
NUM_CYCLES_06__RAW = str
NUM_CYCLES_07 = int
NUM_CYCLES_07__TYPE = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_08 = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_08__RAW = str
NUM_CYCLES_09 = int
NUM_CYCLES_09__TYPE = str
NUM_CYCLES_09__RAW = str
NUM_CYCLES_10 = int
NUM_CYCLES_10__TYPE = str
NUM_CYCLES_10__RAW = str
NUM_CYCLES_11 = int
NUM_CYCLES_11__TYPE = str
NUM_CYCLES_11__RAW = str
NUM_CYCLES_12 = int
NUM_CYCLES_12__TYPE = str
NUM_CYCLES_12__RAW = str
NUM_CYCLES_13 = int
NUM_CYCLES_13__TYPE = str
NUM_CYCLES_13__RAW = str
NUM_CYCLES_14 = int
NUM_CYCLES_14__TYPE = str
NUM_CYCLES_14__RAW = str
NUM_CYCLES_15 = int
NUM_CYCLES_15__TYPE = str
NUM_CYCLES_15__RAW = str
NUM_CYCLES_16 = int
NUM_CYCLES_16__TYPE = str
NUM_CYCLES_16__RAW = str
NUM_CYCLES_17 = int
NUM_CYCLES_17__TYPE = str
NUM_CYCLES_17__RAW = str
NUM_CYCLES_18 = int
NUM_CYCLES_18__TYPE = str
NUM_CYCLES_18__RAW = str
NUM_CYCLES_19 = int
NUM_CYCLES_19__TYPE = str
NUM_CYCLES_19__RAW = str
NUM_CYCLES_20 = int
NUM_CYCLES_20__TYPE = str
NUM_CYCLES_20__RAW = str
NUM_CYCLES_21 = int
NUM_CYCLES_21__TYPE = str
NUM_CYCLES_21__RAW = str
NUM_CYCLES_22 = int
NUM_CYCLES_22__TYPE = str
NUM_CYCLES_22__RAW = str
NUM_CYCLES_23 = int
NUM_CYCLES_23__TYPE = str
NUM_CYCLES_23__RAW = str
NUM_CYCLES_24 = int
NUM_CYCLES_24__TYPE = str
NUM_CYCLES_24__RAW = str
NUM_CYCLES_25 = int
NUM_CYCLES_25__TYPE = str
NUM_CYCLES_25__RAW = str
NUM_CYCLES_26 = int
NUM_CYCLES_26__TYPE = str
NUM_CYCLES_26__RAW = str
NUM_CYCLES_27 = int
NUM_CYCLES_27__TYPE = str
NUM_CYCLES_27__RAW = str
NUM_CYCLES_28 = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_28__RAW = str
NUM_CYCLES_29 = int
NUM_CYCLES_29__TYPE = str
NUM_CYCLES_29__RAW = str
NUM_CYCLES_30 = int
NUM_CYCLES_30__TYPE = str
NUM_CYCLES_30__RAW = str
NUM_CYCLES_31 = int
NUM_CYCLES_31__TYPE = str
NUM_CYCLES_31__RAW = str
MCNTRL_PS_ADDR = int
MCNTRL_PS_ADDR__TYPE = str
MCNTRL_PS_ADDR__RAW = str
MCNTRL_PS_MASK = int
MCNTRL_PS_MASK__TYPE = str
MCNTRL_PS_MASK__RAW = str
MCNTRL_PS_STATUS_REG_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
MCNTRL_PS_EN_RST = int
MCNTRL_PS_EN_RST__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
MCNTRL_PS_CMD = int
MCNTRL_PS_CMD__TYPE = str
MCNTRL_PS_CMD__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
NUM_XFER_BITS = int
NUM_XFER_BITS__TYPE = str
NUM_XFER_BITS__RAW = str
FRAME_WIDTH_BITS = int
FRAME_WIDTH_BITS__TYPE = str
FRAME_WIDTH_BITS__RAW = str
FRAME_HEIGHT_BITS = int
FRAME_HEIGHT_BITS__TYPE = str
FRAME_HEIGHT_BITS__RAW = str
LAST_FRAME_BITS = int
LAST_FRAME_BITS__TYPE = str
LAST_FRAME_BITS__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR = int
MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MCNTRL_SCANLINE_CHN3_ADDR = int
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
MCNTRL_SCANLINE_MASK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCNTRL_SCANLINE_MASK__RAW = str
MCNTRL_SCANLINE_MODE = int
MCNTRL_SCANLINE_MODE__TYPE = str
MCNTRL_SCANLINE_MODE__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL = int
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
MCNTRL_SCANLINE_STARTADDR = int
MCNTRL_SCANLINE_STARTADDR__TYPE = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
MCNTRL_SCANLINE_FRAME_SIZE = int
MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
MCNTRL_SCANLINE_WINDOW_WH = int
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
MAX_TILE_WIDTH = int
MAX_TILE_WIDTH__TYPE = str
MAX_TILE_WIDTH__RAW = str
MAX_TILE_HEIGHT = int
MAX_TILE_HEIGHT__TYPE = str
MAX_TILE_HEIGHT__RAW = str
MCNTRL_TILED_CHN2_ADDR = int
MCNTRL_TILED_CHN2_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
MCNTRL_TILED_CHN4_ADDR = int
MCNTRL_TILED_CHN4_ADDR__TYPE = str
MCNTRL_TILED_CHN4_ADDR__RAW = str
MCNTRL_TILED_MASK = int
MCNTRL_TILED_MASK__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_MODE__TYPE = str
MCNTRL_TILED_MODE__RAW = str
MCNTRL_TILED_STATUS_CNTRL = int
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
MCNTRL_TILED_STATUS_CNTRL__RAW = str
MCNTRL_TILED_STARTADDR = int
MCNTRL_TILED_STARTADDR__TYPE = str
MCNTRL_TILED_STARTADDR__RAW = str
MCNTRL_TILED_FRAME_SIZE = int
MCNTRL_TILED_FRAME_SIZE__TYPE = str
MCNTRL_TILED_FRAME_SIZE__RAW = str
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TILED_FRAME_LAST__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
MCNTRL_TILED_WINDOW_WH = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
MCNTRL_TILED_WINDOW_X0Y0 = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
MCNTRL_TILED_WINDOW_STARTXY = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
MCNTRL_TILED_TILE_WHS = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MCNTRL_TILED_TILE_WHS__RAW = str
MCNTRL_SCANLINE_START_DELAY = int
MCNTRL_SCANLINE_START_DELAY__TYPE = str
MCNTRL_SCANLINE_START_DELAY__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
BUFFER_DEPTH32 = int
BUFFER_DEPTH32__TYPE = str
BUFFER_DEPTH32__RAW = str
MCONTR_LINTILE_NRESET = int
MCONTR_LINTILE_NRESET__TYPE = str
MCONTR_LINTILE_NRESET__RAW = str
MCONTR_LINTILE_EN = int
MCONTR_LINTILE_EN__TYPE = str
MCONTR_LINTILE_EN__RAW = str
MCONTR_LINTILE_WRITE = int
MCONTR_LINTILE_WRITE__TYPE = str
MCONTR_LINTILE_WRITE__RAW = str
MCONTR_LINTILE_EXTRAPG = int
MCONTR_LINTILE_EXTRAPG__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
MCONTR_LINTILE_BYTE32 = int
MCONTR_LINTILE_BYTE32__TYPE = str
MCONTR_LINTILE_BYTE32__RAW = str
MCONTR_LINTILE_LINEAR = int
MCONTR_LINTILE_LINEAR__TYPE = str
MCONTR_LINTILE_LINEAR__RAW = str
MCONTR_LINTILE_RST_FRAME = int
MCONTR_LINTILE_RST_FRAME__TYPE = str
MCONTR_LINTILE_RST_FRAME__RAW = str
MCONTR_LINTILE_SINGLE = int
MCONTR_LINTILE_SINGLE__TYPE = str
MCONTR_LINTILE_SINGLE__RAW = str
MCONTR_LINTILE_REPEAT = int
MCONTR_LINTILE_REPEAT__TYPE = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_LINTILE_DIS_NEED = int
MCONTR_LINTILE_DIS_NEED__TYPE = str
MCONTR_LINTILE_DIS_NEED__RAW = str
MCONTR_LINTILE_SKIP_LATE = int
MCONTR_LINTILE_SKIP_LATE__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
MCONTR_LINTILE_COPY_FRAME__RAW = str
MCONTR_LINTILE_ABORT_LATE = int
MCONTR_LINTILE_ABORT_LATE__TYPE = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
MCNTRL_SCANLINE_DLY_WIDTH = int
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCNTRL_SCANLINE_DLY_WIDTH__RAW = str
MCNTRL_SCANLINE_DLY_DEFAULT = int
MCNTRL_SCANLINE_DLY_DEFAULT__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT__RAW = str
MCNTRL_TEST01_ADDR = int
MCNTRL_TEST01_ADDR__TYPE = str
MCNTRL_TEST01_ADDR__RAW = str
MCNTRL_TEST01_MASK = int
MCNTRL_TEST01_MASK__TYPE = str
MCNTRL_TEST01_MASK__RAW = str
MCNTRL_TEST01_CHN1_MODE = int
MCNTRL_TEST01_CHN1_MODE__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MCNTRL_TEST01_CHN2_MODE__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN3_MODE = int
MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_CHN4_MODE = int
MCNTRL_TEST01_CHN4_MODE__TYPE = str
MCNTRL_TEST01_CHN4_MODE__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_SENS_BASE = int
MCONTR_SENS_BASE__TYPE = str
MCONTR_SENS_BASE__RAW = str
MCONTR_SENS_INC = int
MCONTR_SENS_INC__TYPE = str
MCONTR_SENS_INC__RAW = str
MCONTR_CMPRS_BASE = int
MCONTR_CMPRS_BASE__TYPE = str
MCONTR_CMPRS_BASE__RAW = str
MCONTR_CMPRS_INC = int
MCONTR_CMPRS_INC__TYPE = str
MCONTR_CMPRS_INC__RAW = str
MCONTR_SENS_STATUS_BASE = int
MCONTR_SENS_STATUS_BASE__TYPE = str
MCONTR_SENS_STATUS_BASE__RAW = str
MCONTR_SENS_STATUS_INC = int
MCONTR_SENS_STATUS_INC__TYPE = str
MCONTR_SENS_STATUS_INC__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_CMPRS_STATUS_INC__TYPE = str
MCONTR_CMPRS_STATUS_INC__RAW = str
MEMBRIDGE_ADDR = int
MEMBRIDGE_ADDR__TYPE = str
MEMBRIDGE_ADDR__RAW = str
MEMBRIDGE_MASK = int
MEMBRIDGE_MASK__TYPE = str
MEMBRIDGE_MASK__RAW = str
MEMBRIDGE_CTRL = int
MEMBRIDGE_CTRL__TYPE = str
MEMBRIDGE_CTRL__RAW = str
MEMBRIDGE_STATUS_CNTRL = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
MEMBRIDGE_STATUS_CNTRL__RAW = str
MEMBRIDGE_LO_ADDR64 = int
MEMBRIDGE_LO_ADDR64__TYPE = str
MEMBRIDGE_LO_ADDR64__RAW = str
MEMBRIDGE_SIZE64 = int
MEMBRIDGE_SIZE64__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
MEMBRIDGE_START64 = int
MEMBRIDGE_START64__TYPE = str
MEMBRIDGE_START64__RAW = str
MEMBRIDGE_LEN64 = int
MEMBRIDGE_LEN64__TYPE = str
MEMBRIDGE_LEN64__RAW = str
MEMBRIDGE_WIDTH64 = int
MEMBRIDGE_WIDTH64__TYPE = str
MEMBRIDGE_WIDTH64__RAW = str
MEMBRIDGE_CTRL_IRQ = int
MEMBRIDGE_CTRL_IRQ__TYPE = str
MEMBRIDGE_CTRL_IRQ__RAW = str
MEMBRIDGE_STATUS_REG = int
MEMBRIDGE_STATUS_REG__TYPE = str
MEMBRIDGE_STATUS_REG__RAW = str
RSEL = int
RSEL__TYPE = str
RSEL__RAW = str
WSEL = int
WSEL__TYPE = str
WSEL__RAW = str
SENSOR_GROUP_ADDR = int
SENSOR_GROUP_ADDR__TYPE = str
SENSOR_GROUP_ADDR__RAW = str
SENSOR_BASE_INC = int
SENSOR_BASE_INC__TYPE = str
SENSOR_BASE_INC__RAW = str
HIST_SAXI_ADDR_REL = int
HIST_SAXI_ADDR_REL__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
HIST_SAXI_MODE_ADDR_REL = int
HIST_SAXI_MODE_ADDR_REL__TYPE = str
HIST_SAXI_MODE_ADDR_REL__RAW = str
SENSI2C_STATUS_REG_BASE = int
SENSI2C_STATUS_REG_BASE__TYPE = str
SENSI2C_STATUS_REG_BASE__RAW = str
SENSI2C_STATUS_REG_INC = int
SENSI2C_STATUS_REG_INC__TYPE = str
SENSI2C_STATUS_REG_INC__RAW = str
SENSI2C_STATUS_REG_REL = int
SENSI2C_STATUS_REG_REL__TYPE = str
SENSI2C_STATUS_REG_REL__RAW = str
SENSIO_STATUS_REG_REL = int
SENSIO_STATUS_REG_REL__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
SENSOR_TIMING_STATUS_REG_BASE = int
SENSOR_TIMING_STATUS_REG_BASE__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
SENSOR_TIMING_STATUS_REG_INC = int
SENSOR_TIMING_STATUS_REG_INC__TYPE = str
SENSOR_TIMING_STATUS_REG_INC__RAW = str
SENSOR_TIMING_BITS = int
SENSOR_TIMING_BITS__TYPE = str
SENSOR_TIMING_BITS__RAW = str
SENSOR_TIMING_START = int
SENSOR_TIMING_START__TYPE = str
SENSOR_TIMING_START__RAW = str
SENSOR_TIMING_LANE = int
SENSOR_TIMING_LANE__TYPE = str
SENSOR_TIMING_LANE__RAW = str
SENSOR_TIMING_FROM = int
SENSOR_TIMING_FROM__TYPE = str
SENSOR_TIMING_FROM__RAW = str
SENSOR_TIMING_TO = int
SENSOR_TIMING_TO__TYPE = str
SENSOR_TIMING_TO__RAW = str
SENSOR_NUM_HISTOGRAM = int
SENSOR_NUM_HISTOGRAM__TYPE = str
SENSOR_NUM_HISTOGRAM__RAW = str
HISTOGRAM_RAM_MODE = str
HISTOGRAM_RAM_MODE__TYPE = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_NUM_SUBCHN = int
SENS_NUM_SUBCHN__TYPE = str
SENS_NUM_SUBCHN__RAW = str
SENS_GAMMA_BUFFER = int
SENS_GAMMA_BUFFER__TYPE = str
SENS_GAMMA_BUFFER__RAW = str
SENSOR_CTRL_RADDR = int
SENSOR_CTRL_RADDR__TYPE = str
SENSOR_CTRL_RADDR__RAW = str
SENSOR_CTRL_ADDR_MASK = int
SENSOR_CTRL_ADDR_MASK__TYPE = str
SENSOR_CTRL_ADDR_MASK__RAW = str
SENSOR_HIST_EN_BITS = int
SENSOR_HIST_EN_BITS__TYPE = str
SENSOR_HIST_EN_BITS__RAW = str
SENSOR_HIST_NRST_BITS = int
SENSOR_HIST_NRST_BITS__TYPE = str
SENSOR_HIST_NRST_BITS__RAW = str
SENSOR_HIST_BITS_SET = int
SENSOR_HIST_BITS_SET__TYPE = str
SENSOR_HIST_BITS_SET__RAW = str
SENSOR_CHN_EN_BIT = int
SENSOR_CHN_EN_BIT__TYPE = str
SENSOR_CHN_EN_BIT__RAW = str
SENSOR_CHN_EN_BIT_SET = int
SENSOR_CHN_EN_BIT_SET__TYPE = str
SENSOR_CHN_EN_BIT_SET__RAW = str
SENSOR_16BIT_BIT = int
SENSOR_16BIT_BIT__TYPE = str
SENSOR_16BIT_BIT__RAW = str
SENSOR_16BIT_BIT_SET = int
SENSOR_16BIT_BIT_SET__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
SENSI2C_CTRL_RADDR = int
SENSI2C_CTRL_RADDR__TYPE = str
SENSI2C_CTRL_RADDR__RAW = str
SENSI2C_CTRL_MASK = int
SENSI2C_CTRL_MASK__TYPE = str
SENSI2C_CTRL_MASK__RAW = str
SENSI2C_CTRL = int
SENSI2C_CTRL__TYPE = str
SENSI2C_CTRL__RAW = str
SENSI2C_CMD_TABLE = int
SENSI2C_CMD_TABLE__TYPE = str
SENSI2C_CMD_TABLE__RAW = str
SENSI2C_CMD_TAND = int
SENSI2C_CMD_TAND__TYPE = str
SENSI2C_CMD_TAND__RAW = str
SENSI2C_CMD_RESET = int
SENSI2C_CMD_RESET__TYPE = str
SENSI2C_CMD_RESET__RAW = str
SENSI2C_CMD_RUN = int
SENSI2C_CMD_RUN__TYPE = str
SENSI2C_CMD_RUN__RAW = str
SENSI2C_CMD_RUN_PBITS = int
SENSI2C_CMD_RUN_PBITS__TYPE = str
SENSI2C_CMD_RUN_PBITS__RAW = str
SENSI2C_CMD_USE_EOF = int
SENSI2C_CMD_USE_EOF__TYPE = str
SENSI2C_CMD_USE_EOF__RAW = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENSI2C_CMD_SOFT_SDA__RAW = str
SENSI2C_CMD_SOFT_SCL = int
SENSI2C_CMD_SOFT_SCL__TYPE = str
SENSI2C_CMD_SOFT_SCL__RAW = str
SENSI2C_CMD_FIFO_RD = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENSI2C_CMD_FIFO_RD__RAW = str
SENSI2C_CMD_ACIVE = int
SENSI2C_CMD_ACIVE__TYPE = str
SENSI2C_CMD_ACIVE__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
SENSI2C_CMD_ACIVE_SDA = int
SENSI2C_CMD_ACIVE_SDA__TYPE = str
SENSI2C_CMD_ACIVE_SDA__RAW = str
SENSI2C_TBL_RAH = int
SENSI2C_TBL_RAH__TYPE = str
SENSI2C_TBL_RAH__RAW = str
SENSI2C_TBL_RAH_BITS = int
SENSI2C_TBL_RAH_BITS__TYPE = str
SENSI2C_TBL_RAH_BITS__RAW = str
SENSI2C_TBL_RNWREG = int
SENSI2C_TBL_RNWREG__TYPE = str
SENSI2C_TBL_RNWREG__RAW = str
SENSI2C_TBL_SA = int
SENSI2C_TBL_SA__TYPE = str
SENSI2C_TBL_SA__RAW = str
SENSI2C_TBL_SA_BITS = int
SENSI2C_TBL_SA_BITS__TYPE = str
SENSI2C_TBL_SA_BITS__RAW = str
SENSI2C_TBL_NBWR = int
SENSI2C_TBL_NBWR__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
SENSI2C_TBL_NBWR_BITS = int
SENSI2C_TBL_NBWR_BITS__TYPE = str
SENSI2C_TBL_NBWR_BITS__RAW = str
SENSI2C_TBL_NBRD = int
SENSI2C_TBL_NBRD__TYPE = str
SENSI2C_TBL_NBRD__RAW = str
SENSI2C_TBL_NBRD_BITS = int
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENSI2C_TBL_NBRD_BITS__RAW = str
SENSI2C_TBL_NABRD = int
SENSI2C_TBL_NABRD__TYPE = str
SENSI2C_TBL_NABRD__RAW = str
SENSI2C_TBL_DLY = int
SENSI2C_TBL_DLY__TYPE = str
SENSI2C_TBL_DLY__RAW = str
SENSI2C_TBL_DLY_BITS = int
SENSI2C_TBL_DLY_BITS__TYPE = str
SENSI2C_TBL_DLY_BITS__RAW = str
SENSI2C_STATUS = int
SENSI2C_STATUS__TYPE = str
SENSI2C_STATUS__RAW = str
SENS_SYNC_RADDR = int
SENS_SYNC_RADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_SYNC_MASK = int
SENS_SYNC_MASK__TYPE = str
SENS_SYNC_MASK__RAW = str
SENS_SYNC_MULT = int
SENS_SYNC_MULT__TYPE = str
SENS_SYNC_MULT__RAW = str
SENS_SYNC_LATE = int
SENS_SYNC_LATE__TYPE = str
SENS_SYNC_LATE__RAW = str
SENS_GAMMA_RADDR = int
SENS_GAMMA_RADDR__TYPE = str
SENS_GAMMA_RADDR__RAW = str
SENS_GAMMA_ADDR_MASK = int
SENS_GAMMA_ADDR_MASK__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str
SENS_GAMMA_CTRL = int
SENS_GAMMA_CTRL__TYPE = str
SENS_GAMMA_CTRL__RAW = str
SENS_GAMMA_ADDR_DATA = int
SENS_GAMMA_ADDR_DATA__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
SENS_GAMMA_HEIGHT01 = int
SENS_GAMMA_HEIGHT01__TYPE = str
SENS_GAMMA_HEIGHT01__RAW = str
SENS_GAMMA_HEIGHT2 = int
SENS_GAMMA_HEIGHT2__TYPE = str
SENS_GAMMA_HEIGHT2__RAW = str
SENS_GAMMA_MODE_BAYER = int
SENS_GAMMA_MODE_BAYER__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
SENS_GAMMA_MODE_BAYER_SET = int
SENS_GAMMA_MODE_BAYER_SET__TYPE = str
SENS_GAMMA_MODE_BAYER_SET__RAW = str
SENS_GAMMA_MODE_PAGE = int
SENS_GAMMA_MODE_PAGE__TYPE = str
SENS_GAMMA_MODE_PAGE__RAW = str
SENS_GAMMA_MODE_PAGE_SET = int
SENS_GAMMA_MODE_PAGE_SET__TYPE = str
SENS_GAMMA_MODE_PAGE_SET__RAW = str
SENS_GAMMA_MODE_EN = int
SENS_GAMMA_MODE_EN__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENS_GAMMA_MODE_EN_SET = int
SENS_GAMMA_MODE_EN_SET__TYPE = str
SENS_GAMMA_MODE_EN_SET__RAW = str
SENS_GAMMA_MODE_REPET = int
SENS_GAMMA_MODE_REPET__TYPE = str
SENS_GAMMA_MODE_REPET__RAW = str
SENS_GAMMA_MODE_REPET_SET = int
SENS_GAMMA_MODE_REPET_SET__TYPE = str
SENS_GAMMA_MODE_REPET_SET__RAW = str
SENS_GAMMA_MODE_TRIG = int
SENS_GAMMA_MODE_TRIG__TYPE = str
SENS_GAMMA_MODE_TRIG__RAW = str
SENS_LENS_RADDR = int
SENS_LENS_RADDR__TYPE = str
SENS_LENS_RADDR__RAW = str
SENS_LENS_ADDR_MASK = int
SENS_LENS_ADDR_MASK__TYPE = str
SENS_LENS_ADDR_MASK__RAW = str
SENS_LENS_COEFF = int
SENS_LENS_COEFF__TYPE = str
SENS_LENS_COEFF__RAW = str
SENS_LENS_AX = int
SENS_LENS_AX__TYPE = str
SENS_LENS_AX__RAW = str
SENS_LENS_AX_MASK = int
SENS_LENS_AX_MASK__TYPE = str
SENS_LENS_AX_MASK__RAW = str
SENS_LENS_AY = int
SENS_LENS_AY__TYPE = str
SENS_LENS_AY__RAW = str
SENS_LENS_AY_MASK = int
SENS_LENS_AY_MASK__TYPE = str
SENS_LENS_AY_MASK__RAW = str
SENS_LENS_C = int
SENS_LENS_C__TYPE = str
SENS_LENS_C__RAW = str
SENS_LENS_C_MASK = int
SENS_LENS_C_MASK__TYPE = str
SENS_LENS_C_MASK__RAW = str
SENS_LENS_BX = int
SENS_LENS_BX__TYPE = str
SENS_LENS_BX__RAW = str
SENS_LENS_BX_MASK = int
SENS_LENS_BX_MASK__TYPE = str
SENS_LENS_BX_MASK__RAW = str
SENS_LENS_BY = int
SENS_LENS_BY__TYPE = str
SENS_LENS_BY__RAW = str
SENS_LENS_BY_MASK = int
SENS_LENS_BY_MASK__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_LENS_SCALES = int
SENS_LENS_SCALES__TYPE = str
SENS_LENS_SCALES__RAW = str
SENS_LENS_SCALES_MASK = int
SENS_LENS_SCALES_MASK__TYPE = str
SENS_LENS_SCALES_MASK__RAW = str
SENS_LENS_FAT0_IN = int
SENS_LENS_FAT0_IN__TYPE = str
SENS_LENS_FAT0_IN__RAW = str
SENS_LENS_FAT0_IN_MASK = int
SENS_LENS_FAT0_IN_MASK__TYPE = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_FAT0_OUT = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_LENS_FAT0_OUT__RAW = str
SENS_LENS_FAT0_OUT_MASK = int
SENS_LENS_FAT0_OUT_MASK__TYPE = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENS_LENS_POST_SCALE = int
SENS_LENS_POST_SCALE__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
SENS_LENS_POST_SCALE_MASK = int
SENS_LENS_POST_SCALE_MASK__TYPE = str
SENS_LENS_POST_SCALE_MASK__RAW = str
SENSIO_RADDR = int
SENSIO_RADDR__TYPE = str
SENSIO_RADDR__RAW = str
SENSIO_ADDR_MASK = int
SENSIO_ADDR_MASK__TYPE = str
SENSIO_ADDR_MASK__RAW = str
SENSIO_CTRL = int
SENSIO_CTRL__TYPE = str
SENSIO_CTRL__RAW = str
SENS_CTRL_MRST = int
SENS_CTRL_MRST__TYPE = str
SENS_CTRL_MRST__RAW = str
SENS_CTRL_ARST = int
SENS_CTRL_ARST__TYPE = str
SENS_CTRL_ARST__RAW = str
SENS_CTRL_ARO = int
SENS_CTRL_ARO__TYPE = str
SENS_CTRL_ARO__RAW = str
SENS_CTRL_RST_MMCM = int
SENS_CTRL_RST_MMCM__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
SENS_CTRL_IGNORE_EMBED = int
SENS_CTRL_IGNORE_EMBED__TYPE = str
SENS_CTRL_IGNORE_EMBED__RAW = str
SENS_CTRL_EXT_CLK = int
SENS_CTRL_EXT_CLK__TYPE = str
SENS_CTRL_EXT_CLK__RAW = str
SENS_CTRL_LD_DLY = int
SENS_CTRL_LD_DLY__TYPE = str
SENS_CTRL_LD_DLY__RAW = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP0__TYPE = str
SENS_CTRL_GP0__RAW = str
SENS_CTRL_GP1 = int
SENS_CTRL_GP1__TYPE = str
SENS_CTRL_GP1__RAW = str
SENS_CTRL_GP2 = int
SENS_CTRL_GP2__TYPE = str
SENS_CTRL_GP2__RAW = str
SENS_CTRL_GP3 = int
SENS_CTRL_GP3__TYPE = str
SENS_CTRL_GP3__RAW = str
SENS_UART_EXTIF_EN = int
SENS_UART_EXTIF_EN__TYPE = str
SENS_UART_EXTIF_EN__RAW = str
SENS_UART_XMIT_RST = int
SENS_UART_XMIT_RST__TYPE = str
SENS_UART_XMIT_RST__RAW = str
SENS_UART_RECV_RST = int
SENS_UART_RECV_RST__TYPE = str
SENS_UART_RECV_RST__RAW = str
SENS_UART_XMIT_START = int
SENS_UART_XMIT_START__TYPE = str
SENS_UART_XMIT_START__RAW = str
SENS_UART_RECV_NEXT = int
SENS_UART_RECV_NEXT__TYPE = str
SENS_UART_RECV_NEXT__RAW = str
SENS_CTRL_QUADRANTS = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_CTRL_QUADRANTS__RAW = str
SENS_CTRL_QUADRANTS_WIDTH = int
SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
SENS_CTRL_ODD = int
SENS_CTRL_ODD__TYPE = str
SENS_CTRL_ODD__RAW = str
SENS_CTRL_QUADRANTS_EN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
SENSIO_STATUS = int
SENSIO_STATUS__TYPE = str
SENSIO_STATUS__RAW = str
SENSIO_JTAG = int
SENSIO_JTAG__TYPE = str
SENSIO_JTAG__RAW = str
SENS_JTAG_PGMEN = int
SENS_JTAG_PGMEN__TYPE = str
SENS_JTAG_PGMEN__RAW = str
SENS_JTAG_PROG = int
SENS_JTAG_PROG__TYPE = str
SENS_JTAG_PROG__RAW = str
SENS_JTAG_TCK = int
SENS_JTAG_TCK__TYPE = str
SENS_JTAG_TCK__RAW = str
SENS_JTAG_TMS = int
SENS_JTAG_TMS__TYPE = str
SENS_JTAG_TMS__RAW = str
SENS_JTAG_TDI = int
SENS_JTAG_TDI__TYPE = str
SENS_JTAG_TDI__RAW = str
SENSIO_WIDTH = int
SENSIO_WIDTH__TYPE = str
SENSIO_WIDTH__RAW = str
SENSIO_DELAYS = int
SENSIO_DELAYS__TYPE = str
SENSIO_DELAYS__RAW = str
SENSI2C_ABS_RADDR = int
SENSI2C_ABS_RADDR__TYPE = str
SENSI2C_ABS_RADDR__RAW = str
SENSI2C_REL_RADDR = int
SENSI2C_REL_RADDR__TYPE = str
SENSI2C_REL_RADDR__RAW = str
SENSI2C_ADDR_MASK = int
SENSI2C_ADDR_MASK__TYPE = str
SENSI2C_ADDR_MASK__RAW = str
HISTOGRAM_RADDR_INC = int
HISTOGRAM_RADDR_INC__TYPE = str
HISTOGRAM_RADDR_INC__RAW = str
HISTOGRAM_RADDR0 = int
HISTOGRAM_RADDR0__TYPE = str
HISTOGRAM_RADDR0__RAW = str
HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR1__TYPE = str
HISTOGRAM_RADDR1__RAW = str
HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR2__TYPE = str
HISTOGRAM_RADDR2__RAW = str
HISTOGRAM_RADDR3 = int
HISTOGRAM_RADDR3__TYPE = str
HISTOGRAM_RADDR3__RAW = str
HISTOGRAM_ADDR_MASK = int
HISTOGRAM_ADDR_MASK__TYPE = str
HISTOGRAM_ADDR_MASK__RAW = str
HISTOGRAM_LEFT_TOP = int
HISTOGRAM_LEFT_TOP__TYPE = str
HISTOGRAM_LEFT_TOP__RAW = str
HISTOGRAM_WIDTH_HEIGHT = int
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
XOR_HIST_BAYER = int
XOR_HIST_BAYER__TYPE = str
XOR_HIST_BAYER__RAW = str
SENSI2C_DRIVE = int
SENSI2C_DRIVE__TYPE = str
SENSI2C_DRIVE__RAW = str
SENSI2C_IBUF_LOW_PWR = str
SENSI2C_IBUF_LOW_PWR__TYPE = str
SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_SLEW = str
SENSI2C_SLEW__TYPE = str
SENSI2C_SLEW__RAW = str
VOSPI_MRST = int
VOSPI_MRST__TYPE = str
VOSPI_MRST__RAW = str
VOSPI_MRST_BITS = int
VOSPI_MRST_BITS__TYPE = str
VOSPI_MRST_BITS__RAW = str
VOSPI_RST_SEQ = int
VOSPI_RST_SEQ__TYPE = str
VOSPI_RST_SEQ__RAW = str
VOSPI_SPI_SEQ = int
VOSPI_SPI_SEQ__TYPE = str
VOSPI_SPI_SEQ__RAW = str
VOSPI_MCLK = int
VOSPI_MCLK__TYPE = str
VOSPI_MCLK__RAW = str
VOSPI_MCLK_BITS = int
VOSPI_MCLK_BITS__TYPE = str
VOSPI_MCLK_BITS__RAW = str
VOSPI_EN = int
VOSPI_EN__TYPE = str
VOSPI_EN__RAW = str
VOSPI_EN_BITS = int
VOSPI_EN_BITS__TYPE = str
VOSPI_EN_BITS__RAW = str
VOSPI_OUT_EN = int
VOSPI_OUT_EN__TYPE = str
VOSPI_OUT_EN__RAW = str
VOSPI_OUT_EN_BITS = int
VOSPI_OUT_EN_BITS__TYPE = str
VOSPI_OUT_EN_BITS__RAW = str
VOSPI_OUT_EN_SINGL = int
VOSPI_OUT_EN_SINGL__TYPE = str
VOSPI_OUT_EN_SINGL__RAW = str
VOSPI_RESET_ERR = int
VOSPI_RESET_ERR__TYPE = str
VOSPI_RESET_ERR__RAW = str
VOSPI_SPI_CLK = int
VOSPI_SPI_CLK__TYPE = str
VOSPI_SPI_CLK__RAW = str
VOSPI_SPI_CLK_BITS = int
VOSPI_SPI_CLK_BITS__TYPE = str
VOSPI_SPI_CLK_BITS__RAW = str
VOSPI_SEGM0_OK = int
VOSPI_SEGM0_OK__TYPE = str
VOSPI_SEGM0_OK__RAW = str
VOSPI_SEGM0_OK_BITS = int
VOSPI_SEGM0_OK_BITS__TYPE = str
VOSPI_SEGM0_OK_BITS__RAW = str
VOSPI_VSYNC = int
VOSPI_VSYNC__TYPE = str
VOSPI_VSYNC__RAW = str
VOSPI_VSYNC_BITS = int
VOSPI_VSYNC_BITS__TYPE = str
VOSPI_VSYNC_BITS__RAW = str
VOSPI_NORESYNC = int
VOSPI_NORESYNC__TYPE = str
VOSPI_NORESYNC__RAW = str
VOSPI_NORESYNC_BITS = int
VOSPI_NORESYNC_BITS__TYPE = str
VOSPI_NORESYNC_BITS__RAW = str
VOSPI_TELEMETRY = int
VOSPI_TELEMETRY__TYPE = str
VOSPI_TELEMETRY__RAW = str
VOSPI_TELEMETRY_BITS = int
VOSPI_TELEMETRY_BITS__TYPE = str
VOSPI_TELEMETRY_BITS__RAW = str
VOSPI_GPIO = int
VOSPI_GPIO__TYPE = str
VOSPI_GPIO__RAW = str
VOSPI_GPIO_BITS = int
VOSPI_GPIO_BITS__TYPE = str
VOSPI_GPIO_BITS__RAW = str
VOSPI_DBG_SRC = int
VOSPI_DBG_SRC__TYPE = str
VOSPI_DBG_SRC__RAW = str
VOSPI_DBG_SRC_BITS = int
VOSPI_DBG_SRC_BITS__TYPE = str
VOSPI_DBG_SRC_BITS__RAW = str
VOSPI_PACKET_WORDS = int
VOSPI_PACKET_WORDS__TYPE = str
VOSPI_PACKET_WORDS__RAW = str
VOSPI_NO_INVALID = int
VOSPI_NO_INVALID__TYPE = str
VOSPI_NO_INVALID__RAW = str
VOSPI_PACKETS_PER_LINE = int
VOSPI_PACKETS_PER_LINE__TYPE = str
VOSPI_PACKETS_PER_LINE__RAW = str
VOSPI_SEGMENT_FIRST = int
VOSPI_SEGMENT_FIRST__TYPE = str
VOSPI_SEGMENT_FIRST__RAW = str
VOSPI_SEGMENT_LAST = int
VOSPI_SEGMENT_LAST__TYPE = str
VOSPI_SEGMENT_LAST__RAW = str
VOSPI_PACKET_FIRST = int
VOSPI_PACKET_FIRST__TYPE = str
VOSPI_PACKET_FIRST__RAW = str
VOSPI_PACKET_LAST = int
VOSPI_PACKET_LAST__TYPE = str
VOSPI_PACKET_LAST__RAW = str
VOSPI_PACKET_TTT = int
VOSPI_PACKET_TTT__TYPE = str
VOSPI_PACKET_TTT__RAW = str
VOSPI_SOF_TO_HACT = int
VOSPI_SOF_TO_HACT__TYPE = str
VOSPI_SOF_TO_HACT__RAW = str
VOSPI_HACT_TO_HACT_EOF = int
VOSPI_HACT_TO_HACT_EOF__TYPE = str
VOSPI_HACT_TO_HACT_EOF__RAW = str
VOSPI_MCLK_HALFDIV = int
VOSPI_MCLK_HALFDIV__TYPE = str
VOSPI_MCLK_HALFDIV__RAW = str
VOSPI_MRST_MS = int
VOSPI_MRST_MS__TYPE = str
VOSPI_MRST_MS__RAW = str
VOSPI_MRST_AFTER_MS = int
VOSPI_MRST_AFTER_MS__TYPE = str
VOSPI_MRST_AFTER_MS__RAW = str
VOSPI_SPI_TIMEOUT_MS = int
VOSPI_SPI_TIMEOUT_MS__TYPE = str
VOSPI_SPI_TIMEOUT_MS__RAW = str
SENSOR_DATA_WIDTH = int
SENSOR_DATA_WIDTH__TYPE = str
SENSOR_DATA_WIDTH__RAW = str
SENSOR_FIFO_2DEPTH = int
SENSOR_FIFO_2DEPTH__TYPE = str
SENSOR_FIFO_2DEPTH__RAW = str
SENSOR_FIFO_DELAY = int
SENSOR_FIFO_DELAY__TYPE = str
SENSOR_FIFO_DELAY__RAW = str
HIST_SAXI_ADDR_MASK = int
HIST_SAXI_ADDR_MASK__TYPE = str
HIST_SAXI_ADDR_MASK__RAW = str
HIST_SAXI_MODE_WIDTH = int
HIST_SAXI_MODE_WIDTH__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
HIST_SAXI_EN = int
HIST_SAXI_EN__TYPE = str
HIST_SAXI_EN__RAW = str
HIST_SAXI_NRESET = int
HIST_SAXI_NRESET__TYPE = str
HIST_SAXI_NRESET__RAW = str
HIST_CONFIRM_WRITE = int
HIST_CONFIRM_WRITE__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
HIST_SAXI_AWCACHE = int
HIST_SAXI_AWCACHE__TYPE = str
HIST_SAXI_AWCACHE__RAW = str
HIST_SAXI_MODE_ADDR_MASK = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
NUM_FRAME_BITS = int
NUM_FRAME_BITS__TYPE = str
NUM_FRAME_BITS__RAW = str
SENS_SYNC_FBITS = int
SENS_SYNC_FBITS__TYPE = str
SENS_SYNC_FBITS__RAW = str
SENS_SYNC_LBITS = int
SENS_SYNC_LBITS__TYPE = str
SENS_SYNC_LBITS__RAW = str
SENS_SYNC_LATE_DFLT = int
SENS_SYNC_LATE_DFLT__TYPE = str
SENS_SYNC_LATE_DFLT__RAW = str
SENS_SYNC_MINBITS = int
SENS_SYNC_MINBITS__TYPE = str
SENS_SYNC_MINBITS__RAW = str
SENS_SYNC_MINPER = int
SENS_SYNC_MINPER__TYPE = str
SENS_SYNC_MINPER__RAW = str
IDELAY_VALUE = int
IDELAY_VALUE__TYPE = str
IDELAY_VALUE__RAW = str
PXD_DRIVE = int
PXD_DRIVE__TYPE = str
PXD_DRIVE__RAW = str
PXD_IBUF_LOW_PWR = str
PXD_IBUF_LOW_PWR__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str
PXD_SLEW = str
PXD_SLEW__TYPE = str
PXD_SLEW__RAW = str
VOSPI_DRIVE = int
VOSPI_DRIVE__TYPE = str
VOSPI_DRIVE__RAW = str
VOSPI_IBUF_LOW_PWR = str
VOSPI_IBUF_LOW_PWR__TYPE = str
VOSPI_IBUF_LOW_PWR__RAW = str
VOSPI_IOSTANDARD = str
VOSPI_IOSTANDARD__TYPE = str
VOSPI_IOSTANDARD__RAW = str
VOSPI_SLEW = str
VOSPI_SLEW__TYPE = str
VOSPI_SLEW__RAW = str
SENS_REFCLK_FREQUENCY = float
SENS_REFCLK_FREQUENCY__TYPE = str
SENS_REFCLK_FREQUENCY__RAW = str
SENS_HIGH_PERFORMANCE_MODE = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
PXD_CAPACITANCE = str
PXD_CAPACITANCE__TYPE = str
PXD_CAPACITANCE__RAW = str
PXD_CLK_DIV = int
PXD_CLK_DIV__TYPE = str
PXD_CLK_DIV__RAW = str
PXD_CLK_DIV_BITS = int
PXD_CLK_DIV_BITS__TYPE = str
PXD_CLK_DIV_BITS__RAW = str
SENS_PHASE_WIDTH = int
SENS_PHASE_WIDTH__TYPE = str
SENS_PHASE_WIDTH__RAW = str
SENS_BANDWIDTH = str
SENS_BANDWIDTH__TYPE = str
SENS_BANDWIDTH__RAW = str
CLKIN_PERIOD_SENSOR = float
CLKIN_PERIOD_SENSOR__TYPE = str
CLKIN_PERIOD_SENSOR__RAW = str
CLKFBOUT_MULT_SENSOR = int
CLKFBOUT_MULT_SENSOR__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CLKFBOUT_PHASE_SENSOR = float
CLKFBOUT_PHASE_SENSOR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
IPCLK_PHASE = float
IPCLK_PHASE__TYPE = str
IPCLK_PHASE__RAW = str
IPCLK2X_PHASE = float
IPCLK2X_PHASE__TYPE = str
IPCLK2X_PHASE__RAW = str
PXD_IOSTANDARD = str
PXD_IOSTANDARD__TYPE = str
PXD_IOSTANDARD__RAW = str
SENSI2C_IOSTANDARD = str
SENSI2C_IOSTANDARD__TYPE = str
SENSI2C_IOSTANDARD__RAW = str
HISPI_UNTUNED_SPLIT = str
HISPI_UNTUNED_SPLIT__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
HISPI_DIFF_TERM = str
HISPI_DIFF_TERM__TYPE = str
HISPI_DIFF_TERM__RAW = str
HISPI_IOSTANDARD = str
HISPI_IOSTANDARD__TYPE = str
HISPI_IOSTANDARD__RAW = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS0__TYPE = str
BUF_IPCLK_SENS0__RAW = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS0__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str
BUF_IPCLK_SENS1 = str
BUF_IPCLK_SENS1__TYPE = str
BUF_IPCLK_SENS1__RAW = str
BUF_IPCLK2X_SENS1 = str
BUF_IPCLK2X_SENS1__TYPE = str
BUF_IPCLK2X_SENS1__RAW = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS2__TYPE = str
BUF_IPCLK_SENS2__RAW = str
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS2__TYPE = str
BUF_IPCLK2X_SENS2__RAW = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS3__TYPE = str
BUF_IPCLK_SENS3__RAW = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS3__TYPE = str
BUF_IPCLK2X_SENS3__RAW = str
SENS_DIVCLK_DIVIDE = int
SENS_DIVCLK_DIVIDE__TYPE = str
SENS_DIVCLK_DIVIDE__RAW = str
SENS_REF_JITTER1 = float
SENS_REF_JITTER1__TYPE = str
SENS_REF_JITTER1__RAW = str
SENS_REF_JITTER2 = float
SENS_REF_JITTER2__TYPE = str
SENS_REF_JITTER2__RAW = str
SENS_SS_EN = str
SENS_SS_EN__TYPE = str
SENS_SS_EN__RAW = str
SENS_SS_MODE = str
SENS_SS_MODE__TYPE = str
SENS_SS_MODE__RAW = str
SENS_SS_MOD_PERIOD = int
SENS_SS_MOD_PERIOD__TYPE = str
SENS_SS_MOD_PERIOD__RAW = str
HISPI_MSB_FIRST = int
HISPI_MSB_FIRST__TYPE = str
HISPI_MSB_FIRST__RAW = str
HISPI_NUMLANES = int
HISPI_NUMLANES__TYPE = str
HISPI_NUMLANES__RAW = str
HISPI_DELAY_CLK0 = str
HISPI_DELAY_CLK0__TYPE = str
HISPI_DELAY_CLK0__RAW = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK1__TYPE = str
HISPI_DELAY_CLK1__RAW = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK2__TYPE = str
HISPI_DELAY_CLK2__RAW = str
HISPI_DELAY_CLK3 = str
HISPI_DELAY_CLK3__TYPE = str
HISPI_DELAY_CLK3__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM0__TYPE = str
HISPI_MMCM0__RAW = str
HISPI_MMCM1 = str
HISPI_MMCM1__TYPE = str
HISPI_MMCM1__RAW = str
HISPI_MMCM2 = str
HISPI_MMCM2__TYPE = str
HISPI_MMCM2__RAW = str
HISPI_MMCM3 = str
HISPI_MMCM3__TYPE = str
HISPI_MMCM3__RAW = str
HISPI_KEEP_IRST = int
HISPI_KEEP_IRST__TYPE = str
HISPI_KEEP_IRST__RAW = str
HISPI_WAIT_ALL_LANES = int
HISPI_WAIT_ALL_LANES__TYPE = str
HISPI_WAIT_ALL_LANES__RAW = str
HISPI_FIFO_DEPTH = int
HISPI_FIFO_DEPTH__TYPE = str
HISPI_FIFO_DEPTH__RAW = str
HISPI_FIFO_START = int
HISPI_FIFO_START__TYPE = str
HISPI_FIFO_START__RAW = str
HISPI_CAPACITANCE = str
HISPI_CAPACITANCE__TYPE = str
HISPI_CAPACITANCE__RAW = str
HISPI_DQS_BIAS = str
HISPI_DQS_BIAS__TYPE = str
HISPI_DQS_BIAS__RAW = str
HISPI_IBUF_DELAY_VALUE = str
HISPI_IBUF_DELAY_VALUE__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
HISPI_IBUF_LOW_PWR = str
HISPI_IBUF_LOW_PWR__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
HISPI_IFD_DELAY_VALUE = str
HISPI_IFD_DELAY_VALUE__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CMPRS_NUM_AFI_CHN = int
CMPRS_NUM_AFI_CHN__TYPE = str
CMPRS_NUM_AFI_CHN__RAW = str
CMPRS_GROUP_ADDR = int
CMPRS_GROUP_ADDR__TYPE = str
CMPRS_GROUP_ADDR__RAW = str
CMPRS_BASE_INC = int
CMPRS_BASE_INC__TYPE = str
CMPRS_BASE_INC__RAW = str
CMPRS_AFIMUX_RADDR0 = int
CMPRS_AFIMUX_RADDR0__TYPE = str
CMPRS_AFIMUX_RADDR0__RAW = str
CMPRS_AFIMUX_RADDR1 = int
CMPRS_AFIMUX_RADDR1__TYPE = str
CMPRS_AFIMUX_RADDR1__RAW = str
CMPRS_AFIMUX_MASK = int
CMPRS_AFIMUX_MASK__TYPE = str
CMPRS_AFIMUX_MASK__RAW = str
CMPRS_STATUS_REG_BASE = int
CMPRS_STATUS_REG_BASE__TYPE = str
CMPRS_STATUS_REG_BASE__RAW = str
CMPRS_HIFREQ_REG_BASE = int
CMPRS_HIFREQ_REG_BASE__TYPE = str
CMPRS_HIFREQ_REG_BASE__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
CMPRS_AFIMUX_REG_ADDR1__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
CMPRS_STATUS_REG_INC = int
CMPRS_STATUS_REG_INC__TYPE = str
CMPRS_STATUS_REG_INC__RAW = str
CMPRS_HIFREQ_REG_INC = int
CMPRS_HIFREQ_REG_INC__TYPE = str
CMPRS_HIFREQ_REG_INC__RAW = str
CMPRS_MASK = int
CMPRS_MASK__TYPE = str
CMPRS_MASK__RAW = str
CMPRS_CONTROL_REG = int
CMPRS_CONTROL_REG__TYPE = str
CMPRS_CONTROL_REG__RAW = str
CMPRS_STATUS_CNTRL = int
CMPRS_STATUS_CNTRL__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
CMPRS_FORMAT = int
CMPRS_FORMAT__TYPE = str
CMPRS_FORMAT__RAW = str
CMPRS_COLOR_SATURATION = int
CMPRS_COLOR_SATURATION__TYPE = str
CMPRS_COLOR_SATURATION__RAW = str
CMPRS_CORING_MODE = int
CMPRS_CORING_MODE__TYPE = str
CMPRS_CORING_MODE__RAW = str
CMPRS_INTERRUPTS = int
CMPRS_INTERRUPTS__TYPE = str
CMPRS_INTERRUPTS__RAW = str
CMPRS_TABLES = int
CMPRS_TABLES__TYPE = str
CMPRS_TABLES__RAW = str
TABLE_QUANTIZATION_INDEX = int
TABLE_QUANTIZATION_INDEX__TYPE = str
TABLE_QUANTIZATION_INDEX__RAW = str
TABLE_CORING_INDEX = int
TABLE_CORING_INDEX__TYPE = str
TABLE_CORING_INDEX__RAW = str
TABLE_FOCUS_INDEX = int
TABLE_FOCUS_INDEX__TYPE = str
TABLE_FOCUS_INDEX__RAW = str
TABLE_HUFFMAN_INDEX = int
TABLE_HUFFMAN_INDEX__TYPE = str
TABLE_HUFFMAN_INDEX__RAW = str
CMPRS_CBIT_RUN = int
CMPRS_CBIT_RUN__TYPE = str
CMPRS_CBIT_RUN__RAW = str
CMPRS_CBIT_RUN_BITS = int
CMPRS_CBIT_RUN_BITS__TYPE = str
CMPRS_CBIT_RUN_BITS__RAW = str
CMPRS_CBIT_QBANK = int
CMPRS_CBIT_QBANK__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
CMPRS_CBIT_QBANK_BITS = int
CMPRS_CBIT_QBANK_BITS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_DCSUB__TYPE = str
CMPRS_CBIT_DCSUB__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
CMPRS_CBIT_DCSUB_BITS__RAW = str
CMPRS_CBIT_CMODE = int
CMPRS_CBIT_CMODE__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
CMPRS_CBIT_CMODE_BITS = int
CMPRS_CBIT_CMODE_BITS__TYPE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
CMPRS_CBIT_FRAMES = int
CMPRS_CBIT_FRAMES__TYPE = str
CMPRS_CBIT_FRAMES__RAW = str
CMPRS_CBIT_FRAMES_BITS = int
CMPRS_CBIT_FRAMES_BITS__TYPE = str
CMPRS_CBIT_FRAMES_BITS__RAW = str
CMPRS_CBIT_BE16 = int
CMPRS_CBIT_BE16__TYPE = str
CMPRS_CBIT_BE16__RAW = str
CMPRS_CBIT_BE16_BITS = int
CMPRS_CBIT_BE16_BITS__TYPE = str
CMPRS_CBIT_BE16_BITS__RAW = str
CMPRS_CBIT_BAYER = int
CMPRS_CBIT_BAYER__TYPE = str
CMPRS_CBIT_BAYER__RAW = str
CMPRS_CBIT_BAYER_BITS = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
CMPRS_CBIT_FOCUS = int
CMPRS_CBIT_FOCUS__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
CMPRS_CBIT_FOCUS_BITS = int
CMPRS_CBIT_FOCUS_BITS__TYPE = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMPRS_CBIT_ROWS_LSB = int
CMPRS_CBIT_ROWS_LSB__TYPE = str
CMPRS_CBIT_ROWS_LSB__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS = int
CMPRS_CBIT_ROWS_LSB_BITS__TYPE = str
CMPRS_CBIT_ROWS_LSB_BITS__RAW = str
CMPRS_CBIT_RUN_RST = int
CMPRS_CBIT_RUN_RST__TYPE = str
CMPRS_CBIT_RUN_RST__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
CMPRS_CBIT_RUN_STANDALONE__TYPE = str
CMPRS_CBIT_RUN_STANDALONE__RAW = str
CMPRS_CBIT_RUN_ENABLE = int
CMPRS_CBIT_RUN_ENABLE__TYPE = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
CMPRS_CBIT_CMODE_JPEG18 = int
CMPRS_CBIT_CMODE_JPEG18__TYPE = str
CMPRS_CBIT_CMODE_JPEG18__RAW = str
CMPRS_CBIT_CMODE_MONO6 = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
CMPRS_CBIT_CMODE_MONO6__RAW = str
CMPRS_CBIT_CMODE_JP46 = int
CMPRS_CBIT_CMODE_JP46__TYPE = str
CMPRS_CBIT_CMODE_JP46__RAW = str
CMPRS_CBIT_CMODE_JP46DC = int
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
CMPRS_CBIT_CMODE_JP4 = int
CMPRS_CBIT_CMODE_JP4__TYPE = str
CMPRS_CBIT_CMODE_JP4__RAW = str
CMPRS_CBIT_CMODE_JP4DC = int
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFF = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO1__TYPE = str
CMPRS_CBIT_CMODE_MONO1__RAW = str
CMPRS_CBIT_CMODE_MONO4 = int
CMPRS_CBIT_CMODE_MONO4__TYPE = str
CMPRS_CBIT_CMODE_MONO4__RAW = str
CMPRS_CBIT_CMODE_RAW = int
CMPRS_CBIT_CMODE_RAW__TYPE = str
CMPRS_CBIT_CMODE_RAW__RAW = str
CMPRS_CBIT_FRAMES_SINGLE = int
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
CMPRS_COLOR18 = int
CMPRS_COLOR18__TYPE = str
CMPRS_COLOR18__RAW = str
CMPRS_COLOR20 = int
CMPRS_COLOR20__TYPE = str
CMPRS_COLOR20__RAW = str
CMPRS_MONO16 = int
CMPRS_MONO16__TYPE = str
CMPRS_MONO16__RAW = str
CMPRS_JP4 = int
CMPRS_JP4__TYPE = str
CMPRS_JP4__RAW = str
CMPRS_JP4DIFF = int
CMPRS_JP4DIFF__TYPE = str
CMPRS_JP4DIFF__RAW = str
CMPRS_RAW = int
CMPRS_RAW__TYPE = str
CMPRS_RAW__RAW = str
CMPRS_MONO8 = int
CMPRS_MONO8__TYPE = str
CMPRS_MONO8__RAW = str
CMPRS_FRMT_MBCM1 = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_FRMT_MBCM1__RAW = str
CMPRS_FRMT_MBCM1_BITS = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
CMPRS_FRMT_MBCM1_BITS__RAW = str
CMPRS_FRMT_MBRM1 = int
CMPRS_FRMT_MBRM1__TYPE = str
CMPRS_FRMT_MBRM1__RAW = str
CMPRS_FRMT_MBRM1_BITS = int
CMPRS_FRMT_MBRM1_BITS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
CMPRS_FRMT_LMARG = int
CMPRS_FRMT_LMARG__TYPE = str
CMPRS_FRMT_LMARG__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
CMPRS_FRMT_LMARG_BITS__RAW = str
CMPRS_CSAT_CB = int
CMPRS_CSAT_CB__TYPE = str
CMPRS_CSAT_CB__RAW = str
CMPRS_CSAT_CB_BITS = int
CMPRS_CSAT_CB_BITS__TYPE = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CSAT_CR = int
CMPRS_CSAT_CR__TYPE = str
CMPRS_CSAT_CR__RAW = str
CMPRS_CSAT_CR_BITS = int
CMPRS_CSAT_CR_BITS__TYPE = str
CMPRS_CSAT_CR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMPRS_CORING_BITS__TYPE = str
CMPRS_CORING_BITS__RAW = str
CMPRS_TIMEOUT_BITS = int
CMPRS_TIMEOUT_BITS__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
CMPRS_TIMEOUT = int
CMPRS_TIMEOUT__TYPE = str
CMPRS_TIMEOUT__RAW = str
CMPRS_AFIMUX_EN = int
CMPRS_AFIMUX_EN__TYPE = str
CMPRS_AFIMUX_EN__RAW = str
CMPRS_AFIMUX_RST = int
CMPRS_AFIMUX_RST__TYPE = str
CMPRS_AFIMUX_RST__RAW = str
CMPRS_AFIMUX_MODE = int
CMPRS_AFIMUX_MODE__TYPE = str
CMPRS_AFIMUX_MODE__RAW = str
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
CMPRS_AFIMUX_SA_LEN = int
CMPRS_AFIMUX_SA_LEN__TYPE = str
CMPRS_AFIMUX_SA_LEN__RAW = str
CMPRS_AFIMUX_WIDTH = int
CMPRS_AFIMUX_WIDTH__TYPE = str
CMPRS_AFIMUX_WIDTH__RAW = str
CMPRS_AFIMUX_CYCBITS = int
CMPRS_AFIMUX_CYCBITS__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
AFI_MUX_BUF_LATENCY = int
AFI_MUX_BUF_LATENCY__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
GPIO_DRIVE = int
GPIO_DRIVE__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_ADDR = int
GPIO_ADDR__TYPE = str
GPIO_ADDR__RAW = str
GPIO_MASK = int
GPIO_MASK__TYPE = str
GPIO_MASK__RAW = str
GPIO_STATUS_REG_ADDR = int
GPIO_STATUS_REG_ADDR__TYPE = str
GPIO_STATUS_REG_ADDR__RAW = str
GPIO_IBUF_LOW_PWR = str
GPIO_IBUF_LOW_PWR__TYPE = str
GPIO_IBUF_LOW_PWR__RAW = str
GPIO_IOSTANDARD = str
GPIO_IOSTANDARD__TYPE = str
GPIO_IOSTANDARD__RAW = str
GPIO_SLEW = str
GPIO_SLEW__TYPE = str
GPIO_SLEW__RAW = str
GPIO_SET_PINS = int
GPIO_SET_PINS__TYPE = str
GPIO_SET_PINS__RAW = str
GPIO_SET_STATUS = int
GPIO_SET_STATUS__TYPE = str
GPIO_SET_STATUS__RAW = str
GPIO_N = int
GPIO_N__TYPE = str
GPIO_N__RAW = str
GPIO_PORTEN = int
GPIO_PORTEN__TYPE = str
GPIO_PORTEN__RAW = str
RTC_ADDR = int
RTC_ADDR__TYPE = str
RTC_ADDR__RAW = str
CAMSYNC_ADDR = int
CAMSYNC_ADDR__TYPE = str
CAMSYNC_ADDR__RAW = str
RTC_STATUS_REG_ADDR = int
RTC_STATUS_REG_ADDR__TYPE = str
RTC_STATUS_REG_ADDR__RAW = str
RTC_SEC_USEC_ADDR = int
RTC_SEC_USEC_ADDR__TYPE = str
RTC_SEC_USEC_ADDR__RAW = str
RTC_MASK = int
RTC_MASK__TYPE = str
RTC_MASK__RAW = str
CAMSYNC_MASK = int
CAMSYNC_MASK__TYPE = str
CAMSYNC_MASK__RAW = str
CAMSYNC_MODE = int
CAMSYNC_MODE__TYPE = str
CAMSYNC_MODE__RAW = str
CAMSYNC_TRIG_SRC = int
CAMSYNC_TRIG_SRC__TYPE = str
CAMSYNC_TRIG_SRC__RAW = str
CAMSYNC_TRIG_DST = int
CAMSYNC_TRIG_DST__TYPE = str
CAMSYNC_TRIG_DST__RAW = str
CAMSYNC_TRIG_PERIOD = int
CAMSYNC_TRIG_PERIOD__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY0__TYPE = str
CAMSYNC_TRIG_DELAY0__RAW = str
CAMSYNC_TRIG_DELAY1 = int
CAMSYNC_TRIG_DELAY1__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
CAMSYNC_TRIG_DELAY2 = int
CAMSYNC_TRIG_DELAY2__TYPE = str
CAMSYNC_TRIG_DELAY2__RAW = str
CAMSYNC_TRIG_DELAY3 = int
CAMSYNC_TRIG_DELAY3__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
CAMSYNC_EN_BIT = int
CAMSYNC_EN_BIT__TYPE = str
CAMSYNC_EN_BIT__RAW = str
CAMSYNC_SNDEN_BIT = int
CAMSYNC_SNDEN_BIT__TYPE = str
CAMSYNC_SNDEN_BIT__RAW = str
CAMSYNC_EXTERNAL_BIT = int
CAMSYNC_EXTERNAL_BIT__TYPE = str
CAMSYNC_EXTERNAL_BIT__RAW = str
CAMSYNC_TRIGGERED_BIT = int
CAMSYNC_TRIGGERED_BIT__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
CAMSYNC_MASTER_BIT = int
CAMSYNC_MASTER_BIT__TYPE = str
CAMSYNC_MASTER_BIT__RAW = str
CAMSYNC_CHN_EN_BIT = int
CAMSYNC_CHN_EN_BIT__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
CAMSYNC_PRE_MAGIC = int
CAMSYNC_PRE_MAGIC__TYPE = str
CAMSYNC_PRE_MAGIC__RAW = str
CAMSYNC_POST_MAGIC = int
CAMSYNC_POST_MAGIC__TYPE = str
CAMSYNC_POST_MAGIC__RAW = str
CAMSYNC_GPIO_EXT_IN = int
CAMSYNC_GPIO_EXT_IN__TYPE = str
CAMSYNC_GPIO_EXT_IN__RAW = str
CAMSYNC_GPIO_INT_IN = int
CAMSYNC_GPIO_INT_IN__TYPE = str
CAMSYNC_GPIO_INT_IN__RAW = str
CAMSYNC_GPIO_EXT_OUT = int
CAMSYNC_GPIO_EXT_OUT__TYPE = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
CAMSYNC_GPIO_INT_OUT = int
CAMSYNC_GPIO_INT_OUT__TYPE = str
CAMSYNC_GPIO_INT_OUT__RAW = str
RTC_MHZ = int
RTC_MHZ__TYPE = str
RTC_MHZ__RAW = str
RTC_BITC_PREDIV = int
RTC_BITC_PREDIV__TYPE = str
RTC_BITC_PREDIV__RAW = str
RTC_SET_USEC = int
RTC_SET_USEC__TYPE = str
RTC_SET_USEC__RAW = str
RTC_SET_SEC = int
RTC_SET_SEC__TYPE = str
RTC_SET_SEC__RAW = str
RTC_SET_CORR = int
RTC_SET_CORR__TYPE = str
RTC_SET_CORR__RAW = str
RTC_SET_STATUS = int
RTC_SET_STATUS__TYPE = str
RTC_SET_STATUS__RAW = str
CMDFRAMESEQ_ADDR_BASE = int
CMDFRAMESEQ_ADDR_BASE__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
CMDFRAMESEQ_ADDR_INC = int
CMDFRAMESEQ_ADDR_INC__TYPE = str
CMDFRAMESEQ_ADDR_INC__RAW = str
CMDFRAMESEQ_MASK = int
CMDFRAMESEQ_MASK__TYPE = str
CMDFRAMESEQ_MASK__RAW = str
CMDFRAMESEQ_DEPTH = int
CMDFRAMESEQ_DEPTH__TYPE = str
CMDFRAMESEQ_DEPTH__RAW = str
CMDFRAMESEQ_ABS = int
CMDFRAMESEQ_ABS__TYPE = str
CMDFRAMESEQ_ABS__RAW = str
CMDFRAMESEQ_REL = int
CMDFRAMESEQ_REL__TYPE = str
CMDFRAMESEQ_REL__RAW = str
CMDFRAMESEQ_CTRL = int
CMDFRAMESEQ_CTRL__TYPE = str
CMDFRAMESEQ_CTRL__RAW = str
CMDFRAMESEQ_RST_BIT = int
CMDFRAMESEQ_RST_BIT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
CMDFRAMESEQ_RUN_BIT = int
CMDFRAMESEQ_RUN_BIT__TYPE = str
CMDFRAMESEQ_RUN_BIT__RAW = str
CMDFRAMESEQ_IRQ_BIT = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
CMDSEQMUX_ADDR = int
CMDSEQMUX_ADDR__TYPE = str
CMDSEQMUX_ADDR__RAW = str
CMDSEQMUX_MASK = int
CMDSEQMUX_MASK__TYPE = str
CMDSEQMUX_MASK__RAW = str
CMDSEQMUX_STATUS = int
CMDSEQMUX_STATUS__TYPE = str
CMDSEQMUX_STATUS__RAW = str
LOGGER_ADDR = int
LOGGER_ADDR__TYPE = str
LOGGER_ADDR__RAW = str
LOGGER_STATUS = int
LOGGER_STATUS__TYPE = str
LOGGER_STATUS__RAW = str
LOGGER_STATUS_REG_ADDR = int
LOGGER_STATUS_REG_ADDR__TYPE = str
LOGGER_STATUS_REG_ADDR__RAW = str
LOGGER_MASK = int
LOGGER_MASK__TYPE = str
LOGGER_MASK__RAW = str
LOGGER_STATUS_MASK = int
LOGGER_STATUS_MASK__TYPE = str
LOGGER_STATUS_MASK__RAW = str
LOGGER_PAGE_IMU = int
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_IMU__RAW = str
LOGGER_PAGE_GPS = int
LOGGER_PAGE_GPS__TYPE = str
LOGGER_PAGE_GPS__RAW = str
LOGGER_PAGE_MSG = int
LOGGER_PAGE_MSG__TYPE = str
LOGGER_PAGE_MSG__RAW = str
LOGGER_PERIOD = int
LOGGER_PERIOD__TYPE = str
LOGGER_PERIOD__RAW = str
LOGGER_BIT_DURATION = int
LOGGER_BIT_DURATION__TYPE = str
LOGGER_BIT_DURATION__RAW = str
LOGGER_BIT_HALF_PERIOD = int
LOGGER_BIT_HALF_PERIOD__TYPE = str
LOGGER_BIT_HALF_PERIOD__RAW = str
LOGGER_CONFIG = int
LOGGER_CONFIG__TYPE = str
LOGGER_CONFIG__RAW = str
LOGGER_CONF_IMU = int
LOGGER_CONF_IMU__TYPE = str
LOGGER_CONF_IMU__RAW = str
LOGGER_CONF_IMU_BITS = int
LOGGER_CONF_IMU_BITS__TYPE = str
LOGGER_CONF_IMU_BITS__RAW = str
LOGGER_CONF_GPS = int
LOGGER_CONF_GPS__TYPE = str
LOGGER_CONF_GPS__RAW = str
LOGGER_CONF_GPS_BITS = int
LOGGER_CONF_GPS_BITS__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
LOGGER_CONF_MSG = int
LOGGER_CONF_MSG__TYPE = str
LOGGER_CONF_MSG__RAW = str
LOGGER_CONF_MSG_BITS = int
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_CONF_MSG_BITS__RAW = str
LOGGER_CONF_SYN = int
LOGGER_CONF_SYN__TYPE = str
LOGGER_CONF_SYN__RAW = str
LOGGER_CONF_SYN_BITS = int
LOGGER_CONF_SYN_BITS__TYPE = str
LOGGER_CONF_SYN_BITS__RAW = str
LOGGER_CONF_EN = int
LOGGER_CONF_EN__TYPE = str
LOGGER_CONF_EN__RAW = str
LOGGER_CONF_EN_BITS = int
LOGGER_CONF_EN_BITS__TYPE = str
LOGGER_CONF_EN_BITS__RAW = str
LOGGER_CONF_DBG = int
LOGGER_CONF_DBG__TYPE = str
LOGGER_CONF_DBG__RAW = str
LOGGER_CONF_DBG_BITS = int
LOGGER_CONF_DBG_BITS__TYPE = str
LOGGER_CONF_DBG_BITS__RAW = str
MULT_SAXI_HALF_BRAM_IN = int
MULT_SAXI_HALF_BRAM_IN__TYPE = str
MULT_SAXI_HALF_BRAM_IN__RAW = str
MULT_SAXI_WLOG = int
MULT_SAXI_WLOG__TYPE = str
MULT_SAXI_WLOG__RAW = str
MULT_SAXI_ADDR = int
MULT_SAXI_ADDR__TYPE = str
MULT_SAXI_ADDR__RAW = str
MULT_SAXI_IRQLEN_ADDR = int
MULT_SAXI_IRQLEN_ADDR__TYPE = str
MULT_SAXI_IRQLEN_ADDR__RAW = str
MULT_SAXI_CNTRL_ADDR = int
MULT_SAXI_CNTRL_ADDR__TYPE = str
MULT_SAXI_CNTRL_ADDR__RAW = str
MULT_SAXI_CNTRL_MODE = int
MULT_SAXI_CNTRL_MODE__TYPE = str
MULT_SAXI_CNTRL_MODE__RAW = str
MULT_SAXI_CNTRL_STATUS = int
MULT_SAXI_CNTRL_STATUS__TYPE = str
MULT_SAXI_CNTRL_STATUS__RAW = str
MULT_SAXI_CNTRL_IRQ = int
MULT_SAXI_CNTRL_IRQ__TYPE = str
MULT_SAXI_CNTRL_IRQ__RAW = str
MULT_SAXI_POINTERS_REG = int
MULT_SAXI_POINTERS_REG__TYPE = str
MULT_SAXI_POINTERS_REG__RAW = str
MULT_SAXI_STATUS_REG = int
MULT_SAXI_STATUS_REG__TYPE = str
MULT_SAXI_STATUS_REG__RAW = str
MULT_SAXI_HALF_BRAM = int
MULT_SAXI_HALF_BRAM__TYPE = str
MULT_SAXI_HALF_BRAM__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG0__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
MULT_SAXI_BSLOG1 = int
MULT_SAXI_BSLOG1__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
MULT_SAXI_BSLOG2 = int
MULT_SAXI_BSLOG2__TYPE = str
MULT_SAXI_BSLOG2__RAW = str
MULT_SAXI_BSLOG3 = int
MULT_SAXI_BSLOG3__TYPE = str
MULT_SAXI_BSLOG3__RAW = str
MULT_SAXI_MASK = int
MULT_SAXI_MASK__TYPE = str
MULT_SAXI_MASK__RAW = str
MULT_SAXI_IRQLEN_MASK = int
MULT_SAXI_IRQLEN_MASK__TYPE = str
MULT_SAXI_IRQLEN_MASK__RAW = str
MULT_SAXI_CNTRL_MASK = int
MULT_SAXI_CNTRL_MASK__TYPE = str
MULT_SAXI_CNTRL_MASK__RAW = str
MULT_SAXI_AWCACHE = int
MULT_SAXI_AWCACHE__TYPE = str
MULT_SAXI_AWCACHE__RAW = str
MULT_SAXI_ADV_WR = int
MULT_SAXI_ADV_WR__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
MULT_SAXI_ADV_RD = int
MULT_SAXI_ADV_RD__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
CLK_ADDR = int
CLK_ADDR__TYPE = str
CLK_ADDR__RAW = str
CLK_MASK = int
CLK_MASK__TYPE = str
CLK_MASK__RAW = str
CLK_STATUS_REG_ADDR = int
CLK_STATUS_REG_ADDR__TYPE = str
CLK_STATUS_REG_ADDR__RAW = str
CLK_CNTRL = int
CLK_CNTRL__TYPE = str
CLK_CNTRL__RAW = str
CLK_STATUS = int
CLK_STATUS__TYPE = str
CLK_STATUS__RAW = str
DEBUG_ADDR = int
DEBUG_ADDR__TYPE = str
DEBUG_ADDR__RAW = str
DEBUG_MASK = int
DEBUG_MASK__TYPE = str
DEBUG_MASK__RAW = str
DEBUG_STATUS_REG_ADDR = int
DEBUG_STATUS_REG_ADDR__TYPE = str
DEBUG_STATUS_REG_ADDR__RAW = str
DEBUG_READ_REG_ADDR = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
DEBUG_SHIFT_DATA = int
DEBUG_SHIFT_DATA__TYPE = str
DEBUG_SHIFT_DATA__RAW = str
DEBUG_LOAD = int
DEBUG_LOAD__TYPE = str
DEBUG_LOAD__RAW = str
DEBUG_SET_STATUS = int
DEBUG_SET_STATUS__TYPE = str
DEBUG_SET_STATUS__RAW = str
DEBUG_CMD_LATENCY = int
DEBUG_CMD_LATENCY__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
MULTICLK_IN_PERIOD = int
MULTICLK_IN_PERIOD__TYPE = str
MULTICLK_IN_PERIOD__RAW = str
MULTICLK_DIVCLK = int
MULTICLK_DIVCLK__TYPE = str
MULTICLK_DIVCLK__RAW = str
MULTICLK_MULT = int
MULTICLK_MULT__TYPE = str
MULTICLK_MULT__RAW = str
MULTICLK_DIV_DLYREF = int
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_DIV_DLYREF__RAW = str
MULTICLK_DIV_AXIHP = int
MULTICLK_DIV_AXIHP__TYPE = str
MULTICLK_DIV_AXIHP__RAW = str
MULTICLK_DIV_XCLK = int
MULTICLK_DIV_XCLK__TYPE = str
MULTICLK_DIV_XCLK__RAW = str
MULTICLK_DIV_XCLK2X = int
MULTICLK_DIV_XCLK2X__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
MULTICLK_DIV_SYNC = int
MULTICLK_DIV_SYNC__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
MULTICLK_PHASE_FB = float
MULTICLK_PHASE_FB__TYPE = str
MULTICLK_PHASE_FB__RAW = str
MULTICLK_PHASE_DLYREF = float
MULTICLK_PHASE_DLYREF__TYPE = str
MULTICLK_PHASE_DLYREF__RAW = str
MULTICLK_BUF_DLYREF = str
MULTICLK_BUF_DLYREF__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
MULTICLK_PHASE_AXIHP = float
MULTICLK_PHASE_AXIHP__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
MULTICLK_BUF_AXIHP = str
MULTICLK_BUF_AXIHP__TYPE = str
MULTICLK_BUF_AXIHP__RAW = str
MULTICLK_PHASE_XCLK = float
MULTICLK_PHASE_XCLK__TYPE = str
MULTICLK_PHASE_XCLK__RAW = str
MULTICLK_BUF_XCLK = str
MULTICLK_BUF_XCLK__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
MULTICLK_PHASE_SYNC = float
MULTICLK_PHASE_SYNC__TYPE = str
MULTICLK_PHASE_SYNC__RAW = str
MULTICLK_BUF_SYNC = str
MULTICLK_BUF_SYNC__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
CLKIN_PERIOD_PCLK = int
CLKIN_PERIOD_PCLK__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
DIVCLK_DIVIDE_PCLK = int
DIVCLK_DIVIDE_PCLK__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
CLKFBOUT_MULT_PCLK = int
CLKFBOUT_MULT_PCLK__TYPE = str
CLKFBOUT_MULT_PCLK__RAW = str
CLKOUT_DIV_PCLK = int
CLKOUT_DIV_PCLK__TYPE = str
CLKOUT_DIV_PCLK__RAW = str
CLKOUT_DIV_PCLK2X = int
CLKOUT_DIV_PCLK2X__TYPE = str
CLKOUT_DIV_PCLK2X__RAW = str
PHASE_CLK2X_PCLK = float
PHASE_CLK2X_PCLK__TYPE = str
PHASE_CLK2X_PCLK__RAW = str
BUF_CLK1X_PCLK = str
BUF_CLK1X_PCLK__TYPE = str
BUF_CLK1X_PCLK__RAW = str
BUF_CLK1X_PCLK2X = str
BUF_CLK1X_PCLK2X__TYPE = str
BUF_CLK1X_PCLK2X__RAW = str
MEMCLK_CAPACITANCE = str
MEMCLK_CAPACITANCE__TYPE = str
MEMCLK_CAPACITANCE__RAW = str
MEMCLK_IBUF_LOW_PWR = str
MEMCLK_IBUF_LOW_PWR__TYPE = str
MEMCLK_IBUF_LOW_PWR__RAW = str
MEMCLK_IOSTANDARD = str
MEMCLK_IOSTANDARD__TYPE = str
MEMCLK_IOSTANDARD__RAW = str
FFCLK0_CAPACITANCE = str
FFCLK0_CAPACITANCE__TYPE = str
FFCLK0_CAPACITANCE__RAW = str
FFCLK0_DIFF_TERM = str
FFCLK0_DIFF_TERM__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
FFCLK0_IBUF_LOW_PWR = str
FFCLK0_IBUF_LOW_PWR__TYPE = str
FFCLK0_IBUF_LOW_PWR__RAW = str
FFCLK0_IOSTANDARD = str
FFCLK0_IOSTANDARD__TYPE = str
FFCLK0_IOSTANDARD__RAW = str
FFCLK1_CAPACITANCE = str
FFCLK1_CAPACITANCE__TYPE = str
FFCLK1_CAPACITANCE__RAW = str
FFCLK1_DIFF_TERM = str
FFCLK1_DIFF_TERM__TYPE = str
FFCLK1_DIFF_TERM__RAW = str
FFCLK1_IBUF_LOW_PWR = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__RAW = str
FFCLK1_IOSTANDARD = str
FFCLK1_IOSTANDARD__TYPE = str
FFCLK1_IOSTANDARD__RAW = str
DLY_LANE0_ODELAY = int
DLY_LANE0_ODELAY__TYPE = str
DLY_LANE0_ODELAY__RAW = str
DLY_LANE0_IDELAY = int
DLY_LANE0_IDELAY__TYPE = str
DLY_LANE0_IDELAY__RAW = str
DLY_LANE1_ODELAY = int
DLY_LANE1_ODELAY__TYPE = str
DLY_LANE1_ODELAY__RAW = str
DLY_LANE1_IDELAY = int
DLY_LANE1_IDELAY__TYPE = str
DLY_LANE1_IDELAY__RAW = str
DLY_CMDA = int
DLY_CMDA__TYPE = str
DLY_CMDA__RAW = str
DLY_PHASE = int
DLY_PHASE__TYPE = str
DLY_PHASE__RAW = str
DEFAULT_STATUS_MODE = int
DEFAULT_STATUS_MODE__TYPE = str
DEFAULT_STATUS_MODE__RAW = str
LD_DLY_LANE0_ODELAY = int
LD_DLY_LANE0_ODELAY__TYPE = str
LD_DLY_LANE0_ODELAY__RAW = str
LD_DLY_LANE0_IDELAY = int
LD_DLY_LANE0_IDELAY__TYPE = str
LD_DLY_LANE0_IDELAY__RAW = str
LD_DLY_LANE1_ODELAY = int
LD_DLY_LANE1_ODELAY__TYPE = str
LD_DLY_LANE1_ODELAY__RAW = str
LD_DLY_LANE1_IDELAY = int
LD_DLY_LANE1_IDELAY__TYPE = str
LD_DLY_LANE1_IDELAY__RAW = str
LD_DLY_CMDA = int
LD_DLY_CMDA__TYPE = str
LD_DLY_CMDA__RAW = str
LD_DLY_PHASE = int
LD_DLY_PHASE__TYPE = str
LD_DLY_PHASE__RAW = str
DLY_SET = int
DLY_SET__TYPE = str
DLY_SET__RAW = str
T_RFC = int
T_RFC__TYPE = str
T_RFC__RAW = str
T_REFI = int
T_REFI__TYPE = str
T_REFI__RAW = str
DLY_DQ_IDELAY = int
DLY_DQ_IDELAY__TYPE = str
DLY_DQ_IDELAY__RAW = str
DLY_DQ_ODELAY = int
DLY_DQ_ODELAY__TYPE = str
DLY_DQ_ODELAY__RAW = str
DLY_DQS_IDELAY = int
DLY_DQS_IDELAY__TYPE = str
DLY_DQS_IDELAY__RAW = str
DLY_DQS_ODELAY = int
DLY_DQS_ODELAY__TYPE = str
DLY_DQS_ODELAY__RAW = str
DLY_DM_ODELAY = int
DLY_DM_ODELAY__TYPE = str
DLY_DM_ODELAY__RAW = str
DLY_CMDA_ODELAY = int
DLY_CMDA_ODELAY__TYPE = str
DLY_CMDA_ODELAY__RAW = str
DLY_LANE0_DQS_WLV_IDELAY = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
DLY_LANE1_DQS_WLV_IDELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
DQSTRI_FIRST = int
DQSTRI_FIRST__TYPE = str
DQSTRI_FIRST__RAW = str
DQSTRI_LAST = int
DQSTRI_LAST__TYPE = str
DQSTRI_LAST__RAW = str
DQTRI_FIRST = int
DQTRI_FIRST__TYPE = str
DQTRI_FIRST__RAW = str
DQTRI_LAST = int
DQTRI_LAST__TYPE = str
DQTRI_LAST__RAW = str
WBUF_DLY_DFLT = int
WBUF_DLY_DFLT__TYPE = str
WBUF_DLY_DFLT__RAW = str
WBUF_DLY_WLV = int
WBUF_DLY_WLV__TYPE = str
WBUF_DLY_WLV__RAW = str
INITIALIZE_OFFSET = int
INITIALIZE_OFFSET__TYPE = str
INITIALIZE_OFFSET__RAW = str
REFRESH_OFFSET = int
REFRESH_OFFSET__TYPE = str
REFRESH_OFFSET__RAW = str
WRITELEV_OFFSET = int
WRITELEV_OFFSET__TYPE = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
READ_PATTERN_OFFSET__TYPE = str
READ_PATTERN_OFFSET__RAW = str
WRITE_BLOCK_OFFSET = int
WRITE_BLOCK_OFFSET__TYPE = str
WRITE_BLOCK_OFFSET__RAW = str
READ_BLOCK_OFFSET = int
READ_BLOCK_OFFSET__TYPE = str
READ_BLOCK_OFFSET__RAW = str
STATUS_SEQ_SHFT = int
STATUS_SEQ_SHFT__TYPE = str
STATUS_SEQ_SHFT__RAW = str
STATUS_2LSB_SHFT = int
STATUS_2LSB_SHFT__TYPE = str
STATUS_2LSB_SHFT__RAW = str
STATUS_MSB_RSHFT = int
STATUS_MSB_RSHFT__TYPE = str
STATUS_MSB_RSHFT__RAW = str
STATUS_PSHIFTER_RDY_MASK = int
STATUS_PSHIFTER_RDY_MASK__TYPE = str
STATUS_PSHIFTER_RDY_MASK__RAW = str
FRAME_START_ADDRESS = int
FRAME_START_ADDRESS__TYPE = str
FRAME_START_ADDRESS__RAW = str
FRAME_START_ADDRESS_INC = int
FRAME_START_ADDRESS_INC__TYPE = str
FRAME_START_ADDRESS_INC__RAW = str
LAST_BUF_FRAME = int
LAST_BUF_FRAME__TYPE = str
LAST_BUF_FRAME__RAW = str
CAMSYNC_DELAY = int
CAMSYNC_DELAY__TYPE = str
CAMSYNC_DELAY__RAW = str
FRAME_FULL_WIDTH = int
FRAME_FULL_WIDTH__TYPE = str
FRAME_FULL_WIDTH__RAW = str
AFI_LO_ADDR64 = int
AFI_LO_ADDR64__TYPE = str
AFI_LO_ADDR64__RAW = str
AFI_SIZE64 = int
AFI_SIZE64__TYPE = str
AFI_SIZE64__RAW = str
WINDOW_WIDTH = int
WINDOW_WIDTH__TYPE = str
WINDOW_WIDTH__RAW = str
WINDOW_HEIGHT = int
WINDOW_HEIGHT__TYPE = str
WINDOW_HEIGHT__RAW = str
WINDOW_X0 = int
WINDOW_X0__TYPE = str
WINDOW_X0__RAW = str
WINDOW_Y0 = int
WINDOW_Y0__TYPE = str
WINDOW_Y0__RAW = str
SCANLINE_STARTX = int
SCANLINE_STARTX__TYPE = str
SCANLINE_STARTX__RAW = str
SCANLINE_STARTY = int
SCANLINE_STARTY__TYPE = str
SCANLINE_STARTY__RAW = str
SCANLINE_EXTRA_PAGES = int
SCANLINE_EXTRA_PAGES__TYPE = str
SCANLINE_EXTRA_PAGES__RAW = str
TILED_STARTX = int
TILED_STARTX__TYPE = str
TILED_STARTX__RAW = str
TILED_STARTY = int
TILED_STARTY__TYPE = str
TILED_STARTY__RAW = str
TILED_EXTRA_PAGES = int
TILED_EXTRA_PAGES__TYPE = str
TILED_EXTRA_PAGES__RAW = str
TILED_KEEP_OPEN = int
TILED_KEEP_OPEN__TYPE = str
TILED_KEEP_OPEN__RAW = str
TILE_WIDTH = int
TILE_WIDTH__TYPE = str
TILE_WIDTH__RAW = str
TILE_HEIGHT = int
TILE_HEIGHT__TYPE = str
TILE_HEIGHT__RAW = str
TILE_VSTEP = int
TILE_VSTEP__TYPE = str
TILE_VSTEP__RAW = str
TEST01_START_FRAME = int
TEST01_START_FRAME__TYPE = str
TEST01_START_FRAME__RAW = str
TEST01_NEXT_PAGE = int
TEST01_NEXT_PAGE__TYPE = str
TEST01_NEXT_PAGE__RAW = str
TEST01_SUSPEND = int
TEST01_SUSPEND__TYPE = str
TEST01_SUSPEND__RAW = str
TEST_INITIAL_BURST = int
TEST_INITIAL_BURST__TYPE = str
TEST_INITIAL_BURST__RAW = str
NUM_INTERRUPTS = int
NUM_INTERRUPTS__TYPE = str
NUM_INTERRUPTS__RAW = str
AXI_RDADDR_LATENCY = int
AXI_RDADDR_LATENCY__TYPE = str
AXI_RDADDR_LATENCY__RAW = str
AXI_WRADDR_LATENCY = int
AXI_WRADDR_LATENCY__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
AXI_WRDATA_LATENCY = int
AXI_WRDATA_LATENCY__TYPE = str
AXI_WRDATA_LATENCY__RAW = str
AXI_TASK_HOLD = float
AXI_TASK_HOLD__TYPE = str
AXI_TASK_HOLD__RAW = str
SIMUL_AXI_READ_WIDTH = int
SIMUL_AXI_READ_WIDTH__TYPE = str
SIMUL_AXI_READ_WIDTH__RAW = str
MEMCLK_PERIOD = float
MEMCLK_PERIOD__TYPE = str
MEMCLK_PERIOD__RAW = str
FCLK0_PERIOD = float
FCLK0_PERIOD__TYPE = str
FCLK0_PERIOD__RAW = str
FCLK1_PERIOD = float
FCLK1_PERIOD__TYPE = str
FCLK1_PERIOD__RAW = str
LWIR_DATA_FILE1 = str
LWIR_DATA_FILE1__TYPE = str
LWIR_DATA_FILE1__RAW = str
LWIR_DATA_FILE2 = str
LWIR_DATA_FILE2__TYPE = str
LWIR_DATA_FILE2__RAW = str
LWIR_DATA_FILE3 = str
LWIR_DATA_FILE3__TYPE = str
LWIR_DATA_FILE3__RAW = str
LWIR_DATA_FILE4 = str
LWIR_DATA_FILE4__TYPE = str
LWIR_DATA_FILE4__RAW = str
LWIR_WINDOW_WIDTH = int
LWIR_WINDOW_WIDTH__TYPE = str
LWIR_WINDOW_WIDTH__RAW = str
LWIR_WINDOW_HEIGHT = int
LWIR_WINDOW_HEIGHT__TYPE = str
LWIR_WINDOW_HEIGHT__RAW = str
LWIR_TELEMETRY = int
LWIR_TELEMETRY__TYPE = str
LWIR_TELEMETRY__RAW = str
LWIR_FRAME_PERIOD = int
LWIR_FRAME_PERIOD__TYPE = str
LWIR_FRAME_PERIOD__RAW = str
LWIR_FRAME_DELAY = int
LWIR_FRAME_DELAY__TYPE = str
LWIR_FRAME_DELAY__RAW = str
LWIR_MS_PERIOD = int
LWIR_MS_PERIOD__TYPE = str
LWIR_MS_PERIOD__RAW = str
LWIR_TELEMETRY_REV = int
LWIR_TELEMETRY_REV__TYPE = str
LWIR_TELEMETRY_REV__RAW = str
LWIR_TELEMETRY_STATUS = int
LWIR_TELEMETRY_STATUS__TYPE = str
LWIR_TELEMETRY_STATUS__RAW = str
LWIR_TELEMETRY_SREV = int
LWIR_TELEMETRY_SREV__TYPE = str
LWIR_TELEMETRY_SREV__RAW = str
LWIR_TELEMETRY_TEMP_COUTS = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
LWIR_TELEMETRY_TEMP_COUTS__RAW = str
LWIR_TELEMETRY_TEMP_KELVIN = int
LWIR_TELEMETRY_TEMP_KELVIN__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
LWIR_TELEMETRY_TEMP_LAST_KELVIN__TYPE = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
LWIR_TELEMETRY_TIME_LAST_MS = int
LWIR_TELEMETRY_TIME_LAST_MS__TYPE = str
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
LWIR_TELEMETRY_AGC_ROI_TOP = int
LWIR_TELEMETRY_AGC_ROI_TOP__TYPE = str
LWIR_TELEMETRY_AGC_ROI_TOP__RAW = str
LWIR_TELEMETRY_AGC_ROI_LEFT = int
LWIR_TELEMETRY_AGC_ROI_LEFT__TYPE = str
LWIR_TELEMETRY_AGC_ROI_LEFT__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__TYPE = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
LWIR_TELEMETRY_AGC_ROI_RIGHT = int
LWIR_TELEMETRY_AGC_ROI_RIGHT__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
LWIR_TELEMETRY_AGC_HIGH = int
LWIR_TELEMETRY_AGC_HIGH__TYPE = str
LWIR_TELEMETRY_AGC_HIGH__RAW = str
LWIR_TELEMETRY_AGC_LOW = int
LWIR_TELEMETRY_AGC_LOW__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
LWIR_TELEMETRY_VIDEO_FORMAT__RAW = str
LWIR_GPIO_IN = int
LWIR_GPIO_IN__TYPE = str
LWIR_GPIO_IN__RAW = str
SENSOR_IMAGE_TYPE0 = str
SENSOR_IMAGE_TYPE0__TYPE = str
SENSOR_IMAGE_TYPE0__RAW = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE1__TYPE = str
SENSOR_IMAGE_TYPE1__RAW = str
SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE2__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
SENSOR_IMAGE_TYPE3 = str
SENSOR_IMAGE_TYPE3__TYPE = str
SENSOR_IMAGE_TYPE3__RAW = str
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE0__TYPE = str
SIMULATE_CMPRS_CMODE0__RAW = str
SIMULATE_CMPRS_CMODE1 = int
SIMULATE_CMPRS_CMODE1__TYPE = str
SIMULATE_CMPRS_CMODE1__RAW = str
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE2__TYPE = str
SIMULATE_CMPRS_CMODE2__RAW = str
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE3__TYPE = str
SIMULATE_CMPRS_CMODE3__RAW = str
SENSOR12BITS_NGPL = int
SENSOR12BITS_NGPL__TYPE = str
SENSOR12BITS_NGPL__RAW = str
SENSOR12BITS_NVLO = int
SENSOR12BITS_NVLO__TYPE = str
SENSOR12BITS_NVLO__RAW = str
SENSOR12BITS_TMD = int
SENSOR12BITS_TMD__TYPE = str
SENSOR12BITS_TMD__RAW = str
SENSOR12BITS_TDDO = int
SENSOR12BITS_TDDO__TYPE = str
SENSOR12BITS_TDDO__RAW = str
SENSOR12BITS_TDDO1 = int
SENSOR12BITS_TDDO1__TYPE = str
SENSOR12BITS_TDDO1__RAW = str
HISTOGRAM_LEFT = int
HISTOGRAM_LEFT__TYPE = str
HISTOGRAM_LEFT__RAW = str
HISTOGRAM_TOP = int
HISTOGRAM_TOP__TYPE = str
HISTOGRAM_TOP__RAW = str
HISTOGRAM_WIDTH = int
HISTOGRAM_WIDTH__TYPE = str
HISTOGRAM_WIDTH__RAW = str
HISTOGRAM_HEIGHT = int
HISTOGRAM_HEIGHT__TYPE = str
HISTOGRAM_HEIGHT__RAW = str
HISTOGRAM_START_PAGE = int
HISTOGRAM_START_PAGE__TYPE = str
HISTOGRAM_START_PAGE__RAW = str
FRAME_WIDTH_ROUND_BITS = int
FRAME_WIDTH_ROUND_BITS__TYPE = str
FRAME_WIDTH_ROUND_BITS__RAW = str
WOI_WIDTH = int
WOI_WIDTH__TYPE = str
WOI_WIDTH__RAW = str
WOI_HEIGHT = int
WOI_HEIGHT__TYPE = str
WOI_HEIGHT__RAW = str
QUADRANTS_PXD_HACT_VACT = int
QUADRANTS_PXD_HACT_VACT__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
SENSOR_PRIORITY = int
SENSOR_PRIORITY__TYPE = str
SENSOR_PRIORITY__RAW = str
py393/vrlg_orig.py 0 → 100644
View file @ 043d4849
from __future__ import print_function
from __future__ import division
'''
# Copyright (C) 2015, Elphel.inc.
# Module to keep globals (Verilog parameters) accessible for all modules
# that import (not import from) this one
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
DEFAULTS={}
dqs_dqm_patt=None
def init_vars(d):
global DEFAULTS
if d:
globals().update(d)
for k,v in d.items():
DEFAULTS[k]=v
def set_name_field(vname,
fieldIndex,
value):
"""
Set specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
<value> value to set the specified byte to
"""
v=globals()[vname]
mask = 0xff << (8*fieldIndex)
val = value << (8*fieldIndex)
v = ((v ^ val) & mask) ^ v
globals()[vname]=v
def get_name_field(vname,
fieldIndex):
"""
Get specified byte in the parameter
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return ( globals()[vname] >> (8*fieldIndex)) & 0xff
def get_default_field(vname,
fieldIndex):
"""
Get specified byte in the parameter default value (read at program
start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
Return specified byte
"""
global DEFAULTS
# print ("value for %s is %s"%(vname,str(globals()[vname])))
# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))
return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
def get_default(vname):
"""
Get parameter default value (read at program start from Verilog parameters)
<vname> Verilog parameter name string (as listen in 'parameters')
Return specified parameter default
"""
global DEFAULTS
return DEFAULTS[vname]
def save_default(vname=None):
"""
Save parameter default value (replace read at program start from Verilog
parameters) using current parameter value
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname and vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
else:
for vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
def restore_default(vname=None):
"""
Restore parameter value from default
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname:
globals()[vname] = DEFAULTS[vname]
else:
for vname in DEFAULTS:
globals()[vname] = DEFAULTS[vname]
#### PyDev predefines
SS_EN__RAW = str
CLKIN_PERIOD_PCLK = int
SENSI2C_STATUS_REG_REL__TYPE = str
VOSPI_TELEMETRY__TYPE = str
SENSI2C_CMD_RUN_PBITS__RAW = str
XOR_HIST_BAYER__TYPE = str
HIST_SAXI_AWCACHE__RAW = str
CLK_STATUS_REG_ADDR__TYPE = str
MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
HIST_SAXI_ADDR_MASK = int
CONTROL_RBACK_ADDR_MASK = int
SENSOR_CHN_EN_BIT_SET__RAW = str
CMPRS_CBIT_QBANK__TYPE = str
LWIR_TELEMETRY_AGC_HIGH = int
CLKOUT_DIV_PCLK__RAW = str
SENS_GAMMA_CTRL__RAW = str
DFLT_INV_CLK_DIV__RAW = str
SENS_LENS_SCALES_MASK__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
LOGGER_ADDR__RAW = str
LWIR_MS_PERIOD = int
NUM_CYCLES_30__RAW = str
DLY_DQ_IDELAY__TYPE = str
VOSPI_SOF_TO_HACT = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
MCONTR_LINTILE_RST_FRAME = int
CMPRS_CBIT_CMODE_MONO6__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
SENSOR_FIFO_2DEPTH = int
HIGH_PERFORMANCE_MODE__TYPE = str
VOSPI_MCLK = int
PXD_CAPACITANCE__RAW = str
AFI_LO_ADDR64__TYPE = str
VOSPI_MRST_BITS = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
VOSPI_EN = int
AFI_SIZE64 = int
LOGGER_CONF_IMU_BITS = int
SENS_JTAG_TCK__RAW = str
HISPI_DIFF_TERM = str
MCONTR_PHY_0BIT_SDRST_ACT = int
SENSI2C_IBUF_LOW_PWR = str
CLKOUT_DIV_PCLK2X__RAW = str
CMPRS_JP4__TYPE = str
TABLE_CORING_INDEX = int
DQSTRI_LAST = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
STATUS_2LSB_SHFT__TYPE = str
MEMBRIDGE_LEN64__TYPE = str
SENSOR_TIMING_STATUS_REG_INC = int
HISTOGRAM_ADDR_MASK__RAW = str
LOGGER_CONF_EN__RAW = str
VOSPI_IBUF_LOW_PWR__RAW = str
LWIR_TELEMETRY_AGC_LOW__TYPE = str
HIST_CONFIRM_WRITE = int
CMPRS_GROUP_ADDR__TYPE = str
CMDFRAMESEQ_ADDR_INC = int
CAMSYNC_TRIG_PERIOD = int
CMPRS_CBIT_FRAMES_BITS = int
SENSOR_HIST_EN_BITS__TYPE = str
CMDSEQMUX_STATUS__TYPE = str
DFLT_DQS_PATTERN__TYPE = str
MCONTR_LINTILE_SINGLE = int
MCNTRL_TEST01_ADDR__RAW = str
SENS_GAMMA_MODE_PAGE__RAW = str
CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
SENSI2C_TBL_NBRD__TYPE = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
VOSPI_SLEW = str
CMPRS_CBIT_RUN_BITS__TYPE = str
SENSOR12BITS_TDDO1 = int
TILED_EXTRA_PAGES__RAW = str
MEMBRIDGE_CTRL_IRQ__RAW = str
CMPRS_NUM_AFI_CHN = int
CAMSYNC_TRIG_SRC__RAW = str
MEMCLK_CAPACITANCE = str
MULT_SAXI_ADV_RD__TYPE = str
SENSIO_WIDTH__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
CONTROL_RBACK_ADDR__RAW = str
CMPRS_AFIMUX_CYCBITS = int
VOSPI_OUT_EN__RAW = str
RTC_MHZ = int
VOSPI_PACKET_WORDS = int
SENS_LENS_C_MASK = int
MCONTR_PHY_16BIT_EXTRA = int
HIST_SAXI_EN__TYPE = str
VOSPI_SEGMENT_FIRST = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_LOAD__RAW = str
WINDOW_Y0__RAW = str
CMPRS_STATUS_CNTRL = int
SENSI2C_CMD_ACIVE_SDA__RAW = str
CLK_STATUS_REG_ADDR__RAW = str
CMPRS_CSAT_CB_BITS__TYPE = str
SENSI2C_SLEW__TYPE = str
MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
SENSOR_TIMING_LANE = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
RTC_SET_STATUS__TYPE = str
CMPRS_CBIT_QBANK_BITS__RAW = str
DEBUG_READ_REG_ADDR = int
WINDOW_HEIGHT = int
NUM_INTERRUPTS__TYPE = str
CAMSYNC_TRIG_DELAY0__RAW = str
MCONTR_SENS_STATUS_INC__RAW = str
SENSOR_HIST_NRST_BITS = int
SENSI2C_ABS_RADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str
VOSPI_MCLK_HALFDIV__RAW = str
SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str
DEBUG_ADDR__TYPE = str
CMPRS_CBIT_QBANK_BITS__TYPE = str
SENS_GAMMA_MODE_TRIG = int
RTC_SET_USEC = int
RTC_BITC_PREDIV__TYPE = str
SIMULATE_CMPRS_CMODE0__TYPE = str
LD_DLY_CMDA = int
DLY_SET__RAW = str
SENSI2C_CMD_TABLE = int
MCNTRL_PS_ADDR__RAW = str
WOI_WIDTH__TYPE = str
NUM_FRAME_BITS__RAW = str
SENSI2C_CMD_ACIVE__RAW = str
HISTOGRAM_TOP__RAW = str
LOGGER_CONF_GPS__TYPE = str
HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
VOSPI_PACKET_LAST__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN__RAW = str
LOGGER_CONF_SYN_BITS__TYPE = str
MULTICLK_DIVCLK__RAW = str
GPIO_ADDR__TYPE = str
CAMSYNC_TRIG_SRC = int
SENS_CTRL_GP1__RAW = str
CLKOUT_DIV_PCLK__TYPE = str
LOGGER_PAGE_IMU = int
MEMCLK_IOSTANDARD__RAW = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
MCONTR_LINTILE_LINEAR = int
VOSPI_VSYNC_BITS__TYPE = str
DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
NUM_CYCLES_30 = int
HISPI_DELAY_CLK0__TYPE = str
CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MEMCLK_PERIOD__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
LWIR_TELEMETRY_SREV__RAW = str
SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str
LWIR_TELEMETRY_AGC_HIGH__RAW = str
SENSI2C_CMD_SOFT_SCL = int
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
DEBUG_LOAD = int
CMPRS_JP4DIFF__TYPE = str
MULT_SAXI_CNTRL_IRQ__TYPE = str
LOGGER_CONF_DBG__RAW = str
FRAME_START_ADDRESS_INC__TYPE = str
DLY_DQS_IDELAY__TYPE = str
CLK_PHASE = float
MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
VOSPI_NO_INVALID__RAW = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
SENSOR12BITS_TMD__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS = int
MAX_TILE_HEIGHT = int
BUF_CLK1X_PCLK = str
LOGGER_CONF_DBG_BITS = int
SENS_CTRL_ARO__TYPE = str
SENS_LENS_SCALES_MASK__RAW = str
LWIR_WINDOW_HEIGHT__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
MCONTR_LINTILE_BYTE32__RAW = str
HISTOGRAM_WIDTH_HEIGHT = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM = int
MCONTR_RD_MASK__TYPE = str
MULT_SAXI_CNTRL_MASK = int
NUM_CYCLES_23__RAW = str
REF_JITTER1__RAW = str
CAMSYNC_MASK__TYPE = str
SENS_JTAG_PGMEN__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str
VOSPI_TELEMETRY_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
HISPI_DQS_BIAS__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
MEMCLK_PERIOD = float
BUF_IPCLK2X_SENS1__RAW = str
HISTOGRAM_WIDTH__RAW = str
SENS_LENS_FAT0_OUT_MASK = int
SENS_SYNC_MULT__TYPE = str
NUM_CYCLES_27__RAW = str
SENSI2C_IOSTANDARD__RAW = str
SCANLINE_EXTRA_PAGES__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
CMPRS_AFIMUX_MASK__TYPE = str
MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
SENSIO_STATUS = int
DFLT_DQS_PATTERN = int
MCONTR_BUF3_RD_ADDR__RAW = str
CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
SLEW_CLK = str
CMPRS_JP4DIFF = int
RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
TILED_EXTRA_PAGES__TYPE = str
FRAME_START_ADDRESS__TYPE = str
AXI_RDADDR_LATENCY = int
VOSPI_VSYNC__TYPE = str
AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int
CLK_CNTRL__RAW = str
MCONTR_LINTILE_EXTRAPG_BITS = int
MCONTR_LINTILE_RST_FRAME__TYPE = str
LAST_BUF_FRAME__RAW = str
FCLK1_PERIOD = float
CMPRS_AFIMUX_RADDR1__RAW = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
CMPRS_CBIT_DCSUB_BITS__RAW = str
SENS_CTRL_LD_DLY__RAW = str
HIST_SAXI_MODE_ADDR_REL__TYPE = str
MULT_SAXI_CNTRL_STATUS__RAW = str
CMPRS_CBIT_CMODE_JP46__TYPE = str
NUM_CYCLES_17__RAW = str
DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_24__RAW = str
VOSPI_SEGM0_OK__RAW = str
NUM_INTERRUPTS = int
NUM_CYCLES_13__RAW = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
VOSPI_PACKETS_PER_LINE = int
LAST_FRAME_BITS__RAW = str
VOSPI_MCLK__RAW = str
SENS_DIVCLK_DIVIDE = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str
GPIO_MASK = int
GPIO_STATUS_REG_ADDR = int
AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
DLY_DM_ODELAY__RAW = str
CMPRS_FRMT_MBRM1_BITS = int
CAMSYNC_EXTERNAL_BIT = int
CMPRS_STATUS_REG_BASE__TYPE = str
AFI_MUX_BUF_LATENCY__TYPE = str
SENSOR_CTRL_RADDR = int
FRAME_WIDTH_BITS__RAW = str
ADDRESS_NUMBER__RAW = str
STATUS_PSHIFTER_RDY_MASK__TYPE = str
SENSI2C_ADDR_MASK = int
LD_DLY_LANE1_IDELAY = int
SENS_SYNC_MASK = int
DIVCLK_DIVIDE = int
CMD_PAUSE_BITS__RAW = str
SENSI2C_TBL_DLY_BITS = int
IDELAY_VALUE__RAW = str
MULTICLK_PHASE_SYNC__TYPE = str
BUFFER_DEPTH32 = int
SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
DLY_DQS_ODELAY__TYPE = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
LWIR_TELEMETRY_TEMP_KELVIN__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
TEST01_START_FRAME = int
LWIR_DATA_FILE3 = str
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
LWIR_TELEMETRY_AGC_LOW = int
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_ADDR = int
MCONTR_PHY_0BIT_DCI_RST__RAW = str
REFCLK_FREQUENCY__RAW = str
VOSPI_TELEMETRY_BITS__RAW = str
LOGGER_BIT_HALF_PERIOD__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
DLY_DQ_ODELAY__TYPE = str
SENSOR_FIFO_2DEPTH__TYPE = str
NUM_CYCLES_28 = int
NUM_CYCLES_29 = int
NUM_CYCLES_26 = int
NUM_CYCLES_27 = int
NUM_CYCLES_24 = int
NUM_CYCLES_25 = int
NUM_CYCLES_22 = int
NUM_CYCLES_23 = int
NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str
HISPI_DELAY_CLK0 = str
MCNTRL_SCANLINE_DLY_WIDTH = int
MAX_TILE_WIDTH__RAW = str
PICKLE = str
AFI_SIZE64__TYPE = str
NUM_CYCLES_LOW_BIT__TYPE = str
MCONTR_PHY_0BIT_ADDR_MASK = int
SENSI2C_SLEW = str
VOSPI_DBG_SRC_BITS__RAW = str
DFLT_WBUF_DELAY__TYPE = str
MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
SENSI2C_STATUS_REG_INC__TYPE = str
MULT_SAXI_CNTRL_STATUS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
LOGGER_CONF_EN_BITS__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MAX_TILE_WIDTH__TYPE = str
SENS_LENS_FAT0_IN_MASK__TYPE = str
RSEL = int
LWIR_TELEMETRY_AGC_ROI_TOP__TYPE = str
TABLE_CORING_INDEX__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
VOSPI_NORESYNC = int
TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
HISPI_DELAY_CLK1__TYPE = str
NUM_CYCLES_14__TYPE = str
MCONTR_CMPRS_INC__TYPE = str
TILED_EXTRA_PAGES = int
DLY_DQS_ODELAY__RAW = str
CLKIN_PERIOD_PCLK__TYPE = str
FFCLK1_DIFF_TERM__RAW = str
SENS_JTAG_TDI__RAW = str
MCONTR_SENS_STATUS_BASE = int
AXI_WR_ADDR_BITS__RAW = str
SENSI2C_CMD_RUN__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
VOSPI_EN__RAW = str
CMPRS_CORING_MODE = int
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
SENSIO_STATUS__TYPE = str
GPIO_SLEW = str
LOGGER_CONF_SYN__TYPE = str
CAMSYNC_DELAY__RAW = str
LOGGER_CONF_DBG_BITS__RAW = str
FRAME_HEIGHT_BITS__RAW = str
MCONTR_LINTILE_KEEP_OPEN = int
SENS_SYNC_LATE__RAW = str
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = int
GPIO_PORTEN__RAW = str
LOGGER_BIT_DURATION__RAW = str
VOSPI_DBG_SRC_BITS = int
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str
VOSPI_TELEMETRY__RAW = str
TABLE_HUFFMAN_INDEX = int
VOSPI_HACT_TO_HACT_EOF__RAW = str
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_RAW__TYPE = str
HISPI_DELAY_CLK1__RAW = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
LOGGER_CONF_DBG = int
CAMSYNC_EN_BIT__TYPE = str
LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
FCLK0_PERIOD__RAW = str
VOSPI_SEGM0_OK_BITS__RAW = str
MCLK_PHASE__TYPE = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
MCONTR_BUF2_WR_ADDR__TYPE = str
GPIO_SLEW__TYPE = str
SENS_LENS_BX__RAW = str
DQTRI_LAST__TYPE = str
TEST_INITIAL_BURST = int
SENS_REF_JITTER1__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
CMPRS_CBIT_BE16 = int
SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
VOSPI_VSYNC_BITS__RAW = str
SENS_LENS_FAT0_IN_MASK__RAW = str
SENS_LENS_AY_MASK__RAW = str
SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
MCNTRL_TEST01_MASK = int
FFCLK1_DIFF_TERM = str
MULTICLK_PHASE_AXIHP__TYPE = str
FFCLK0_IOSTANDARD__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT__TYPE = str
WOI_WIDTH__RAW = str
STATUS_MSB_RSHFT = int
CMPRS_CONTROL_REG__RAW = str
CLKIN_PERIOD__TYPE = str
SENS_GAMMA_CTRL = int
HISPI_WAIT_ALL_LANES__TYPE = str
SENSIO_RADDR = int
VOSPI_NORESYNC_BITS__RAW = str
BUF_CLK1X_PCLK__RAW = str
LWIR_FRAME_DELAY = int
GPIO_N__TYPE = str
MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
LD_DLY_LANE0_ODELAY__TYPE = str
MCONTR_TOP_16BIT_ADDR__RAW = str
MCNTRL_SCANLINE_DLY_WIDTH__RAW = str
HIST_SAXI_MODE_ADDR_REL = int
MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
BUFFER_DEPTH32__TYPE = str
CMPRS_CBIT_CMODE_JPEG18 = int
MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
HISTOGRAM_RADDR0__TYPE = str
HISPI_FIFO_DEPTH__TYPE = str
LOGGER_CONF_SYN_BITS = int
MCONTR_CMPRS_BASE__RAW = str
NUM_CYCLES_19 = int
MULTICLK_DIV_XCLK2X = int
SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
LWIR_TELEMETRY__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
CMDFRAMESEQ_CTRL__TYPE = str
HISPI_FIFO_DEPTH__RAW = str
SENSOR_HIST_BITS_SET__RAW = str
NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int
SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str
HISTOGRAM_HEIGHT__TYPE = str
CMPRS_HIFREQ_REG_BASE__TYPE = str
FCLK0_PERIOD__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
LWIR_WINDOW_WIDTH__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = int
BUF_IPCLK_SENS1__TYPE = str
VOSPI_DRIVE = int
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
HISPI_IOSTANDARD__TYPE = str
CMPRS_AFIMUX_RST = int
NUM_CYCLES_18 = int
SENS_LENS_POST_SCALE_MASK__RAW = str
NUM_CYCLES_13 = int
CMPRS_FRMT_MBRM1__TYPE = str
VERBOSE__RAW = str
LOGGER_CONF_IMU_BITS__RAW = str
NUM_CYCLES_17 = int
NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
CMPRS_CSAT_CB__RAW = str
CMD_PAUSE_BITS = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
HISPI_IOSTANDARD__RAW = str
SENSI2C_TBL_SA__TYPE = str
BUF_IPCLK_SENS3__TYPE = str
MCNTRL_TILED_MODE = int
MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
CMPRS_COLOR20__TYPE = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
MCNTRL_SCANLINE_START_DELAY__TYPE = str
LOGGER_CONF_SYN = int
MCNTRL_TILED_CHN4_ADDR__RAW = str
MCONTR_CMPRS_STATUS_BASE = int
MCONTR_PHY_16BIT_PATTERNS__TYPE = str
MCONTR_PHY_0BIT_CKE_EN__RAW = str
NUM_CYCLES_26__TYPE = str
PICKLE__RAW = str
DQSTRI_LAST__RAW = str
WRITELEV_OFFSET__TYPE = str
CMPRS_BASE_INC = int
SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE1 = int
MULT_SAXI_BSLOG3__RAW = str
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
SENS_GAMMA_MODE_PAGE_SET__RAW = str
LWIR_DATA_FILE1__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
SENS_LENS_AX = int
MCONTR_PHY_16BIT_PATTERNS = int
SENSOR_CTRL_ADDR_MASK__TYPE = str
CMPRS_MONO16__RAW = str
RTC_ADDR = int
VOSPI_RESET_ERR__TYPE = str
SENSIO_RADDR__TYPE = str
CLKFBOUT_MULT_PCLK__TYPE = str
CLK_ADDR__TYPE = str
CMPRS_FORMAT = int
VOSPI_SEGM0_OK_BITS = int
SENSIO_STATUS_REG_REL = int
FFCLK1_CAPACITANCE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
CMPRS_TABLES = int
HIST_SAXI_MODE_WIDTH = int
CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
VOSPI_GPIO_BITS = int
SENS_REFCLK_FREQUENCY__TYPE = str
HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENS_CTRL_ODD__TYPE = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
MCNTRL_SCANLINE_START_DELAY__RAW = str
SIMULATE_CMPRS_CMODE2__TYPE = str
MCONTR_LINTILE_LINEAR__RAW = str
LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int
CMPRS_AFIMUX_SA_LEN__RAW = str
LOGGER_CONF_MSG = int
CMPRS_CSAT_CR__RAW = str
CMPRS_CBIT_RUN = int
SENS_LENS_ADDR_MASK__RAW = str
SENS_CTRL_QUADRANTS__RAW = str
SENSOR_TIMING_BITS__TYPE = str
RTC_MASK__RAW = str
SENS_LENS_ADDR_MASK__TYPE = str
SENS_LENS_AX__TYPE = str
PXD_DRIVE__TYPE = str
HIST_SAXI_NRESET = int
MULT_SAXI_HALF_BRAM_IN__RAW = str
HISTOGRAM_HEIGHT = int
SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
VOSPI_RST_SEQ__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
CLK_STATUS__TYPE = str
VOSPI_OUT_EN_BITS = int
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
SENS_CTRL_ODD__RAW = str
XOR_HIST_BAYER__RAW = str
DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW = str
CMPRS_CBIT_DCSUB__TYPE = str
DFLT_INV_CLK_DIV__TYPE = str
HISTOGRAM_RADDR_INC__RAW = str
MEMBRIDGE_WIDTH64__TYPE = str
SENS_GAMMA_MODE_BAYER__RAW = str
MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
CMPRS_CBIT_FOCUS_BITS__TYPE = str
STATUS_ADDR__RAW = str
NUM_CYCLES_30__TYPE = str
HISPI_MMCM1__TYPE = str
SDCLK_PHASE__RAW = str
SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
VOSPI_SEGM0_OK = int
VOSPI_RST_SEQ = int
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
VOSPI_MRST_BITS__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
NUM_CYCLES_09__RAW = str
VOSPI_SPI_SEQ = int
SENS_SYNC_LBITS__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int
HIST_SAXI_ADDR_REL__TYPE = str
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int
SENS_JTAG_TMS = int
MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
MCNTRL_PS_EN_RST__TYPE = str
BUF_CLK1X_PCLK2X__TYPE = str
MCNTRL_TILED_CHN4_ADDR = int
MULT_SAXI_POINTERS_REG__RAW = str
MCONTR_SENS_INC__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LOGGER_MASK__RAW = str
IBUF_LOW_PWR__RAW = str
DLY_CMDA_ODELAY__TYPE = str
VOSPI_SPI_CLK_BITS = int
SENS_LENS_FAT0_OUT_MASK__TYPE = str
LWIR_GPIO_IN__TYPE = str
SENSI2C_ABS_RADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
WBUF_DLY_WLV__TYPE = str
HISPI_MSB_FIRST__TYPE = str
MCONTR_TOP_16BIT_CHN_EN = int
LWIR_WINDOW_WIDTH__RAW = str
BUF_IPCLK2X_SENS1__TYPE = str
DEFAULT_STATUS_MODE = int
CMPRS_CBIT_CMODE_JPEG18__TYPE = str
MULT_SAXI_AWCACHE = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
VOSPI_EN_BITS = int
SENSI2C_TBL_RAH__RAW = str
CMPRS_CSAT_CR_BITS__TYPE = str
NUM_CYCLES_05 = int
NUM_CYCLES_06 = int
NUM_CYCLES_07 = int
NUM_CYCLES_00 = int
NUM_CYCLES_01 = int
NUM_CYCLES_02 = int
NUM_CYCLES_03 = int
SENSIO_ADDR_MASK__TYPE = str
NUM_CYCLES_08 = int
NUM_CYCLES_09 = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
SENS_SYNC_LBITS = int
STATUS_DEPTH__RAW = str
NUM_CYCLES_25__TYPE = str
MCONTR_LINTILE_REPEAT = int
CHNBUF_READ_LATENCY = int
SENS_CTRL_QUADRANTS_WIDTH = int
STATUS_PSHIFTER_RDY_MASK__RAW = str
WBUF_DLY_DFLT__RAW = str
SENS_GAMMA_MODE_BAYER__TYPE = str
MULT_SAXI_CNTRL_IRQ = int
TILE_WIDTH__TYPE = str
MCNTRL_TILED_FRAME_LAST__RAW = str
SENSI2C_CMD_RESET__RAW = str
REFRESH_OFFSET = int
MCNTRL_PS_EN_RST = int
MCONTR_SENS_BASE__RAW = str
SENS_GAMMA_ADDR_MASK__TYPE = str
CMPRS_CSAT_CR = int
CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
CMPRS_CSAT_CB = int
VOSPI_SEGMENT_LAST__TYPE = str
VERBOSE = int
DLY_LANE1_ODELAY = int
LOGGER_PERIOD__RAW = str
LWIR_TELEMETRY_STATUS__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
MCONTR_PHY_16BIT_EXTRA__RAW = str
SENS_SS_MOD_PERIOD__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
CMPRS_CBIT_CMODE_RAW__RAW = str
MEMBRIDGE_LEN64__RAW = str
LWIR_DATA_FILE2__TYPE = str
MCONTR_LINTILE_EN = int
DFLT_REFRESH_ADDR__RAW = str
GPIO_N = int
MCONTR_ARBIT_ADDR_MASK__TYPE = str
SENS_CTRL_MRST__TYPE = str
HISTOGRAM_RADDR_INC__TYPE = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP1 = int
FFCLK0_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_MINBITS__TYPE = str
LWIR_TELEMETRY_REV = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
SENS_GAMMA_RADDR = int
NUM_CYCLES_14__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
CLKIN_PERIOD_SENSOR__RAW = str
PHASE_WIDTH__TYPE = str
CMPRS_JP4__RAW = str
CMPRS_HIFREQ_REG_BASE__RAW = str
SS_MOD_PERIOD = int
MCONTR_CMPRS_BASE__TYPE = str
FFCLK1_IBUF_LOW_PWR = str
HISPI_CAPACITANCE__TYPE = str
MCONTR_LINTILE_KEEP_OPEN__TYPE = str
SENS_LENS_POST_SCALE = int
LOGGER_STATUS_REG_ADDR__TYPE = str
MEMBRIDGE_LO_ADDR64__TYPE = str
MCONTR_CMD_WR_ADDR__RAW = str
CMDFRAMESEQ_CTRL = int
DLY_LD__TYPE = str
MCNTRL_SCANLINE_STARTADDR__TYPE = str
SENS_JTAG_PROG__RAW = str
CMDFRAMESEQ_REL__RAW = str
CMPRS_AFIMUX_MASK = int
DLY_PHASE = int
CONTROL_RBACK_DEPTH__RAW = str
MCONTR_LINTILE_NRESET__RAW = str
MULT_SAXI_CNTRL_MODE = int
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MULT_SAXI_ADV_WR = int
MCNTRL_SCANLINE_MASK = int
MCONTR_LINTILE_LINEAR__TYPE = str
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
SENSOR12BITS_NGPL__RAW = str
CLKFBOUT_MULT__RAW = str
VOSPI_SEGMENT_FIRST__TYPE = str
CMPRS_STATUS_REG_INC__RAW = str
SENSOR_TIMING_STATUS_REG_INC__RAW = str
HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int
PXD_CAPACITANCE = str
SENS_LENS_AY = int
CMPRS_CBIT_CMODE_MONO6__TYPE = str
MULTICLK_BUF_XCLK__RAW = str
HISTOGRAM_RAM_MODE__RAW = str
SENS_LENS_AX_MASK__RAW = str
SENSI2C_TBL_SA_BITS = int
CMPRS_FRMT_MBCM1__TYPE = str
CMPRS_TIMEOUT__TYPE = str
MCLK_PHASE__RAW = str
NUM_CYCLES_10__TYPE = str
MCONTR_LINTILE_EXTRAPG__RAW = str
SENS_LENS_FAT0_IN__RAW = str
CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
LOGGER_CONFIG__RAW = str
LD_DLY_LANE0_ODELAY__RAW = str
PXD_CLK_DIV_BITS__RAW = str
CMPRS_FRMT_LMARG_BITS = int
CMDSEQMUX_ADDR = int
CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
SENS_GAMMA_MODE_PAGE_SET = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR = int
DLY_DQS_IDELAY__RAW = str
SENS_SYNC_RADDR = int
CONTROL_RBACK_ADDR_MASK__TYPE = str
MCONTR_BUF4_WR_ADDR = int
SENS_DIVCLK_DIVIDE__RAW = str
SENSOR_BASE_INC__RAW = str
VOSPI_PACKET_FIRST__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
HISTOGRAM_LEFT__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str
HIST_SAXI_MODE_WIDTH__TYPE = str
VOSPI_MRST_BITS__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
MEMBRIDGE_LEN64 = int
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
TILED_STARTX__RAW = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
SENSI2C_STATUS_REG_BASE__TYPE = str
DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
VOSPI_EN_BITS__TYPE = str
MULTICLK_PHASE_SYNC = float
SENSI2C_TBL_SA_BITS__RAW = str
HISPI_MMCM3__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
LWIR_DATA_FILE2__RAW = str
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
MCONTR_CMPRS_INC = int
CMPRS_CBIT_RUN_ENABLE__TYPE = str
LOGGER_CONF_IMU = int
DLY_DQS_IDELAY = int
HISTOGRAM_WIDTH_HEIGHT__TYPE = str
TEST01_NEXT_PAGE = int
MULTICLK_DIV_XCLK = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
PXD_IBUF_LOW_PWR = str
NUM_CYCLES_17__TYPE = str
SLEW_CLK__RAW = str
MCONTR_BUF2_WR_ADDR = int
SENS_LENS_FAT0_IN__TYPE = str
SENSIO_CTRL__TYPE = str
SENSIO_WIDTH__RAW = str
CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
CMPRS_CBIT_CMODE_RAW__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
VOSPI_VSYNC_BITS = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
CMPRS_CBIT_CMODE_RAW = int
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
T_RFC__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
MCONTR_LINTILE_NRESET__TYPE = str
PXD_CLK_DIV__RAW = str
SENS_NUM_SUBCHN__RAW = str
CMPRS_CBIT_RUN_ENABLE__RAW = str
AXI_RDADDR_LATENCY__TYPE = str
BUF_IPCLK_SENS3__RAW = str
CLK_STATUS__RAW = str
CMPRS_CBIT_ROWS_LSB__RAW = str
MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
SENS_CTRL_RST_MMCM = int
VOSPI_TELEMETRY_BITS = int
VOSPI_PACKET_LAST = int
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
SENSOR12BITS_TDDO1__RAW = str
HISPI_MMCM0__TYPE = str
TILE_WIDTH = int
CMPRS_CONTROL_REG = int
DLY_LANE0_ODELAY = int
NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
LWIR_DATA_FILE4 = str
LWIR_DATA_FILE1 = str
DLY_LANE0_ODELAY__RAW = str
LWIR_DATA_FILE2 = str
MCONTR_BUF3_WR_ADDR__TYPE = str
SCANLINE_STARTX__TYPE = str
SIMUL_AXI_READ_WIDTH = int
WRITE_BLOCK_OFFSET = int
FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str
LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
VOSPI_IBUF_LOW_PWR__TYPE = str
CMPRS_AFIMUX_MODE__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
SENSI2C_TBL_RAH_BITS = int
MULT_SAXI_CNTRL_IRQ__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
CHNBUF_READ_LATENCY__TYPE = str
CMPRS_CBIT_CMODE_BITS__TYPE = str
LOGGER_BIT_DURATION__TYPE = str
HISPI_MMCM1__RAW = str
MULT_SAXI_CNTRL_STATUS = int
TEST_INITIAL_BURST__TYPE = str
SENSOR12BITS_NVLO = int
LWIR_TELEMETRY_AGC_ROI_LEFT = int
NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str
CMPRS_CBIT_CMODE_JPEG20__TYPE = str
VOSPI_SPI_SEQ__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
MEMBRIDGE_LO_ADDR64__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
RTC_SET_USEC__TYPE = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
MULT_SAXI_CNTRL_ADDR = int
CMPRS_TIMEOUT_BITS__TYPE = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
WRITELEV_OFFSET = int
MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
MULT_SAXI_ADV_RD__RAW = str
SENS_GAMMA_MODE_EN_SET__RAW = str
SENS_GAMMA_MODE_BAYER_SET__TYPE = str
T_RFC__RAW = str
VOSPI_IOSTANDARD__RAW = str
WBUF_DLY_DFLT__TYPE = str
HISPI_DELAY_CLK0__RAW = str
PXD_SLEW__TYPE = str
FRAME_START_ADDRESS = int
DEBUG_SET_STATUS__RAW = str
MCONTR_RD_MASK__RAW = str
LOGGER_CONF_EN = int
FFCLK0_CAPACITANCE = str
MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
VOSPI_IBUF_LOW_PWR = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
LOGGER_MASK = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
CMPRS_GROUP_ADDR = int
CAMSYNC_PRE_MAGIC__RAW = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
LD_DLY_LANE0_ODELAY = int
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
LWIR_FRAME_DELAY__TYPE = str
MULTICLK_DIV_XCLK2X__TYPE = str
MEMBRIDGE_SIZE64 = int
SENSOR_IMAGE_TYPE1__RAW = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
CMPRS_FRMT_MBCM1_BITS = int
SENS_GAMMA_MODE_REPET_SET__TYPE = str
HISTOGRAM_RAM_MODE__TYPE = str
AFI_LO_ADDR64 = int
HISTOGRAM_RADDR_INC = int
VOSPI_PACKETS_PER_LINE__TYPE = str
NUM_CYCLES_07__TYPE = str
SENS_LENS_FAT0_IN = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
SENSOR12BITS_NGPL__TYPE = str
HISTOGRAM_RADDR1__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MULTICLK_DIV_DLYREF__RAW = str
VERBOSE__TYPE = str
BUF_CLK1X_PCLK__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
LWIR_TELEMETRY_STATUS = int
CAMSYNC_TRIG_DELAY0__TYPE = str
LWIR_DATA_FILE3__RAW = str
SENSI2C_STATUS_REG_INC = int
CLKFBOUT_PHASE__TYPE = str
TABLE_QUANTIZATION_INDEX__RAW = str
MCNTRL_TILED_WINDOW_WH = int
CMDFRAMESEQ_MASK = int
CLK_ADDR = int
MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MULTICLK_PHASE_FB = float
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM__TYPE = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
SENS_GAMMA_RADDR__RAW = str
SENS_CTRL_EXT_CLK = int
MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
SENS_GAMMA_BUFFER = int
GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP46__RAW = str
MULTICLK_DIV_SYNC__TYPE = str
LWIR_WINDOW_HEIGHT__RAW = str
MULTICLK_BUF_DLYREF__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_IBUF_LOW_PWR__TYPE = str
SENS_SYNC_FBITS__RAW = str
CMPRS_CORING_MODE__TYPE = str
CMPRS_FRMT_MBRM1_BITS__TYPE = str
MCNTRL_TILED_TILE_WHS__RAW = str
SENS_REFCLK_FREQUENCY = float
CMD_PAUSE_BITS__TYPE = str
SENS_CTRL_EXT_CLK__TYPE = str
SENS_LENS_BY = int
SENS_LENS_BX = int
NUM_CYCLES_02__TYPE = str
MCNTRL_TILED_STARTADDR = int
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
TILE_HEIGHT__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
VOSPI_DBG_SRC = int
MCNTRL_TILED_CHN4_ADDR__TYPE = str
HISPI_NUMLANES__TYPE = str
VOSPI_DBG_SRC__RAW = str
HISPI_FIFO_START = int
TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
MCONTR_TOP_STATUS_REG_ADDR = int
SENSOR_TIMING_TO = int
VOSPI_SEGM0_OK__TYPE = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
CMPRS_STATUS_REG_BASE__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
TEST01_NEXT_PAGE__TYPE = str
CONTROL_RBACK_ADDR = int
T_REFI__RAW = str
MULTICLK_PHASE_SYNC__RAW = str
CLKFBOUT_MULT_SENSOR = int
HISPI_MMCM2__RAW = str
CMPRS_AFIMUX_EN = int
COLADDR_NUMBER = int
MCNTRL_PS_CMD = int
VOSPI_OUT_EN_SINGL = int
LWIR_TELEMETRY_SREV__TYPE = str
TABLE_FOCUS_INDEX__TYPE = str
CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
SENSI2C_CMD_USE_EOF__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
VOSPI_MRST_MS = int
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str
MULTICLK_DIV_XCLK__RAW = str
DFLT_DQS_TRI_ON_PATTERN__TYPE = str
MCONTR_PHY_0BIT_DLY_RST__TYPE = str
TILED_KEEP_OPEN__RAW = str
AXI_WRADDR_LATENCY__TYPE = str
MULT_SAXI_IRQLEN_ADDR = int
XOR_HIST_BAYER = int
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
VOSPI_VSYNC__RAW = str
CLKFBOUT_PHASE_SENSOR__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
MCONTR_SENS_BASE = int
CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
MCNTRL_SCANLINE_FRAME_SIZE = int
STATUS_DEPTH = int
NUM_CYCLES_20__RAW = str
MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
VOSPI_IOSTANDARD = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
VOSPI_SLEW__RAW = str
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
VOSPI_OUT_EN_SINGL__TYPE = str
SENSOR_TIMING_START__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
PXD_CLK_DIV_BITS__TYPE = str
MCONTR_CMPRS_INC__RAW = str
CMPRS_HIFREQ_REG_INC__RAW = str
PXD_CLK_DIV__TYPE = str
SENSOR_DATA_WIDTH__RAW = str
SENSI2C_TBL_DLY_BITS__TYPE = str
MEMBRIDGE_MASK = int
SENSI2C_TBL_NBWR_BITS__TYPE = str
DLY_SET__TYPE = str
CMPRS_STATUS_REG_INC = int
FFCLK0_CAPACITANCE__TYPE = str
LAST_FRAME_BITS__TYPE = str
CLK_MASK__RAW = str
DLY_DM_ODELAY = int
MEMBRIDGE_STATUS_CNTRL__RAW = str
VOSPI_SPI_CLK__TYPE = str
DEBUG_SHIFT_DATA = int
LWIR_DATA_FILE4__TYPE = str
MEMBRIDGE_STATUS_REG = int
CMPRS_CBIT_CMODE_JPEG18__RAW = str
IPCLK2X_PHASE = float
VOSPI_OUT_EN_BITS__RAW = str
CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int
SENSI2C_CMD_USE_EOF__RAW = str
SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
WSEL__TYPE = str
CMPRS_AFIMUX_CYCBITS__RAW = str
MAX_TILE_WIDTH = int
NUM_CYCLES_09__TYPE = str
LD_DLY_LANE0_IDELAY__RAW = str
FRAME_WIDTH_BITS__TYPE = str
SENS_SYNC_LBITS__TYPE = str
NUM_CYCLES_25__RAW = str
SENSOR_NUM_HISTOGRAM__RAW = str
CMPRS_CBIT_CMODE = int
HIST_SAXI_ADDR_MASK__RAW = str
HISPI_WAIT_ALL_LANES__RAW = str
MEMBRIDGE_STATUS_REG__TYPE = str
CLKIN_PERIOD__RAW = str
SENS_SYNC_MULT__RAW = str
SENSOR_TIMING_STATUS_REG_BASE = int
SENSOR_HIST_NRST_BITS__RAW = str
SENS_LENS_BY__TYPE = str
NUM_CYCLES_02__RAW = str
CAMSYNC_GPIO_INT_IN = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
VOSPI_MCLK_BITS__RAW = str
MCNTRL_TILED_WINDOW_X0Y0 = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MULT_SAXI_WLOG__TYPE = str
STATUS_2LSB_SHFT = int
HISPI_IFD_DELAY_VALUE = str
CMPRS_CBIT_CMODE_JP4DC = int
MULT_SAXI_IRQLEN_MASK = int
NUM_CYCLES_08__TYPE = str
NUM_CYCLES_LOW_BIT__RAW = str
SENSI2C_TBL_NBRD_BITS__TYPE = str
SENS_SYNC_MINBITS = int
MULTICLK_BUF_DLYREF = str
MCNTRL_SCANLINE_WINDOW_STARTXY = int
BUF_IPCLK_SENS2__RAW = str
CMPRS_STATUS_CNTRL__TYPE = str
MCONTR_RD_MASK = int
CMPRS_COLOR_SATURATION = int
NUM_CYCLES_21__RAW = str
MULTICLK_PHASE_DLYREF__RAW = str
SENSIO_DELAYS__RAW = str
CMDFRAMESEQ_RUN_BIT = int
SENS_SYNC_MINPER = int
CMPRS_FRMT_MBRM1__RAW = str
MCONTR_SENS_BASE__TYPE = str
LOGGER_BIT_HALF_PERIOD = int
CMPRS_CBIT_CMODE_JP4 = int
VOSPI_DRIVE__RAW = str
CAMSYNC_TRIGGERED_BIT = int
VOSPI_SPI_CLK_BITS__RAW = str
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_GPS__RAW = str
SENS_PHASE_WIDTH__TYPE = str
CMPRS_COLOR18__TYPE = str
CMPRS_HIFREQ_REG_INC__TYPE = str
VOSPI_OUT_EN = int
PXD_CLK_DIV = int
MCNTRL_TILED_STATUS_CNTRL = int
NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
CMPRS_RAW__RAW = str
FFCLK0_CAPACITANCE__RAW = str
SENSOR12BITS_TDDO1__TYPE = str
CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
CAMSYNC_GPIO_EXT_OUT__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
MCONTR_LINTILE_EN__RAW = str
SENSI2C_ADDR_MASK__TYPE = str
SENSOR12BITS_NVLO__RAW = str
CAMSYNC_EXTERNAL_BIT__TYPE = str
CMPRS_BASE_INC__RAW = str
SENS_SYNC_FBITS = int
BUF_IPCLK_SENS0__RAW = str
MCNTRL_TEST01_ADDR = int
MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
VOSPI_SLEW__TYPE = str
GPIO_SET_PINS = int
FRAME_START_ADDRESS__RAW = str
LOGGER_BIT_DURATION = int
FCLK1_PERIOD__TYPE = str
CAMSYNC_MODE__TYPE = str
CHNBUF_READ_LATENCY__RAW = str
NUM_CYCLES_12__RAW = str
CMPRS_CBIT_RUN_BITS__RAW = str
CMPRS_AFIMUX_RST__TYPE = str
LD_DLY_PHASE = int
SENSI2C_CTRL_RADDR__TYPE = str
SENSIO_ADDR_MASK__RAW = str
LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
CLK_CNTRL__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
SENSOR_TIMING_LANE__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
SENS_BANDWIDTH__RAW = str
CMPRS_CBIT_BE16_BITS__TYPE = str
SENS_SS_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
LOGGER_STATUS_MASK__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
MULT_SAXI_IRQLEN_MASK__RAW = str
MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
SENSOR12BITS_NGPL = int
CMDFRAMESEQ_REL = int
CAMSYNC_POST_MAGIC__TYPE = str
NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE = str
CAMSYNC_ADDR = int
FFCLK1_CAPACITANCE__RAW = str
VOSPI_SPI_SEQ__RAW = str
VOSPI_PACKET_LAST__RAW = str
RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
CLK_STATUS = int
SENSI2C_STATUS_REG_INC__RAW = str
GPIO_ADDR__RAW = str
MEMBRIDGE_START64__TYPE = str
CMPRS_CBIT_CMODE_JP46 = int
MEMCLK_CAPACITANCE__TYPE = str
MCONTR_BUF0_WR_ADDR__RAW = str
HISTOGRAM_TOP = int
SENS_SS_MODE = str
SENSOR12BITS_TDDO = int
CAMSYNC_TRIG_DST = int
DLY_LANE1_ODELAY__TYPE = str
CMPRS_AFIMUX_WIDTH__TYPE = str
TILE_VSTEP__RAW = str
CMPRS_CBIT_QBANK = int
SENSI2C_TBL_RAH_BITS__TYPE = str
LWIR_WINDOW_WIDTH = int
CMPRS_AFIMUX_WIDTH = int
HISTOGRAM_ADDR_MASK__TYPE = str
HISTOGRAM_RADDR3__TYPE = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSOR_TIMING_START = int
SENSOR_NUM_HISTOGRAM = int
HIST_SAXI_NRESET__RAW = str
CMPRS_COLOR18 = int
LOGGER_CONF_MSG__TYPE = str
MCNTRL_TILED_MASK__RAW = str
MULTICLK_DIV_AXIHP__RAW = str
SENSI2C_CMD_SOFT_SDA__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
SENSI2C_STATUS_REG_BASE = int
MCNTRL_TILED_STATUS_CNTRL__RAW = str
CMPRS_CBIT_BAYER__RAW = str
DFLT_DQS_TRI_OFF_PATTERN = int
SENSIO_JTAG__TYPE = str
VOSPI_NORESYNC__RAW = str
SENSOR_GROUP_ADDR__RAW = str
LOGGER_MASK__TYPE = str
T_RFC = int
FFCLK1_IOSTANDARD__RAW = str
CMD_DONE_BIT__TYPE = str
SENSOR_DATA_WIDTH__TYPE = str
VOSPI_RESET_ERR__RAW = str
RTC_BITC_PREDIV__RAW = str
CMPRS_CORING_BITS__TYPE = str
STATUS_DEPTH__TYPE = str
SENSI2C_TBL_RAH__TYPE = str
CMPRS_AFIMUX_CYCBITS__TYPE = str
HISPI_MSB_FIRST = int
SENS_SS_EN__RAW = str
SENS_LENS_ADDR_MASK = int
SENSOR_CTRL_RADDR__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
VOSPI_PACKETS_PER_LINE__RAW = str
CLKOUT_DIV_PCLK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
PXD_IOSTANDARD__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR = int
LAST_BUF_FRAME = int
SENS_REF_JITTER1 = float
SENS_REF_JITTER2 = float
MCNTRL_TILED_FRAME_SIZE__RAW = str
VOSPI_MRST_AFTER_MS = int
MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
LWIR_MS_PERIOD__RAW = str
SLEW_DQ = str
CAMSYNC_GPIO_INT_OUT__TYPE = str
SENS_GAMMA_MODE_REPET__RAW = str
SENSOR_DATA_WIDTH = int
SENSOR_TIMING_LANE__RAW = str
SLEW_DQS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT = int
VOSPI_SEGMENT_LAST__RAW = str
SENSIO_ADDR_MASK = int
TILE_HEIGHT__RAW = str
SCANLINE_STARTY = int
SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str
GPIO_DRIVE__TYPE = str
FFCLK0_DIFF_TERM__TYPE = str
HISPI_UNTUNED_SPLIT__TYPE = str
LD_DLY_CMDA__TYPE = str
MCONTR_TOP_0BIT_REFRESH_EN = int
CMPRS_CBIT_RUN_RST = int
IPCLK2X_PHASE__RAW = str
VOSPI_NORESYNC_BITS__TYPE = str
SENSI2C_IOSTANDARD__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
REFCLK_FREQUENCY__TYPE = str
CLKOUT_DIV_PCLK2X__TYPE = str
MEMBRIDGE_CTRL = int
SENSOR_IMAGE_TYPE3__TYPE = str
HISTOGRAM_LEFT = int
MULT_SAXI_HALF_BRAM__TYPE = str
VOSPI_EN_BITS__RAW = str
MCONTR_PHY_STATUS_CNTRL = int
SENSOR_GROUP_ADDR = int
NUM_CYCLES_14 = int
CMPRS_CBIT_RUN_STANDALONE__TYPE = str
BUF_IPCLK_SENS1__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
VOSPI_NO_INVALID__TYPE = str
VOSPI_DRIVE__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
MCNTRL_SCANLINE_STARTADDR = int
CONTROL_ADDR = int
DQSTRI_FIRST__TYPE = str
MULT_SAXI_HALF_BRAM_IN__TYPE = str
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
LWIR_DATA_FILE1__TYPE = str
MCNTRL_TILED_STARTADDR__RAW = str
WINDOW_X0__RAW = str
VOSPI_EN__TYPE = str
LWIR_FRAME_PERIOD__RAW = str
CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
WINDOW_Y0 = int
LOGGER_CONF_GPS_BITS__TYPE = str
CAMSYNC_GPIO_EXT_IN__TYPE = str
SENS_LENS_AX_MASK__TYPE = str
HISTOGRAM_RADDR0 = int
HISTOGRAM_RADDR1 = int
HISTOGRAM_RADDR2 = int
HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
HISTOGRAM_LEFT__TYPE = str
SENS_LENS_AY_MASK__TYPE = str
VOSPI_PACKET_TTT__RAW = str
VOSPI_MRST__RAW = str
SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str
CONTROL_ADDR_MASK__RAW = str
LD_DLY_CMDA__RAW = str
SENSI2C_STATUS_REG_REL__RAW = str
NUM_CYCLES_18__TYPE = str
MCNTRL_TEST01_CHN2_MODE = int
MCNTRL_TILED_WINDOW_WH__TYPE = str
SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
SENSOR_IMAGE_TYPE3 = str
MULTICLK_DIV_AXIHP__TYPE = str
LWIR_FRAME_PERIOD__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
WSEL__RAW = str
SENSOR_PRIORITY = int
DLY_PHASE__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
VOSPI_VSYNC = int
MCNTRL_TEST01_CHN1_MODE__RAW = str
SLEW_CMDA__TYPE = str
MULT_SAXI_CNTRL_MODE__TYPE = str
NUM_CYCLES_19__TYPE = str
CMPRS_CORING_MODE__RAW = str
MEMBRIDGE_ADDR = int
CMPRS_CSAT_CR_BITS__RAW = str
MULTICLK_IN_PERIOD__RAW = str
CMPRS_CBIT_FOCUS = int
FFCLK1_CAPACITANCE__TYPE = str
SENSOR_FIFO_DELAY = int
MULTICLK_PHASE_AXIHP = float
MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
WBUF_DLY_DFLT = int
SENS_JTAG_PROG = int
MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
FFCLK0_IOSTANDARD = str
AXI_TASK_HOLD__TYPE = str
SENS_GAMMA_ADDR_MASK__RAW = str
SENSOR_IMAGE_TYPE3__RAW = str
DLY_LANE1_IDELAY__TYPE = str
SENS_LENS_BY_MASK = int
DEBUG_MASK__RAW = str
VOSPI_NORESYNC__TYPE = str
NUM_INTERRUPTS__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MEMBRIDGE_ADDR__RAW = str
LWIR_GPIO_IN = int
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
MULTICLK_IN_PERIOD__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
VOSPI_GPIO__TYPE = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
RTC_SEC_USEC_ADDR__TYPE = str
WINDOW_X0__TYPE = str
CMPRS_CBIT_QBANK_BITS = int
MCNTRL_TEST01_CHN1_MODE = int
DLY_CMDA = int
SENS_GAMMA_MODE_BAYER = int
LAST_BUF_FRAME__TYPE = str
CMPRS_HIFREQ_REG_BASE = int
FCLK1_PERIOD__RAW = str
MCONTR_ARBIT_ADDR = int
MEMBRIDGE_CTRL__RAW = str
CMPRS_CBIT_RUN_RST__RAW = str
TABLE_QUANTIZATION_INDEX = int
NUM_CYCLES_04__TYPE = str
SENSOR_IMAGE_TYPE2 = str
SENSOR_IMAGE_TYPE1 = str
SENSOR_IMAGE_TYPE0 = str
SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
NUM_CYCLES_00__TYPE = str
VOSPI_MCLK_HALFDIV = int
CMPRS_MASK__RAW = str
MEMBRIDGE_CTRL_IRQ__TYPE = str
MCNTRL_TEST01_MASK__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK = int
CAMSYNC_TRIG_DELAY1__TYPE = str
HIGH_PERFORMANCE_MODE = str
DQTRI_LAST__RAW = str
MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
SIMULATE_CMPRS_CMODE3__TYPE = str
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CMPRS_CBIT_BE16_BITS = int
AXI_WRDATA_LATENCY__RAW = str
LWIR_FRAME_PERIOD = int
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
MCONTR_PHY_16BIT_EXTRA__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
VOSPI_NO_INVALID = int
SENSI2C_CMD_SOFT_SCL__RAW = str
CMPRS_CSAT_CR__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
DLY_LANE1_IDELAY = int
HIST_SAXI_NRESET__TYPE = str
MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
CMPRS_AFIMUX_SA_LEN__TYPE = str
SENS_LENS_SCALES__RAW = str
MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
DLY_LANE0_ODELAY__TYPE = str
SENS_LENS_FAT0_IN_MASK = int
CMPRS_CBIT_CMODE_JP4__TYPE = str
LOGGER_CONF_GPS = int
MULT_SAXI_AWCACHE__RAW = str
MCONTR_PHY_0BIT_CKE_EN = int
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_CBIT_FRAMES__RAW = str
SLEW_DQS = str
MCONTR_WR_MASK = int
MCONTR_LINTILE_ABORT_LATE = int
CMPRS_FRMT_MBCM1 = int
MEMBRIDGE_STATUS_CNTRL__TYPE = str
GPIO_IOSTANDARD__TYPE = str
CLKFBOUT_USE_FINE_PS__TYPE = str
CMPRS_FRMT_LMARG = int
CMPRS_AFIMUX_EN__RAW = str
CMPRS_TIMEOUT__RAW = str
MEMCLK_IBUF_LOW_PWR__RAW = str
SENS_LENS_FAT0_OUT_MASK__RAW = str
SENSI2C_CMD_FIFO_RD__RAW = str
RTC_ADDR__TYPE = str
MCONTR_LINTILE_COPY_FRAME__RAW = str
SENSI2C_ABS_RADDR = int
PXD_IOSTANDARD__RAW = str
CMPRS_CBIT_FRAMES = int
SENS_GAMMA_HEIGHT01__RAW = str
CONTROL_RBACK_DEPTH__TYPE = str
CMPRS_CBIT_CMODE_MONO1__RAW = str
MCNTRL_SCANLINE_DLY_DEFAULT__RAW = str
GPIO_PORTEN__TYPE = str
CMDSEQMUX_ADDR__RAW = str
DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
LWIR_TELEMETRY_TEMP_COUTS = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
SENS_SS_MOD_PERIOD__RAW = str
SENSOR_TIMING_TO__RAW = str
COLADDR_NUMBER__TYPE = str
SENSOR_TIMING_FROM = int
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
MULT_SAXI_IRQLEN_ADDR__TYPE = str
MULT_SAXI_IRQLEN_MASK__TYPE = str
PICKLE__TYPE = str
SENSI2C_TBL_NBWR__RAW = str
TABLE_FOCUS_INDEX__RAW = str
MCONTR_LINTILE_WRITE__RAW = str
MCNTRL_TILED_CHN2_ADDR__RAW = str
CMPRS_CONTROL_REG__TYPE = str
SENS_CTRL_ARST__TYPE = str
CMPRS_CBIT_FOCUS__RAW = str
CMPRS_MONO8__TYPE = str
NUM_CYCLES_00__RAW = str
IPCLK_PHASE__RAW = str
SENSI2C_CTRL = int
SENS_SYNC_MULT = int
CLK_ADDR__RAW = str
SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
VOSPI_GPIO = int
CMPRS_CBIT_BE16__TYPE = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = int
MULTICLK_PHASE_DLYREF = float
HIST_SAXI_ADDR_REL = int
CMDFRAMESEQ_ADDR_BASE = int
STATUS_SEQ_SHFT__RAW = str
SENS_SS_MODE__TYPE = str
CMPRS_AFIMUX_RADDR0 = int
CMPRS_FRMT_MBCM1_BITS__RAW = str
CMPRS_AFIMUX_REG_ADDR1__TYPE = str
CMPRS_CBIT_FRAMES__TYPE = str
MCONTR_TOP_0BIT_ADDR = int
NUM_CYCLES_05__RAW = str
MCNTRL_TILED_FRAME_LAST__TYPE = str
QUADRANTS_PXD_HACT_VACT__RAW = str
CMPRS_CBIT_ROWS_LSB_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str
MCONTR_LINTILE_ABORT_LATE__TYPE = str
SENSI2C_CMD_RESET__TYPE = str
LWIR_DATA_FILE4__RAW = str
VOSPI_NORESYNC_BITS = int
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
AXI_TASK_HOLD = float
CMPRS_CBIT_ROWS_LSB__TYPE = str
ADDRESS_NUMBER = int
CAMSYNC_GPIO_EXT_OUT = int
SENSOR_TIMING_FROM__RAW = str
SENS_SYNC_LATE__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
GPIO_STATUS_REG_ADDR__TYPE = str
HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS = int
CMPRS_MONO8__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_BANDWIDTH__TYPE = str
LD_DLY_LANE0_IDELAY__TYPE = str
CLKFBOUT_PHASE__RAW = str
NUM_CYCLES_08__RAW = str
GPIO_IBUF_LOW_PWR__RAW = str
HISTOGRAM_RADDR3__RAW = str
NUM_XFER_BITS__TYPE = str
LWIR_GPIO_IN__RAW = str
TABLE_QUANTIZATION_INDEX__TYPE = str
BUF_IPCLK2X_SENS2__RAW = str
MCNTRL_TEST01_CHN4_MODE__TYPE = str
MULT_SAXI_ADDR__TYPE = str
CMPRS_CBIT_DCSUB__RAW = str
SENS_LENS_AY__TYPE = str
CMPRS_CBIT_CMODE_JP46DC = int
CAMSYNC_MODE__RAW = str
REFCLK_FREQUENCY = float
STATUS_ADDR_MASK__RAW = str
CMPRS_AFIMUX_MODE = int
DLY_CMDA__RAW = str
BUFFER_DEPTH32__RAW = str
LWIR_TELEMETRY_REV__RAW = str
DIVCLK_DIVIDE__RAW = str
MCNTRL_PS_CMD__RAW = str
VOSPI_PACKET_WORDS__RAW = str
CAMSYNC_ADDR__RAW = str
MCONTR_BUF3_WR_ADDR = int
SENS_NUM_SUBCHN__TYPE = str
REFRESH_OFFSET__RAW = str
HISPI_MMCM0 = str
HISPI_MMCM3 = str
HISPI_MMCM2 = str
MULT_SAXI_CNTRL_ADDR__TYPE = str
HISPI_KEEP_IRST__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
CAMSYNC_GPIO_EXT_IN = int
MEMCLK_IOSTANDARD__TYPE = str
NUM_CYCLES_27__TYPE = str
SENSI2C_TBL_NBRD = int
CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
CAMSYNC_GPIO_INT_OUT = int
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
QUADRANTS_PXD_HACT_VACT__TYPE = str
SENS_GAMMA_MODE_BAYER_SET__RAW = str
SENSOR_PRIORITY__TYPE = str
SENS_LENS_BY__RAW = str
MCNTRL_PS_CMD__TYPE = str
SENS_SYNC_MASK__RAW = str
MEMBRIDGE_START64__RAW = str
SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
SENSI2C_DRIVE = int
NUM_CYCLES_04__RAW = str
SENS_GAMMA_HEIGHT2__RAW = str
MULT_SAXI_POINTERS_REG__TYPE = str
HISPI_DELAY_CLK1 = str
HISPI_DELAY_CLK2 = str
HISPI_DELAY_CLK3 = str
MULT_SAXI_BSLOG0__TYPE = str
DQTRI_FIRST__RAW = str
DIVCLK_DIVIDE__TYPE = str
WBUF_DLY_WLV = int
MCONTR_BUF3_WR_ADDR__RAW = str
MEMBRIDGE_WIDTH64 = int
MCNTRL_TEST01_CHN3_MODE = int
MULTICLK_DIV_DLYREF = int
TABLE_HUFFMAN_INDEX__RAW = str
LD_DLY_PHASE__RAW = str
TEST_INITIAL_BURST__RAW = str
SENSOR_TIMING_FROM__TYPE = str
CMPRS_CBIT_FRAMES_BITS__TYPE = str
CMPRS_FRMT_MBCM1__RAW = str
FFCLK0_DIFF_TERM = str
DIVCLK_DIVIDE_PCLK__TYPE = str
HISPI_FIFO_START__TYPE = str
SENSOR_HIST_EN_BITS = int
DFLT_DQS_TRI_OFF_PATTERN__RAW = str
CMPRS_FRMT_MBRM1 = int
CAMSYNC_SNDEN_BIT__RAW = str
MCONTR_ARBIT_ADDR_MASK__RAW = str
VOSPI_SEGMENT_LAST = int
WINDOW_WIDTH__TYPE = str
MCONTR_CMPRS_STATUS_INC__TYPE = str
DFLT_INV_CLK_DIV = int
DEFAULT_STATUS_MODE__TYPE = str
HISTOGRAM_LEFT_TOP = int
PHASE_CLK2X_PCLK = float
GPIO_SLEW__RAW = str
MULTICLK_PHASE_DLYREF__TYPE = str
TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
FRAME_WIDTH_ROUND_BITS__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str
VOSPI_SPI_CLK_BITS__TYPE = str
MCONTR_BUF4_WR_ADDR__RAW = str
DFLT_DQM_PATTERN__RAW = str
CMPRS_CSAT_CB__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
RTC_MASK = int
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
MCONTR_LINTILE_RST_FRAME__RAW = str
LOGGER_CONFIG__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT = int
LWIR_TELEMETRY_AGC_ROI_TOP = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
LWIR_TELEMETRY_AGC_ROI_TOP__RAW = str
SENSOR12BITS_NVLO__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
SENSOR_16BIT_BIT_SET__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
SLEW_DQS__RAW = str
FRAME_HEIGHT_BITS__TYPE = str
CMPRS_CBIT_BAYER__TYPE = str
MCONTR_PHY_0BIT_ADDR = int
AXI_WRADDR_LATENCY = int
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MAX_TILE_HEIGHT__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
HISTOGRAM_WIDTH_HEIGHT__RAW = str
WRITELEV_OFFSET__RAW = str
READ_PATTERN_OFFSET = int
CLK_PHASE__TYPE = str
SENSOR_16BIT_BIT = int
MCNTRL_PS_STATUS_REG_ADDR = int
SENS_CTRL_EXT_CLK__RAW = str
SENSOR_CHN_EN_BIT_SET = int
WOI_HEIGHT = int
LOGGER_PAGE_GPS__TYPE = str
T_REFI = int
HIST_CONFIRM_WRITE__TYPE = str
HISTOGRAM_LEFT_TOP__RAW = str
MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
LOGGER_STATUS_REG_ADDR = int
CMDSEQMUX_ADDR__TYPE = str
DEBUG_STATUS_REG_ADDR = int
SENS_JTAG_TDI__TYPE = str
SENS_GAMMA_MODE_PAGE = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
LWIR_TELEMETRY__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
CAMSYNC_MASTER_BIT = int
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
NUM_CYCLES_28__RAW = str
LWIR_TELEMETRY_STATUS__TYPE = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
MULTICLK_BUF_AXIHP__TYPE = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CAMSYNC_GPIO_EXT_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
RTC_SET_CORR__RAW = str
SENSI2C_TBL_RAH_BITS__RAW = str
TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
SENSOR_TIMING_BITS__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
WOI_WIDTH = int
CMPRS_AFIMUX_WIDTH__RAW = str
BUF_CLK1X_PCLK2X = str
MCNTRL_TEST01_CHN4_MODE = int
HISPI_DQS_BIAS = str
TABLE_FOCUS_INDEX = int
CMPRS_CBIT_RUN_STANDALONE__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
DFLT_DQ_TRI_OFF_PATTERN__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_CMODE_JP4DIFF = int
MULT_SAXI_CNTRL_MASK__TYPE = str
LWIR_DATA_FILE3__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN = int
VOSPI_GPIO__RAW = str
INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
CMPRS_AFIMUX_RST__RAW = str
SENSOR12BITS_TDDO__RAW = str
CAMSYNC_TRIG_DST__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
SENSOR_TIMING_TO__TYPE = str
HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
MCNTRL_SCANLINE_START_DELAY = int
SENS_CTRL_QUADRANTS_EN = int
MCNTRL_SCANLINE_WINDOW_WH__RAW = str
MULTICLK_PHASE_FB__TYPE = str
SENSI2C_TBL_NBWR_BITS = int
VOSPI_RST_SEQ__TYPE = str
BUF_IPCLK2X_SENS2 = str
BUF_IPCLK2X_SENS3 = str
BUF_IPCLK2X_SENS0 = str
BUF_IPCLK2X_SENS1 = str
LOGGER_CONFIG = int
DLY_LD__RAW = str
HISPI_MMCM3__TYPE = str
NUM_CYCLES_12__TYPE = str
MCONTR_LINTILE_EXTRAPG = int
MEMCLK_IOSTANDARD = str
DLY_LANE1_ODELAY__RAW = str
SENSI2C_IBUF_LOW_PWR__RAW = str
SENSI2C_STATUS_REG_REL = int
AXI_RDADDR_LATENCY__RAW = str
SENSOR_CTRL_ADDR_MASK = int
SENS_GAMMA_MODE_BAYER_SET = int
NUM_CYCLES_16__TYPE = str
SS_MODE = str
CMDFRAMESEQ_MASK__RAW = str
SENSOR12BITS_TMD__TYPE = str
SENS_CTRL_LD_DLY__TYPE = str
MCONTR_TOP_16BIT_ADDR__TYPE = str
PXD_SLEW = str
VOSPI_DBG_SRC_BITS__TYPE = str
MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
TEST01_SUSPEND = int
NUM_FRAME_BITS = int
LOGGER_STATUS_REG_ADDR__RAW = str
CMPRS_CBIT_FRAMES_BITS__RAW = str
MCNTRL_TILED_MASK__TYPE = str
DEBUG_MASK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN = int
SENSI2C_CMD_ACIVE = int
CMPRS_FRMT_LMARG__TYPE = str
LWIR_TELEMETRY_TIME_LAST_MS__TYPE = str
SENSI2C_TBL_NBRD_BITS = int
SENSIO_JTAG = int
DLY_LD = int
CMPRS_CBIT_FRAMES_SINGLE = int
SENS_SYNC_LATE = int
MEMBRIDGE_CTRL_IRQ = int
CMDFRAMESEQ_CTRL__RAW = str
SENSIO_DELAYS = int
MULTICLK_BUF_SYNC = str
MCONTR_BUF0_RD_ADDR__TYPE = str
CMPRS_STATUS_REG_INC__TYPE = str
DLY_LANE0_IDELAY__TYPE = str
MCNTRL_PS_ADDR__TYPE = str
VOSPI_SPI_TIMEOUT_MS = int
WINDOW_WIDTH__RAW = str
MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
SENS_CTRL_MRST__RAW = str
SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE = str
IPCLK2X_PHASE__TYPE = str
SENSOR_HIST_BITS_SET = int
CLK_MASK = int
MCNTRL_SCANLINE_CHN1_ADDR = int
VOSPI_MCLK__TYPE = str
MULT_SAXI_HALF_BRAM_IN = int
CMDFRAMESEQ_ADDR_INC__RAW = str
IPCLK_PHASE__TYPE = str
NUM_CYCLES_18__RAW = str
NUM_CYCLES_13__TYPE = str
MCONTR_WR_MASK__RAW = str
MCNTRL_TILED_WINDOW_STARTXY = int
MCONTR_TOP_0BIT_MCONTR_EN = int
SENS_LENS_BX__TYPE = str
LOGGER_CONF_GPS__RAW = str
SENS_GAMMA_MODE_TRIG__RAW = str
RTC_SET_CORR = int
CMPRS_CBIT_FOCUS__TYPE = str
CMPRS_NUM_AFI_CHN__TYPE = str
CMPRS_GROUP_ADDR__RAW = str
CAMSYNC_GPIO_INT_IN__TYPE = str
SENS_LENS_AX__RAW = str
CMPRS_JP4DIFF__RAW = str
SENS_SS_MODE__RAW = str
CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
CAMSYNC_GPIO_INT_OUT__RAW = str
LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
HISPI_CAPACITANCE = str
HISTOGRAM_START_PAGE__RAW = str
CONTROL_ADDR_MASK = int
LOGGER_PERIOD = int
MEMCLK_PERIOD__RAW = str
MCONTR_BUF0_WR_ADDR = int
MCNTRL_PS_STATUS_REG_ADDR__RAW = str
LOGGER_STATUS_MASK__RAW = str
RTC_ADDR__RAW = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMDFRAMESEQ_RUN_BIT__TYPE = str
VOSPI_GPIO_BITS__RAW = str
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
SENSI2C_CTRL__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
SENS_CTRL_GP0__RAW = str
SENSI2C_CMD_USE_EOF = int
MCONTR_BUF2_WR_ADDR__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG1 = int
MULT_SAXI_BSLOG2 = int
MULT_SAXI_BSLOG3 = int
MCONTR_BUF4_RD_ADDR__RAW = str
SENS_SS_MOD_PERIOD = int
DQSTRI_FIRST = int
VOSPI_HACT_TO_HACT_EOF = int
SENS_REF_JITTER2__RAW = str
SCANLINE_EXTRA_PAGES__RAW = str
CMDSEQMUX_STATUS__RAW = str
MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
SENSOR_IMAGE_TYPE0__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
DIVCLK_DIVIDE_PCLK = int
SENSOR_TIMING_STATUS_REG_INC__TYPE = str
MCNTRL_PS_MASK = int
SENSI2C_STATUS__TYPE = str
CMPRS_CSAT_CB_BITS = int
SENSI2C_TBL_NBRD__RAW = str
HISPI_IBUF_DELAY_VALUE = str
SENSI2C_IOSTANDARD = str
GPIO_IOSTANDARD = str
MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
SENS_SYNC_MINPER__TYPE = str
SENSI2C_CTRL_RADDR__RAW = str
SENS_SYNC_LATE_DFLT__RAW = str
MCONTR_LINTILE_DIS_NEED__RAW = str
MCONTR_LINTILE_WRITE__TYPE = str
CAMSYNC_MASTER_BIT__RAW = str
MEMBRIDGE_STATUS_CNTRL = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
GPIO_SET_PINS__TYPE = str
CONTROL_RBACK_ADDR__TYPE = str
CMPRS_CORING_BITS__RAW = str
CMDFRAMESEQ_RST_BIT = int
CAMSYNC_SNDEN_BIT = int
DQSTRI_FIRST__RAW = str
SENSI2C_CTRL_MASK__TYPE = str
LWIR_TELEMETRY_SREV = int
VOSPI_SPI_TIMEOUT_MS__RAW = str
SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
SENS_JTAG_TMS__RAW = str
VOSPI_RESET_ERR = int
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str
SENS_CTRL_MRST = int
MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
MCONTR_SENS_STATUS_BASE__RAW = str
MCNTRL_TEST01_CHN3_MODE__TYPE = str
MCONTR_BUF2_RD_ADDR__TYPE = str
SENS_SYNC_RADDR__RAW = str
SENS_HIGH_PERFORMANCE_MODE__RAW = str
VOSPI_MRST_AFTER_MS__RAW = str
MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
CLKFBOUT_PHASE_SENSOR__TYPE = str
SENSOR_HIST_NRST_BITS__TYPE = str
GPIO_PORTEN = int
RTC_STATUS_REG_ADDR__TYPE = str
SENS_JTAG_TCK__TYPE = str
VOSPI_SPI_TIMEOUT_MS__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
SENSOR_CHN_EN_BIT_SET__TYPE = str
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
CMDFRAMESEQ_ADDR_BASE__TYPE = str
AXI_WRDATA_LATENCY__TYPE = str
SENS_GAMMA_HEIGHT01 = int
RTC_SET_SEC__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
SS_MODE__RAW = str
MCNTRL_SCANLINE_CHN3_ADDR = int
NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
VOSPI_MRST_AFTER_MS__TYPE = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
VOSPI_PACKET_TTT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str
MCONTR_PHY_0BIT_ADDR__RAW = str
MCLK_PHASE = float
CMPRS_INTERRUPTS = int
SENSI2C_SLEW__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str
DQTRI_FIRST = int
CONTROL_RBACK_DEPTH = int
CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY1 = int
CAMSYNC_TRIG_DELAY2 = int
CAMSYNC_TRIG_DELAY3 = int
SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int
CAMSYNC_GPIO_INT_IN__RAW = str
CMPRS_CBIT_BE16__RAW = str
VOSPI_IOSTANDARD__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
CMPRS_FRMT_LMARG_BITS__RAW = str
LWIR_TELEMETRY_TIME_LAST_MS = int
MEMBRIDGE_ADDR__TYPE = str
LAST_FRAME_BITS = int
SENSOR_FIFO_2DEPTH__RAW = str
CMPRS_COLOR20__RAW = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
WINDOW_Y0__TYPE = str
SENSI2C_CTRL__TYPE = str
LOGGER_PAGE_MSG__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL = int
CMPRS_CBIT_CMODE_MONO4__RAW = str
MULT_SAXI_MASK = int
SENS_LENS_BX_MASK__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
CMDFRAMESEQ_DEPTH__TYPE = str
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
DLY_LANE0_IDELAY__RAW = str
HISPI_UNTUNED_SPLIT__RAW = str
HISTOGRAM_RADDR1__RAW = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
HISTOGRAM_HEIGHT__RAW = str
SENSOR_TIMING_BITS = int
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
VOSPI_OUT_EN_SINGL__RAW = str
FRAME_START_ADDRESS_INC__RAW = str
SENSOR12BITS_TDDO__TYPE = str
LWIR_TELEMETRY_AGC_ROI_LEFT__TYPE = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
SENS_GAMMA_ADDR_DATA = int
HISPI_WAIT_ALL_LANES = int
MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
HISPI_DQS_BIAS__RAW = str
MCONTR_LINTILE_WRITE = int
TILE_VSTEP__TYPE = str
MCONTR_PHY_STATUS_CNTRL__RAW = str
VOSPI_MRST_MS__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY = int
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
SENSI2C_CMD_RESET = int
SENSI2C_TBL_NABRD__TYPE = str
NUM_CYCLES_01__RAW = str
WINDOW_HEIGHT__RAW = str
GPIO_IBUF_LOW_PWR = str
DQTRI_LAST = int
SENSI2C_CTRL_MASK = int
PHASE_CLK2X_PCLK__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
MCONTR_TOP_0BIT_ADDR__RAW = str
HISPI_IBUF_LOW_PWR = str
SENS_GAMMA_MODE_REPET_SET = int
HISPI_KEEP_IRST__RAW = str
LOGGER_CONF_DBG__TYPE = str
AFI_SIZE64__RAW = str
SENSI2C_TBL_RNWREG = int
STATUS_PSHIFTER_RDY_MASK = int
SENSI2C_CMD_FIFO_RD__TYPE = str
SENS_LENS_C_MASK__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST__RAW = str
SENSI2C_CMD_ACIVE_EARLY0 = int
SENS_PHASE_WIDTH__RAW = str
SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
FRAME_WIDTH_ROUND_BITS = int
VOSPI_MCLK_BITS__TYPE = str
LD_DLY_LANE1_IDELAY__TYPE = str
CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str
MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
CMPRS_CBIT_CMODE_BITS = int
TEST01_START_FRAME__TYPE = str
MULT_SAXI_CNTRL_ADDR__RAW = str
FFCLK1_IOSTANDARD__TYPE = str
CAMSYNC_TRIG_DELAY2__RAW = str
MCNTRL_TEST01_CHN4_MODE__RAW = str
DLY_CMDA__TYPE = str
CLKFBOUT_MULT__TYPE = str
DEBUG_MASK = int
MCONTR_PHY_0BIT_CMDA_EN__RAW = str
SENS_GAMMA_MODE_PAGE_SET__TYPE = str
IDELAY_VALUE = int
DQSTRI_LAST__TYPE = str
HISTOGRAM_RADDR2__TYPE = str
SENS_JTAG_PROG__TYPE = str
TILE_VSTEP = int
DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
CAMSYNC_EN_BIT__RAW = str
SENSIO_WIDTH = int
MCONTR_PHY_0BIT_DLY_RST__RAW = str
BUF_CLK1X_PCLK2X__RAW = str
MULT_SAXI_POINTERS_REG = int
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
SENSI2C_TBL_RAH = int
SENS_LENS_FAT0_OUT__RAW = str
SENSI2C_ADDR_MASK__RAW = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
TEST01_SUSPEND__TYPE = str
NUM_CYCLES_15__RAW = str
DLY_DQ_IDELAY = int
CLKFBOUT_USE_FINE_PS = int
MCNTRL_TEST01_ADDR__TYPE = str
CMPRS_STATUS_REG_BASE = int
MCONTR_LINTILE_NRESET = int
CMPRS_CBIT_RUN_BITS = int
SENS_LENS_AY_MASK = int
BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MULTICLK_DIV_XCLK__TYPE = str
HISPI_MMCM2__TYPE = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
MCONTR_LINTILE_SINGLE__TYPE = str
DLY_DQ_IDELAY__RAW = str
MCONTR_LINTILE_ABORT_LATE__RAW = str
SENSOR_CTRL_RADDR__RAW = str
CMPRS_MONO16 = int
CONTROL_ADDR__RAW = str
SENSI2C_TBL_DLY = int
SENSIO_STATUS__RAW = str
SENSOR_16BIT_BIT_SET = int
MCONTR_LINTILE_DIS_NEED = int
SENS_LENS_BX_MASK = int
HISPI_FIFO_START__RAW = str
DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
FFCLK1_IOSTANDARD = str
CMPRS_RAW = int
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
CMPRS_CBIT_ROWS_LSB_BITS__RAW = str
MULT_SAXI_BSLOG2__TYPE = str
TILED_STARTX = int
MEMBRIDGE_MASK__TYPE = str
SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_31__TYPE = str
HISPI_CAPACITANCE__RAW = str
CMPRS_CBIT_BE16_BITS__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
HISPI_DIFF_TERM__RAW = str
BUF_IPCLK_SENS2__TYPE = str
SENSOR_FIFO_DELAY__TYPE = str
CMDFRAMESEQ_ABS__TYPE = str
NUM_CYCLES_06__RAW = str
SENS_JTAG_TDI = int
CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
VOSPI_MRST__TYPE = str
HISTOGRAM_START_PAGE__TYPE = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = int
VOSPI_SEGMENT_FIRST__RAW = str
DEBUG_SHIFT_DATA__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
VOSPI_PACKET_TTT = int
CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
SENSI2C_REL_RADDR = int
MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
DFLT_CHN_EN = int
GPIO_STATUS_REG_ADDR__RAW = str
DLY_DQS_ODELAY = int
SENSOR_CHN_EN_BIT__RAW = str
VOSPI_MRST_MS__RAW = str
CMPRS_AFIMUX_RADDR1 = int
CAMSYNC_TRIG_SRC__TYPE = str
SENSI2C_CMD_FIFO_RD = int
LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
SENS_LENS_AY__RAW = str
SS_EN = str
LWIR_TELEMETRY_AGC_ROI_LEFT__RAW = str
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
VOSPI_MRST = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ARO__RAW = str
BUF_IPCLK2X_SENS0__TYPE = str
MULTICLK_BUF_SYNC__RAW = str
MCONTR_PHY_0BIT_DLY_SET__RAW = str
NUM_CYCLES_11__RAW = str
SENS_GAMMA_MODE_REPET_SET__RAW = str
SENSI2C_DRIVE__RAW = str
LWIR_WINDOW_HEIGHT = int
SENSOR_HIST_BITS_SET__TYPE = str
HISPI_MMCM1 = str
LWIR_TELEMETRY_AGC_HIGH__TYPE = str
SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
NUM_CYCLES_LOW_BIT = int
READ_BLOCK_OFFSET = int
RSEL__RAW = str
VOSPI_TELEMETRY = int
LWIR_FRAME_DELAY__RAW = str
VOSPI_SEGM0_OK_BITS__TYPE = str
SDCLK_PHASE__TYPE = str
NUM_CYCLES_31__RAW = str
LWIR_TELEMETRY_REV__TYPE = str
SENSI2C_IBUF_LOW_PWR__TYPE = str
SENS_LENS_POST_SCALE_MASK__TYPE = str
SCANLINE_STARTY__TYPE = str
VOSPI_PACKET_WORDS__TYPE = str
SENS_LENS_SCALES_MASK = int
LOGGER_PAGE_MSG__TYPE = str
CAMSYNC_MASK__RAW = str
RTC_MHZ__TYPE = str
MEMBRIDGE_START64 = int
MEMBRIDGE_LO_ADDR64 = int
CMPRS_AFIMUX_EN__TYPE = str
CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
MCONTR_LINTILE_BYTE32 = int
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
SENSI2C_TBL_NABRD = int
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
MULTICLK_PHASE_XCLK = float
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
SENSOR_TIMING_START__RAW = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MULTICLK_IN_PERIOD = int
MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
MULTICLK_PHASE_FB__RAW = str
TABLE_HUFFMAN_INDEX__TYPE = str
SENS_GAMMA_MODE_EN_SET__TYPE = str
CMPRS_CBIT_ROWS_LSB = int
RTC_SET_STATUS__RAW = str
SENS_CTRL_QUADRANTS = int
LD_DLY_PHASE__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
CMPRS_INTERRUPTS__RAW = str
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
CMDSEQMUX_MASK__RAW = str
DFLT_WBUF_DELAY = int
CONTROL_RBACK_ADDR_MASK__RAW = str
AXI_WR_ADDR_BITS__TYPE = str
RTC_SET_STATUS = int
SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
VOSPI_SOF_TO_HACT__TYPE = str
CMPRS_AFIMUX_REG_ADDR0__RAW = str
CMPRS_FRMT_LMARG__RAW = str
NUM_CYCLES_22__TYPE = str
DLY_PHASE__RAW = str
MCONTR_SENS_INC__RAW = str
MULT_SAXI_WLOG__RAW = str
TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
LWIR_TELEMETRY_TEMP_COUTS__RAW = str
CLKIN_PERIOD_SENSOR = float
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
SENS_CTRL_ARST = int
LD_DLY_LANE1_IDELAY__RAW = str
MEMBRIDGE_STATUS_REG__RAW = str
CMDFRAMESEQ_DEPTH__RAW = str
SENS_LENS_BX_MASK__RAW = str
SENSI2C_TBL_NBWR_BITS__RAW = str
WRITE_BLOCK_OFFSET__RAW = str
SENS_GAMMA_MODE_EN_SET = int
MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
VOSPI_MCLK_HALFDIV__TYPE = str
SENS_GAMMA_BUFFER__TYPE = str
SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
MCNTRL_PS_MASK__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__TYPE = str
LWIR_MS_PERIOD__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT__RAW = str
HISPI_DELAY_CLK3__TYPE = str
MCONTR_LINTILE_BYTE32__TYPE = str
VOSPI_HACT_TO_HACT_EOF__TYPE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
CMDFRAMESEQ_IRQ_BIT__TYPE = str
VOSPI_DBG_SRC__TYPE = str
MCONTR_BUF4_WR_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
CAMSYNC_MASK = int
COLADDR_NUMBER__RAW = str
STATUS_SEQ_SHFT = int
SENS_GAMMA_BUFFER__RAW = str
MULT_SAXI_AWCACHE__TYPE = str
NUM_CYCLES_05__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
SENSI2C_TBL_NBWR__TYPE = str
AXI_WR_ADDR_BITS = int
FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
LWIR_TELEMETRY = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
WOI_HEIGHT__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__TYPE = str
HISTOGRAM_START_PAGE = int
VOSPI_MCLK_BITS = int
RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str
MEMCLK_IBUF_LOW_PWR = str
HISPI_DELAY_CLK3__RAW = str
CAMSYNC_TRIG_DST__TYPE = str
CMPRS_AFIMUX_RADDR1__TYPE = str
MCONTR_PHY_STATUS_CNTRL__TYPE = str
MULT_SAXI_WLOG = int
DLY_CMDA_ODELAY__RAW = str
SENSOR_GROUP_ADDR__TYPE = str
MCONTR_BUF2_RD_ADDR = int
MCNTRL_TILED_FRAME_SIZE = int
GPIO_SET_STATUS = int
CLKOUT_DIV_PCLK2X = int
VOSPI_PACKET_FIRST = int
MULT_SAXI_ADDR = int
VOSPI_SPI_CLK__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ODD = int
VOSPI_OUT_EN_BITS__TYPE = str
SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str
VOSPI_SOF_TO_HACT__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
SENSI2C_REL_RADDR__TYPE = str
AXI_WRADDR_LATENCY__RAW = str
GPIO_DRIVE = int
HISPI_MSB_FIRST__RAW = str
SENS_LENS_SCALES = int
CONTROL_ADDR_MASK__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__RAW = str
REF_JITTER1 = float
SENSOR_BASE_INC__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
SENS_DIVCLK_DIVIDE__TYPE = str
VOSPI_PACKET_FIRST__TYPE = str
LOGGER_CONF_MSG_BITS = int
SENS_GAMMA_RADDR__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
CMPRS_CBIT_CMODE_MONO1 = int
CMPRS_CBIT_CMODE_MONO6 = int
SENS_SS_EN = str
CMPRS_CBIT_CMODE_MONO4 = int
HISPI_DELAY_CLK2__RAW = str
SS_MOD_PERIOD__TYPE = str
TILE_HEIGHT = int
MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
CMPRS_TABLES__TYPE = str
VOSPI_SPI_CLK = int
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
FRAME_HEIGHT_BITS = int
MCONTR_BUF0_WR_ADDR__TYPE = str
SENSOR_CHN_EN_BIT__TYPE = str
CMPRS_COLOR18__RAW = str
LOGGER_STATUS = int
CMDFRAMESEQ_RUN_BIT__RAW = str
py393/x393_export_c.py
View file @ 043d4849
...@@ -324,7 +324,8 @@ class X393ExportC(object): ...@@ -324,7 +324,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status", stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(), data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(), self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()], self._enc_status_sens_io_vospi(),
self._enc_status_sens_io_boson()],
name = "x393_status_sens_io", typ="ro", name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
...@@ -434,7 +435,8 @@ class X393ExportC(object): ...@@ -434,7 +435,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control", stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(), data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi(), self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()], self._enc_sensio_ctrl_vospi(),
self._enc_sensio_ctrl_boson()],
name = "x393_sensio_ctl", typ="wo", name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA", stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
...@@ -450,12 +452,14 @@ class X393ExportC(object): ...@@ -450,12 +452,14 @@ class X393ExportC(object):
""" """
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 0 (different meanings for different sensor types)", stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 0 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim0(), data = [self._enc_sensio_par12_tim0(),
self._enc_sensio_hispi_tim0()], self._enc_sensio_hispi_tim0(),
self._enc_sensio_boson_tim0()],
name = "x393_sensio_tim0", typ="rw", name = "x393_sensio_tim0", typ="rw",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 1 (different meanings for different sensor types)", stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 1 (different meanings for different sensor types)",
data = [self._enc_sensio_par12_tim1(), data = [self._enc_sensio_par12_tim1(),
self._enc_sensio_hispi_tim1()], self._enc_sensio_hispi_tim1(),
self._enc_sensio_boson_tim1()],
name = "x393_sensio_tim1", typ="rw", name = "x393_sensio_tim1", typ="rw",
frmt_spcs = frmt_spcs) frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 2 (different meanings for different sensor types)", stypedefs += self.get_typedef32(comment = "Sensor i/o timing register 2 (different meanings for different sensor types)",
...@@ -1898,6 +1902,25 @@ class X393ExportC(object): ...@@ -1898,6 +1902,25 @@ class X393ExportC(object):
dw.append(("seq_num", 26, 6,0, "Sequence number")) dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw return dw
def _enc_status_sens_io_boson(self):
dw=[]
dw.append(("ps_out", 0, 8,0, "Sensor MMCM current phase"))
dw.append(("ps_rdy", 8, 1,0, "Sensor MMCM phase ready"))
dw.append(("perr", 9, 1,0, "Parity error in video stream"))
dw.append(("clkfb_pxd_stopped_mmcm",10, 1,0, "Sensor MMCM feedback clock stopped"))
dw.append(("clkin_pxd_stopped_mmcm",11, 1,0, "Sensor MMCM input clock stopped"))
dw.append(("locked_pxd_mmcm", 12, 1,0, "Sensor MMCM locked"))
dw.append(("hact_alive", 13, 1,0, "HACT signal from the sensor (or internal) is toggling"))
dw.append(("recv_prgrs", 14, 1,0, "UART packet receive in progress"))
dw.append(("recv_dav", 15, 1,0, "Byte available in received UART packet"))
dw.append(("recv_data", 16, 8,0, "Received UART data byte"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xmit_busy", 25, 1,0, "UART transmitter busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self): def _enc_status_sens_i2c(self):
dw=[] dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO")) dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
...@@ -1964,6 +1987,7 @@ class X393ExportC(object): ...@@ -1964,6 +1987,7 @@ class X393ExportC(object):
dw.append(("nbwr", vrlg.SENSI2C_TBL_NBWR, vrlg.SENSI2C_TBL_NBWR_BITS,0, "Number of bytes to write (1..10)")) dw.append(("nbwr", vrlg.SENSI2C_TBL_NBWR, vrlg.SENSI2C_TBL_NBWR_BITS,0, "Number of bytes to write (1..10)"))
dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period")) dw.append(("dly", vrlg.SENSI2C_TBL_DLY, vrlg.SENSI2C_TBL_DLY_BITS, 0, "Bit delay - number of mclk periods in 1/4 of the SCL period"))
dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode")) dw.append(("tbl_mode", vrlg.SENSI2C_CMD_TAND, 2, 2, "Should be 2 to select table data write mode"))
dw.append(("extif_mode", vrlg.SENSI2C_TBL_EXTIF, vrlg.SENSI2C_TBL_EXTIF_BITS,0, "External interface mode: 0 - I2C (old), 1 - UART (Boson)"))
return dw return dw
def _enc_i2c_tbl_rmode(self): def _enc_i2c_tbl_rmode(self):
...@@ -2156,6 +2180,29 @@ class X393ExportC(object): ...@@ -2156,6 +2180,29 @@ class X393ExportC(object):
dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src")) dw.append(("dbg_src_set", vrlg.VOSPI_DBG_SRC+3, 1, 0, "Enable write to dbg_src"))
return dw return dw
def _enc_sensio_ctrl_boson(self):
dw=[]
dw.append(("mrst", vrlg.SENS_CTRL_MRST, 1, 0, "MRST signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.SENS_CTRL_MRST + 1, 1, 0, "when set to 1, MRST is set to the 'mrst' field value"))
# dw.append(("arst", vrlg.SENS_CTRL_ARST, 1, 0, "ARST signal to the sensor"))
# dw.append(("arst_set", vrlg.SENS_CTRL_ARST + 1, 1, 0, "ARST set to the 'arst' field"))
# dw.append(("aro", vrlg.SENS_CTRL_ARO, 1, 0, "ARO signal to the sensor"))
# dw.append(("aro_set", vrlg.SENS_CTRL_ARO + 1, 1, 0, "ARO set to the 'aro' field"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sensor clock) reset signal"))
dw.append(("mmcm_rst_set", vrlg.SENS_CTRL_RST_MMCM + 1, 1, 0, "MMCM reset set to 'mmcm_rst' field"))
# dw.append(("ign_embed", vrlg.SENS_CTRL_IGNORE_EMBED, 1, 0, "Ignore embedded data (non-image pixel lines"))
# dw.append(("ign_embed_set",vrlg.SENS_CTRL_IGNORE_EMBED + 1,1,0, "Set mode to 'ign_embed' field"))
dw.append(("set_dly", vrlg.SENS_CTRL_LD_DLY, 1, 0, "Set all pre-programmed delays to the sensor port input delays"))
dw.append(("gp0", vrlg.SENS_CTRL_GP0, 2, 0 , "GP0 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp0_set", vrlg.SENS_CTRL_GP0 + 2, 1, 0, "Set GP0 to 'gp0' value"))
dw.append(("gp1", vrlg.SENS_CTRL_GP1, 2, 0 , "GP1 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
dw.append(("gp2", vrlg.SENS_CTRL_GP2, 2, 0 , "GP2 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp2_set", vrlg.SENS_CTRL_GP2 + 2, 1, 0, "Set GP2 to 'gp2' value"))
dw.append(("gp3", vrlg.SENS_CTRL_GP3, 2, 0 , "GP3 multi-purpose signal to the sensor: 0 - float, 1 - low, 2 - high, 3 - TRIG"))
dw.append(("gp3_set", vrlg.SENS_CTRL_GP3 + 2, 1, 0, "Set GP3 to 'gp3' value"))
return dw
def _enc_sensio_jtag(self): def _enc_sensio_jtag(self):
dw=[] dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level")) dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
...@@ -2266,6 +2313,26 @@ class X393ExportC(object): ...@@ -2266,6 +2313,26 @@ class X393ExportC(object):
dw.append(("phase_h", 0, 8, 0, "MMCM phase")) dw.append(("phase_h", 0, 8, 0, "MMCM phase"))
return dw return dw
def _enc_sensio_boson_tim0(self):
dw=[]
dw.append(("uart_txd", 0, 8, 0, "UART transmit data byte"))
return dw
def _enc_sensio_boson_tim1(self):
dw=[]
dw.append(("uart_extif_en", vrlg.SENS_UART_EXTIF_EN, 1, 0, "UART: enable sequencer commands"))
dw.append(("uart_extif_en_set", vrlg.SENS_UART_EXTIF_EN+1, 1, 0, "set 'uart_extif_en' field"))
dw.append(("uart_xmit_rst", vrlg.SENS_UART_XMIT_RST, 1, 0, "UART: reset software packet transmission"))
dw.append(("uart_xmit_rst_set", vrlg.SENS_UART_XMIT_RST+1, 1, 0, "set 'uart_xmit_rst' field"))
dw.append(("uart_recv_rst", vrlg.SENS_UART_RECV_RST, 1, 0, "UART: reset software packet receiving"))
dw.append(("uart_recv_rst_set", vrlg.SENS_UART_RECV_RST+1, 1, 0, "set 'uart_recv_rst' field"))
dw.append(("uart_xmit_start", vrlg.SENS_UART_XMIT_START, 1, 0, "UART: start transmiting prepared packet"))
dw.append(("uart_recv_next", vrlg.SENS_UART_RECV_NEXT, 1, 0, "UART: advance receive FIFO to next byte"))
return dw
def _enc_sensio_width(self): def _enc_sensio_width(self):
dw=[] dw=[]
dw.append(("sensor_width", 0, 16, 0, "Sensor frame width (0 - use line sync signals from the sensor)")) dw.append(("sensor_width", 0, 16, 0, "Sensor frame width (0 - use line sync signals from the sensor)"))
...@@ -2784,4 +2851,4 @@ class X393ExportC(object): ...@@ -2784,4 +2851,4 @@ class X393ExportC(object):
\ No newline at end of file
py393/x393_sens_cmprs.py
View file @ 043d4849
...@@ -131,13 +131,17 @@ FRAME_START_ADDRESS_INC = 0x80000 ...@@ -131,13 +131,17 @@ FRAME_START_ADDRESS_INC = 0x80000
# for now - single sensor type per interface # for now - single sensor type per interface
SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"}, SENSOR_INTERFACES={x393_sensor.SENSOR_INTERFACE_PARALLEL: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}, x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"},
x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"}} x393_sensor.SENSOR_INTERFACE_VOSPI: {"mv":2800, "freq":24.0, "iface":"2V5_LVDS"},
x393_sensor.SENSOR_INTERFACE_BOSON: {"mv":1820, "freq":24.444, "iface":"1V8_LVDS"}} # see if freq is not needed
# x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}} # x393_sensor.SENSOR_INTERFACE_HISPI: {"mv":2500, "freq":24.444, "iface":"1V8_LVDS"}}
#slave is 7 bit #slave is 7 bit
#BOSON: add parameters for uart instead of the i2C
#Use 'hardware' dimensions here, simulation ones will be overwritten
SENSOR_DEFAULTS= { x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3}, SENSOR_DEFAULTS= { x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}, x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2},
# x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":120, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}} # x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":120, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}} x393_sensor.SENSOR_INTERFACE_VOSPI: {"width":160, "height":122, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2},
x393_sensor.SENSOR_INTERFACE_BOSON: {"width":640, "height":513, "top":0, "left":0, "slave":0x2a, "i2c_delay":100, "bayer":2}}
#SENSOR_DEFAULTS_SIMULATION= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3}, #SENSOR_DEFAULTS_SIMULATION= {x393_sensor.SENSOR_INTERFACE_PARALLEL: {"width":2592, "height":1944, "top":0, "left":0, "slave":0x48, "i2c_delay":100, "bayer":3},
# x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}} # x393_sensor.SENSOR_INTERFACE_HISPI: {"width":4384, "height":3288, "top":0, "left":0, "slave":0x10, "i2c_delay":100, "bayer":2}}
...@@ -187,8 +191,10 @@ class X393SensCmprs(object): ...@@ -187,8 +191,10 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0 SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_VOSPI]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_BOSON]["height"]= vrlg.WOI_HEIGHT + 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS) print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except: except:
...@@ -792,6 +798,37 @@ class X393SensCmprs(object): ...@@ -792,6 +798,37 @@ class X393SensCmprs(object):
spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable spi_en = 3, #None, # 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable
out_en = True) out_en = True)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = True,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = False,
uart_xmit_rst = True,
uart_recv_rst = True,
uart_xmit_start = False,
uart_recv_next = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = True, #reset mmcm
set_delays = False)
self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor,
mrst = False,
mmcm_rst = False,
set_delays = False)
self.x393Sensor.func_sensor_uart_ctl_boson (
uart_extif_en = True,
uart_xmit_rst = False,
uart_recv_rst = False,
uart_xmit_start = False,
uart_recv_next = False)
if exit_step == 17: return False if exit_step == 17: return False
""" """
...@@ -1844,7 +1881,8 @@ class X393SensCmprs(object): ...@@ -1844,7 +1881,8 @@ class X393SensCmprs(object):
num_bytes_rd = 2, num_bytes_rd = 2,
bit_delay = i2c_delay, bit_delay = i2c_delay,
verbose = verbose) verbose = verbose)
elif sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
pass
else: else:
raise ("Unknown sensor type: %s"%(sensorType)) raise ("Unknown sensor type: %s"%(sensorType))
......
py393/x393_sensor.py
View file @ 043d4849
...@@ -49,6 +49,7 @@ import x393_mcntrl ...@@ -49,6 +49,7 @@ import x393_mcntrl
SENSOR_INTERFACE_PARALLEL = "PAR12" SENSOR_INTERFACE_PARALLEL = "PAR12"
SENSOR_INTERFACE_HISPI = "HISPI" SENSOR_INTERFACE_HISPI = "HISPI"
SENSOR_INTERFACE_VOSPI = "VOSPI" SENSOR_INTERFACE_VOSPI = "VOSPI"
SENSOR_INTERFACE_BOSON = "BOSON"
class X393Sensor(object): class X393Sensor(object):
DRY_MODE= True # True DRY_MODE= True # True
...@@ -74,11 +75,21 @@ class X393Sensor(object): ...@@ -74,11 +75,21 @@ class X393Sensor(object):
Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi Get sensor interface type by reading status register 0xfe that is set to 0 for parallel and 1 for HiSPi
@return "PAR12" or "HISPI" @return "PAR12" or "HISPI"
""" """
if self.DRY_MODE is True: print ("===== Was: Running in dry mode, using parallel sensor======")
print ("===== Running in dry mode, using parallel sensor======") # if self.DRY_MODE is True:
return SENSOR_INTERFACE_PARALLEL # print ("===== Running in dry mode, using parallel sensor======")
print(self.x393_axi_tasks.read_status(address=0xfe)) # return SENSOR_INTERFACE_PARALLEL
sens_type = (SENSOR_INTERFACE_PARALLEL, SENSOR_INTERFACE_HISPI,SENSOR_INTERFACE_VOSPI)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI" try:
print(self.x393_axi_tasks.read_status(address=0xfe))
except:
print ("===== Failed to read sesnor type, using parallel sensor======")
if self.DRY_MODE is True:
return SENSOR_INTERFACE_PARALLEL
sens_type = (SENSOR_INTERFACE_PARALLEL,
SENSOR_INTERFACE_HISPI,
SENSOR_INTERFACE_VOSPI,
SENSOR_INTERFACE_BOSON
)[self.x393_axi_tasks.read_status(address=0xfe)] # "PAR12" , "HISPI"
print ("===== Sensor type read from FPGA = >>> %s <<< ======"%(sens_type)) print ("===== Sensor type read from FPGA = >>> %s <<< ======"%(sens_type))
return sens_type return sens_type
...@@ -186,6 +197,20 @@ class X393Sensor(object): ...@@ -186,6 +197,20 @@ class X393Sensor(object):
print (" senspgmin = %d"%((status>>24) & 1)) print (" senspgmin = %d"%((status>>24) & 1))
print (" busy = %d"%((status>>25) & 1)) print (" busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f)) print (" seq = %d"%((status>>26) & 0x3f))
elif (sensorType == SENSOR_INTERFACE_BOSON):
print (" ps_out = %d"%((status>> 0) & 0xff))
print (" ps_rdy = %d"%((status>> 8) & 1))
print (" perr = %d"%((status>> 9) & 1))
print (" clkfb_pxd_stopped_mmcm = %d"%((status>>10) & 1))
print (" clkin_pxd_stopped_mmcm = %d"%((status>>11) & 1))
print (" locked_pxd_mmcm = %d"%((status>>12) & 1))
print (" hact_alive = %d"%((status>>13) & 1))
print (" recv_prgrs = %d"%((status>>14) & 1))
print (" recv_dav = %d"%((status>>15) & 1))
print (" recv_data = %d"%((status>>16) & 0xff))
print (" senspgmin = %d"%((status>>24) & 1))
print (" xmit_busy = %d"%((status>>25) & 1))
print (" seq = %d"%((status>>26) & 0x3f))
else: else:
#last_in_line_1cyc_mclk, dout_valid_1cyc_mclk #last_in_line_1cyc_mclk, dout_valid_1cyc_mclk
""" """
...@@ -376,12 +401,14 @@ class X393Sensor(object): ...@@ -376,12 +401,14 @@ class X393Sensor(object):
rah, rah,
num_bytes, num_bytes,
bit_delay, bit_delay,
extif = 0,
verbose = 1): verbose = 1):
""" """
@param slave_addr - 7-bit i2c slave address @param slave_addr - 7-bit i2c slave address
@param rah - register address high byte (bits [15:8]) optionally used for register write commands @param rah - register address high byte (bits [15:8]) optionally used for register write commands
@param num_bytes - number of bytes to send (including register address bytes) 1..10 @param num_bytes - number of bytes to send (including register address bytes) 1..10
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period @param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param extif - extrenal intgerface instead of i2c. 0 - i2c, 1 - uart,2,3 - reserved
@param verbose - verbose level @param verbose - verbose level
@return combined table data word. @return combined table data word.
""" """
...@@ -392,6 +419,7 @@ class X393Sensor(object): ...@@ -392,6 +419,7 @@ class X393Sensor(object):
rslt |= (rah & ((1 << vrlg.SENSI2C_TBL_RAH_BITS) - 1)) << vrlg.SENSI2C_TBL_RAH rslt |= (rah & ((1 << vrlg.SENSI2C_TBL_RAH_BITS) - 1)) << vrlg.SENSI2C_TBL_RAH
rslt |= (num_bytes & ((1 << vrlg.SENSI2C_TBL_NBWR_BITS) - 1)) << vrlg.SENSI2C_TBL_NBWR rslt |= (num_bytes & ((1 << vrlg.SENSI2C_TBL_NBWR_BITS) - 1)) << vrlg.SENSI2C_TBL_NBWR
rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY rslt |= (bit_delay & ((1 << vrlg.SENSI2C_TBL_DLY_BITS) - 1)) << vrlg.SENSI2C_TBL_DLY
rslt |= (extif & ((1 << vrlg.SENSI2C_TBL_EXTIF_BITS) - 1)) << vrlg.SENSI2C_TBL_EXTIF
return rslt return rslt
def func_sensor_i2c_table_reg_rd (self, def func_sensor_i2c_table_reg_rd (self,
...@@ -551,7 +579,68 @@ class X393Sensor(object): ...@@ -551,7 +579,68 @@ class X393Sensor(object):
return rslt return rslt
def func_sensor_io_ctl_boson (self,
mrst = None,
mmcm_rst = None,
set_delays = False,
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
"""
Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param mmcm_rst - True - activate MMCM reset, False - deactivate MMCM reset, None - no change (needed after clock change/interruption)
@param set_delays - (self-clearing) load all pre-programmed delays for the sensor pad inputs
@param gpio0 - GPIO[0]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@return sensor i/o control word
"""
rslt = 0
if not mrst is None:
rslt |= (3,2)[mrst] << vrlg.SENS_CTRL_MRST
if not mmcm_rst is None:
rslt |= (2,3)[mmcm_rst] << vrlg.SENS_CTRL_RST_MMCM
rslt |= (0,1)[set_delays] << vrlg.SENS_CTRL_LD_DLY
#GPIO are not yet used in Boson?
if not gpio0 is None:
rslt |= (4 | (gpio0 & 3)) << vrlg.SENS_CTRL_GP0
if not gpio1 is None:
rslt |= (4 | (gpio1 & 3)) << vrlg.SENS_CTRL_GP1
if not gpio2 is None:
rslt |= (4 | (gpio2 & 3)) << vrlg.SENS_CTRL_GP2
if not gpio3 is None:
rslt |= (4 | (gpio3 & 3)) << vrlg.SENS_CTRL_GP3
return rslt
def func_sensor_uart_ctl_boson (self,
uart_extif_en = None,
uart_xmit_rst = None,
uart_recv_rst = None,
uart_xmit_start = False,
uart_recv_next = False):
"""
Combine sensor UART control parameters into a control word
@param uart_extif_en - True - enable sequencer commands, False - disable sequencer commands
@param uart_xmit_rst - True - persistent reset software packet transmission, False - disable reset software packet transmission (normal operation)
@param uart_recv_rst - True - persistent reset packet receive, False - disable reset packet receive (normal operation)
@param uart_xmit_start - start transmiting prepared packet
@param uart_recv_next - advance receive FIFO to next byte
@return uart control word
"""
rslt = 0
if not uart_extif_en is None:
rslt |= (3,2)[uart_extif_en] << vrlg.SENS_UART_EXTIF_EN
if not uart_xmit_rst is None:
rslt |= (3,2)[uart_xmit_rst] << vrlg.SENS_UART_XMIT_RST
if not uart_recv_rst is None:
rslt |= (3,2)[uart_recv_rst] << vrlg.SENS_UART_RECV_RST
rslt |= (0,1)[uart_xmit_start] << vrlg.SENS_UART_XMIT_START
rslt |= (0,1)[uart_recv_next] << vrlg.SENS_UART_RECV_NEXT
return rslt
def func_sensor_jtag_ctl(self, def func_sensor_jtag_ctl(self,
pgmen = None, # <2: keep PGMEN, 2 - PGMEN low (inactive), 3 - high (active) enable JTAG control pgmen = None, # <2: keep PGMEN, 2 - PGMEN low (inactive), 3 - high (active) enable JTAG control
...@@ -733,15 +822,17 @@ class X393Sensor(object): ...@@ -733,15 +822,17 @@ class X393Sensor(object):
rah, rah,
num_bytes, num_bytes,
bit_delay, bit_delay,
extif = 0,
verbose = 1): verbose = 1):
""" """
Set table entry for a single index for register write Set table entry for a single index for register write
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
@param page - 1 byte table index (later provided as high byte of the 32-bit command) @param page - 1 byte table index (later provided as high byte of the 32-bit command)
@param slave_addr - 7-bit i2c slave address @param slave_addr - 7-bit i2c slave address (number of payload bytes for UART command (0..4)
@param rah - register address high byte (bits [15:8]) optionally used for register write commands @param rah - register address high byte (bits [15:8]) optionally used for register write commands (module # for UART)
@param num_bytes - number of bytes to send (including register address bytes) 1..10 @param num_bytes - number of bytes to send (including register address bytes) 1..10 (always 4 for UART)
@param bit_delay - number of mclk clock cycle in 1/4 of the SCL period @param bit_delay - number of mclk clock cycle in 1/4 of the SCL period
@param extif - extrenal intgerface instead of i2c. 0 - i2c, 1 - uart,2,3 - reserved
@param verbose - verbose level @param verbose - verbose level
""" """
ta = (1 << vrlg.SENSI2C_CMD_TABLE) | (1 << vrlg.SENSI2C_CMD_TAND) | (page & 0xff) ta = (1 << vrlg.SENSI2C_CMD_TABLE) | (1 << vrlg.SENSI2C_CMD_TAND) | (page & 0xff)
...@@ -750,6 +841,7 @@ class X393Sensor(object): ...@@ -750,6 +841,7 @@ class X393Sensor(object):
rah = rah, rah = rah,
num_bytes = num_bytes, num_bytes = num_bytes,
bit_delay = bit_delay, bit_delay = bit_delay,
extif = extif,
verbose = verbose) verbose = verbose)
self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta) self.x393_axi_tasks.write_control_register(vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC + vrlg.SENSI2C_CTRL_RADDR, ta)
...@@ -1166,6 +1258,118 @@ class X393Sensor(object): ...@@ -1166,6 +1258,118 @@ class X393Sensor(object):
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL; reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data) self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_io_ctl_boson (self,
num_sensor,
mrst = None,
mmcm_rst = None,
set_delays = False,
gpio0 = None,
gpio1 = None,
gpio2 = None,
gpio3 = None):
"""
Set sensor I/O controls, including I/O signals
@param num_sensor - sensor port number (0..3)
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
@param mmcm_rst - True - activate MMCM reset, False - deactivate MMCM reset, None - no change (needed after clock change/interruption)
@param set_delays - (self-clearing) load all pre-programmed delays for the sensor pad inputs
@param gpio0 - GPIO[0]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_io_ctl_boson (num_sensor,
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
return
except:
pass
data = self.func_sensor_io_ctl_boson (
mrst = mrst,
mmcm_rst = mmcm_rst,
set_delays = set_delays,
gpio0 = gpio0,
gpio1 = gpio1,
gpio2 = gpio2,
gpio3 = gpio3)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_uart_ctl_boson (self,
num_sensor,
uart_extif_en = None,
uart_xmit_rst = None,
uart_recv_rst = None,
uart_xmit_start = False,
uart_recv_next = False):
"""
Set sensor UART control signals
@param num_sensor - sensor port number (0..3)
@param uart_extif_en - True - enable sequencer commands, False - disable sequencer commands
@param uart_xmit_rst - True - persistent reset software packet transmission, False - disable reset software packet transmission (normal operation)
@param uart_recv_rst - True - persistent reset packet receive, False - disable reset packet receive (normal operation)
@param uart_xmit_start - start transmiting prepared packet
@param uart_recv_next - advance receive FIFO to next byte
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_uart_ctl_boson (num_sensor,
uart_extif_en = uart_extif_en,
uart_xmit_rst = uart_xmit_rst,
uart_recv_rst = uart_recv_rst,
uart_xmit_start = uart_xmit_start,
uart_recv_next = uart_recv_next)
return
except:
pass
data = self.func_sensor_uart_ctl_boson (
uart_extif_en = uart_extif_en,
uart_xmit_rst = uart_xmit_rst,
uart_recv_rst = uart_recv_rst,
uart_xmit_start = uart_xmit_start,
uart_recv_next = uart_recv_next)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + (vrlg.SENSIO_DELAYS + 1);
self.x393_axi_tasks.write_control_register(reg_addr, data)
def set_sensor_uart_fifo_byte_boson (self,
num_sensor,
uart_tx_byte):
"""
Write byte tio the sensor UART transmit FIFO
@param num_sensor - sensor port number (0..3)
@param uart_tx_byte - Byte to write to FIFO
"""
try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
for num_sensor in range(4):
self.set_sensor_uart_fifo_byte_boson (num_sensor,
uart_tx_byte = uart_tx_byte)
return
except:
pass
data = uart_tx_byte & 0xff;
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + (vrlg.SENSIO_DELAYS + 0);
self.x393_axi_tasks.write_control_register(reg_addr, data)
# TODO: Make one for HiSPi (it is different)
def set_sensor_io_dly_parallel (self, def set_sensor_io_dly_parallel (self,
num_sensor, num_sensor,
mmcm_phase, mmcm_phase,
......
py393/x393_tiff_verilog.py
View file @ 043d4849
...@@ -50,6 +50,7 @@ try: ...@@ -50,6 +50,7 @@ try:
outname = sys.argv[3] outname = sys.argv[3]
except IndexError: except IndexError:
outname = fname.replace(".tiff",".dat") outname = fname.replace(".tiff",".dat")
print("Generating %s frm %s"%(outname, fname))
tif = Image.open(fname) tif = Image.open(fname)
...@@ -59,6 +60,9 @@ f="%%0%dx"%(digits) ...@@ -59,6 +60,9 @@ f="%%0%dx"%(digits)
with open(outname,"w") as outfile: with open(outname,"w") as outfile:
print("//",file=outfile) print("//",file=outfile)
print("// autogenerated from %s"%(fname),file=outfile) print("// autogenerated from %s"%(fname),file=outfile)
print("// GENERATOR = %s"%(sys.argv[0]),file=outfile)
print("// WIDTH = %d"%(image_array.shape[1]),file=outfile)
print("// HEIGHT = %d"%(image_array.shape[0]),file=outfile)
print("//",file=outfile) print("//",file=outfile)
for image_line in image_array: for image_line in image_array:
for pixel in image_line: for pixel in image_line:
......
sensor/boson_uart.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> boson_uart
* @file boson_uart.v
* @date 2020-12-12
* @author eyesis
*
* @brief 921.6K8N1 UART to communicate with Boson
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* boson_uart.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* boson_uart.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh" // just for debugging histograms
module boson_uart #(
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
input [7:0] tx_byte, // transmit byte in
input tx_stb, // transmit strobe for byte in
output tx_busy, // transmit in progress
output tx_rdy, // ready to accept tx_stb
output [7:0] rx_byte, // received byte
output rx_stb // received data strobe (valid 1 cycle before and later for 1 bit)
);
localparam CLK_DIV_BITS = clogb2(CLK_DIV); // + 1);
localparam RX_DEBOUNCE_BITS = clogb2(RX_DEBOUNCE + 1);
reg [CLK_DIV_BITS-1:0] clk_div_cntr_rx;
reg [CLK_DIV_BITS-1:0] clk_div_cntr_tx;
reg [RX_DEBOUNCE_BITS-1:0] debounce_cntr;
reg rxd_r;
reg [9:0] rx_sr; // receive channel shift register, including start_stop
reg [9:0] tx_sr; // transmit channel shift register, including start_stop
reg [7:0] tx_r; // transmit channel data input register
reg [3:0] rx_bcntr; // read channel bit counter;
reg [3:0] tx_bcntr; // read channel bit counter;
reg rx_err;
reg rx_bit;
reg [1:0] tx_bit;
reg [1:0] rx_stb_r;
reg tx_busy_r;
reg tx_rq; // request to transmit
reg mrst_d;
reg tx_start;
reg tx_continue;
wire debounced;
wire rx_bitw;
wire tx_bitw;
wire mark;
wire rx_errw;
wire start_bit_rx;
wire stop_bit_rx;
wire stop_bit_tx;
wire tx_startw; // start next 10-bit transmission
wire tx_continuew;
assign debounced = (debounce_cntr == 0);
assign rx_bitw = (clk_div_cntr_rx == 0);
assign tx_bitw = (clk_div_cntr_tx == 0);
assign mark = &rx_sr; // all ones
assign start_bit_rx = (rx_bcntr == 0);
assign stop_bit_rx = (rx_bcntr == 9);
assign stop_bit_tx = (tx_bcntr == 9);
assign rx_errw = rxd_r ? start_bit_rx : stop_bit_rx; // 1 at start, 0 at stop
assign tx_startw = tx_bit[0] && stop_bit_tx && tx_rq;
assign tx_continuew = tx_bit[0] && !stop_bit_tx;
assign rx_byte = rx_sr[8:1];
assign rx_stb = rx_stb_r[1];
assign tx_rdy = tx_rq;
assign tx_busy = tx_busy_r || !tx_rq;
assign txd = tx_sr[0];
always @(posedge mclk) begin
if (mrst) rxd_r <= rxd;
else if (debounced) rxd_r <= rxd;
if (rxd_r == rxd) debounce_cntr <= RX_DEBOUNCE;
else if (!debounced) debounce_cntr <= debounce_cntr - 1;
if (mrst) clk_div_cntr_rx <= CLK_DIV - 2;
else if (rx_bit) clk_div_cntr_rx <= CLK_DIV - 2;
else if (debounced) clk_div_cntr_rx <= (CLK_DIV >> 1); // half interval
else clk_div_cntr_rx <= clk_div_cntr_rx - 1;
rx_bit <= rx_bitw;
if (mrst) rx_sr <= 10'h3ff; // inactive "1"
else if (rx_bit) rx_sr <= {rxd_r,rx_sr[9:1]}; // little endian as RX232
if (mark || rx_err || (rx_bit && stop_bit_rx)) rx_bcntr <= 0;
else if (rx_bit) rx_bcntr <= rx_bcntr + 1;
if (mark) rx_err <= 0;
else if (rx_bit && rx_errw) rx_err <= 1;
rx_stb_r <= {rx_stb_r[0], stop_bit_rx & rx_bit};
end
// Transmit path
always @(posedge mclk) begin
if (tx_stb) tx_r <= tx_byte;
mrst_d <= mrst;
tx_bit <= {tx_bit[0],tx_bitw};
if (mrst) clk_div_cntr_tx <= CLK_DIV - 3;
else if (tx_bit[1]) clk_div_cntr_tx <= CLK_DIV - 3;
else clk_div_cntr_tx <= clk_div_cntr_tx - 1;
if (mrst) tx_sr <= 10'h3ff;
else if (tx_start) tx_sr <= {1'b1, tx_r, 1'b0};
else if (tx_bit[1]) tx_sr <= {1'b1, tx_sr[9:1]};
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_bit[1] && stop_bit_tx) tx_busy_r <= 0;
if (mrst) tx_rq <= 0;
else if (mrst_d) tx_rq <= 1; // single-cycle turn-on after mrst
else if (tx_stb) tx_rq <= 0;
else if (tx_start) tx_rq <= 1;
if (mrst) tx_bcntr <= 0;
else if (tx_start) tx_bcntr <= 0;
else if (tx_continue) tx_bcntr <= tx_bcntr + 1;
tx_start <= tx_startw;
tx_continue <= tx_continuew;
end
function integer clogb2;
input [31:0] value;
begin
value = value - 1;
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin // SuppressThisWarning VEditor - VDT bug
value = value >> 1;
end
end
endfunction
endmodule
sensor/crc16_xmodem.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> crc16_xmodem
* @file crc16_xmodem.v
* @date 2020-12-13
* @author eyesis
*
* @brief Calculate and insert/verify crc16 (both receive and transmit)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* crc16_xmodem.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_xmodem.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_xmodem#(
parameter INITIAL_CRC16 = 16'h1d0f
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
// Transmit channel
input tx_start, // initialize crc16
input [7:0] txd_in, // transmit payload
input tx_in_stb, // strobe for the txd_in
input tx_over, // payload data ended, should output crc16 (should be after the last tx_in_stb)
input tx_rdy, // stuffer is ready to accept next byte
output tx_in_rdy, // module ready to accept next byte
output [7:0] txd_out, // delayed txt_in, followed by the CRC16
output tx_out_stb, // load txd_out to stuffer
output tx_busy // does not include destuffer and uart
// implementing only transmit CRC16 as response is only needed for non-sequencer operation
/*
// receive channel
,input rx_start,
input [7:0] rxd_in, // byte input from stuffer
input rx_in_stb, // next byte from destuffer in rxd_in
input rx_over, // no more data from destuffer (last 2 bytes were crc16: msb, lsb)
output [7:0] rxd_out, // received chn, payload and crc data
output rx_out_stb, // received data output strobe
output rx_busy, // received channel busy
output rx_crc_good // valid with !rx_busy
*/
);
reg [7:0] txd_in_r;
reg tx_busy_r;
reg tx_stb_crc_m;
reg tx_stb_crc_l;
reg tx_stb_crc_l2; // next cycle after tx_stb_crc_l, same as last tx_out_stb
reg [15:0] tx_crc16_r;
reg [3:0] tx_crc16_s;
reg [7:0] crc16_addr;
reg [7:0] txd_out_r;
reg tx_pre_crc;
reg [1:0] tx_crc_out;
reg [1:0] tx_crc_out_d;
reg tx_in_rdy_r;
reg tx_dav_r;
reg tx_out_stb_r;
reg tx_out_stb_r2;
reg tx_gen_bsy;
wire tx_crc16_next; // calculate next CRC16
wire [15:0] crc16_table; // valid at tx_crc16_s[3]
wire [15:0] tx_crc16_w;
assign tx_crc16_next =tx_crc16_s[3];
assign tx_crc16_w = {tx_crc16_r[7:0] ^ crc16_table[15:8], crc16_table[7:0]};
assign tx_busy = tx_busy_r;
assign txd_out = txd_out_r;
assign tx_in_rdy = tx_in_rdy_r;
assign tx_out_stb = tx_out_stb_r;
always @(posedge mclk) begin
if (mrst) tx_in_rdy_r <= 0;
else if (tx_start || tx_crc16_s[0]) tx_in_rdy_r <= 1; // tx_crc16_next
else if (tx_in_stb || tx_over) tx_in_rdy_r <= 0;
if (mrst) tx_gen_bsy <= 0;
else if (tx_in_stb) tx_gen_bsy <= 1;
else if (tx_out_stb_r) tx_gen_bsy <= 0;
if (mrst) tx_pre_crc <= 0;
else if (tx_start) tx_pre_crc <= 0;
else if (tx_over) tx_pre_crc <= 1;
if (mrst) tx_crc_out[0] <= 0;
else if (tx_start) tx_crc_out[0] <= 0;
else if (tx_pre_crc && !tx_gen_bsy) tx_crc_out[0] <= 1;
if (mrst) tx_crc_out[1] <= 0;
else if (tx_start) tx_crc_out[1] <= 0;
else if (tx_crc_out[0] && tx_out_stb_r) tx_crc_out <= 2'h1;
tx_crc_out_d <= tx_crc_out;
if (mrst) tx_dav_r <= 0;
else if (tx_out_stb_r) tx_dav_r <= 0;
else if (tx_crc16_next || tx_stb_crc_m || tx_stb_crc_l) tx_dav_r <= 1;
tx_out_stb_r <= !tx_out_stb_r && !tx_out_stb_r2 && tx_dav_r && tx_rdy;
tx_out_stb_r2 <= tx_out_stb_r;
tx_stb_crc_m <= tx_crc_out[0] && !tx_crc_out[1] && !tx_crc_out_d[0]; // tx_crc_out[0] just 0->1
tx_stb_crc_l <= tx_crc_out[1] && !tx_crc_out_d[1]; // tx_crc_out[1] just 0->1
if (tx_crc16_next) txd_out_r <= txd_in_r;
else if (tx_stb_crc_m) txd_out_r <= tx_crc16_r[15:8];
else if (tx_stb_crc_l) txd_out_r <= tx_crc16_r[ 7:0];
if (mrst) tx_crc16_s <= 0;
else tx_crc16_s <= {tx_crc16_s[2:0],tx_in_stb};
if (tx_crc16_s[0]) crc16_addr <= tx_crc16_r[15:8] ^ txd_in_r;
if (tx_in_stb) txd_in_r <= txd_in;
tx_stb_crc_l2 <= tx_stb_crc_l;
if (mrst) tx_busy_r <= 0;
else if (tx_start) tx_busy_r <= 1;
else if (tx_stb_crc_l2) tx_busy_r <= 0;
if (tx_start) tx_crc16_r <= INITIAL_CRC16;
else if (tx_crc16_next) tx_crc16_r <= tx_crc16_w;
end
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (4),
.LOG2WIDTH_RD (4),
.DUMMY (0)
`ifdef PRELOAD_BRAMS
, .INIT_00 (256'hF1EFE1CED1ADC18CB16BA14A9129810870E760C650A540843063204210210000)
, .INIT_01 (256'hE3DEF3FFC39CD3BDA35AB37B8318933962D672F7429452B52252327302101231)
, .INIT_02 (256'hD58DC5ACF5CFE5EE95098528B54BA56A548544A474C764E61401042034432462)
, .INIT_03 (256'hC7BCD79DE7FEF7DF87389719A77AB75B46B4569566F676D70630161126723653)
, .INIT_04 (256'hB92BA90A99698948F9AFE98ED9EDC9CC382328021861084078A7688658E548C4)
, .INIT_05 (256'hAB1ABB3B8B589B79EB9EFBBFCBDCDBFD2A123A330A501A716A967AB74AD45AF5)
, .INIT_06 (256'h9D498D68BD0BAD2ADDCDCDECFD8FEDAE1C410C603C032C225CC54CE47C876CA6)
, .INIT_07 (256'h8F789F59AF3ABF1BCFFCDFDDEFBEFF9F0E701E512E323E134EF45ED56EB67E97)
, .INIT_08 (256'h606770464025500420E330C200A11080E16FF14EC12DD10CA1EBB1CA81A99188)
, .INIT_09 (256'h725662775214423532D222F3129002B1F35EE37FD31CC33DB3DAA3FB939883B9)
, .INIT_0A (256'h4405542464477466048114A024C334E2C50DD52CE54FF56E858995A8A5CBB5EA)
, .INIT_0B (256'h563446157676665716B0069136F226D3D73CC71DF77EE75F97B88799B7FAA7DB)
, .INIT_0C (256'h28A3388208E118C06827780648655844A9ABB98A89E999C8E92FF90EC96DD94C)
, .INIT_0D (256'h3A922AB31AD00AF17A166A375A544A75BB9AABBB9BD88BF9FB1EEB3FDB5CCB7D)
, .INIT_0E (256'h0CC11CE02C833CA24C455C646C077C268DC99DE8AD8BBDAACD4DDD6CED0FFD2E)
, .INIT_0F (256'h1EF00ED13EB22E935E744E557E366E179FF88FD9BFBAAF9BDF7CCF5DFF3EEF1F)
`endif
) i_crc16 (
.rclk (mclk), // input
.raddr ({2'b0, crc16_addr[7:0]}), // input[8:0]
.ren (tx_crc16_s[1]), // input
.regen (tx_crc16_s[2]), // input
.data_out (crc16_table[15:0]), // output[15:0]
.wclk (1'b0), // input
.waddr (10'b0), // input[8:0]
.we (1'b0), // input
.web (4'b0), // input[3:0]
.data_in (16'b0) // input[15:0]
);
endmodule
sensor/sens_103993.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993
* @file sens_103993.v
* @date 2015-10-15
* @author Andrey Filippov
*
* @brief Top level module for the 10398 SFE (with MT9F002 sensor)
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993 #(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
/// parameter SENSIO_JTAG = 'h2,
/// parameter SENSIO_WIDTH = 'h3, // HERE - number of lines to skip
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 - each address sets 4 delays through 4 bytes of 32-bit data
// 5, swap lanes 6 - delays, 7 - phase
parameter SENSIO_STATUS_REG = 'h21,
/// parameter SENS_JTAG_PGMEN = 8,
/// parameter SENS_JTAG_PROG = 6,
/// parameter SENS_JTAG_TCK = 4,
/// parameter SENS_JTAG_TMS = 2,
/// parameter SENS_JTAG_TDI = 0,
parameter SENS_CTRL_MRST= 0, // 1: 0
/// parameter SENS_CTRL_ARST= 2, // 3: 2
/// parameter SENS_CTRL_ARO= 4, // 5: 4
parameter SENS_CTRL_RST_MMCM= 6, // 7: 6
// parameter SENS_CTRL_EXT_CLK= 8, // 9: 8
/// parameter SENS_CTRL_IGNORE_EMBED = 8, // 9: 8
parameter SENS_CTRL_LD_DLY= 10, // 10
// parameter SENS_CTRL_GP0= 12, // 13:12
// parameter SENS_CTRL_GP1= 14, // 15:14
parameter SENS_CTRL_GP0= 12, // 14:12 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP1= 15, // 17:15 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
// parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
// parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
// parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// parameter LVDS_MSB_FIRST = 0,
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
// parameter LVDS_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter LVDS_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter LVDS_FIFO_DEPTH = 4,
// parameter LVDS_FIFO_START = 7,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE",
// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
// parameter PXD_CLK_DIV_BITS = 4,
// ,parameter STATUS_ALIVE_WIDTH = 4
// parameter SENSIO_SKIP_BITS = 8, // number of bits in line skip counter
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
output pclk, // global clock input, pixel rate (220MHz for MT9F002)
output locked_pclk,
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
// delay control inputs
input mclk,
input mrst,
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// input trigger_mode, // running in triggered mode (0 - free running mode)
input ext_sync, // trig, // per-sensor trigger input
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
inout sns_gp2, // sns1_dn[6] just to reduce EMI from the clock == gp[2]
inout sns_pgm, // (pullup) SENSPGM
output sns_ext_sync, // (TCK)
output sns_mrst, // sns_dp[7]
inout sns_gp3, // sns_dn[7] == gp[3] TMS
inout sns_gp0, // sns_dp[5] == gp[0] TDI (differs from 10353)
inout sns_gp1, // sns_dn[5] == gp[1]
output sns_txd, // flash_tdo, // sns_dp[4] TDO (differs from 10353)
input sns_rxd, // shutter_done,// sns_dn[4] DONE (differs from 10353)
output [15:0] pxd,
output vsync,
output hsync, // @pclk
output dvalid, // @pclk
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst
);
wire dvalid_w;
reg dvalid_r;
// wire vact_w;
// wire dvalid_w;
reg [31:0] data_r;
// reg [3:0] set_idelay;
// reg set_lanes_map; // set sequence of lanes im the composite pixel line
// reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_uart_ctrl; // set UART control bits (both TX and receive)
reg set_uart_tx; // set UART tx data (full, starting witgh channel number = 0)
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
reg set_status_r;
// reg set_jtag_r;
wire perr; // parity error from deserializer
wire ps_rdy;
wire [7:0] ps_out;
// wire locked_pxd_mmcm;
wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm;
// programmed resets to the sensor
reg imrst = 0; // active low
reg rst_mmcm=1; // rst and command - en/dis
reg ld_idelay=0;
wire [25:0] status;
wire cmd_we;
wire [2:0] cmd_a;
wire [31:0] cmd_data;
reg [7:0] gp_r; // sensor GP0, GP1. 2 bits per port : 00 - float, 01 - low, 10 - high , 11 - trigger
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
wire hact_mclk;
wire perr_mclk;
reg hact_alive;
reg perr_persistent;
// new for Boson
wire txd;
wire rxd;
reg extif_en; // enable sequencer commands (disable during software ones if needed)
reg xmit_rst; // input
reg recv_rst; // input
reg xmit_start; // input
reg recv_next; // input
wire xmit_busy; // output
wire recv_prgrs; // output
wire recv_dav; // output fifo not empty
wire [7:0] recv_data; // output[7:0]
wire senspgmin; // detect sensorboard
// GP0..GP3 are not yet used, fake-use gp_comb to keep
wire [3:0] gp;
wire gp_comb = &gp[3:0];
assign status = {recv_data[7:0], // [23:16]
recv_dav, // 15
recv_prgrs, // 14
mrst ? gp_comb : hact_alive, // 13 using gp_comb to keep
locked_pclk, // 12
clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error
ps_rdy, // 8
ps_out[7:0], // [7:0]
xmit_busy, // 25
senspgmin}; // 24
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign dvalid = dvalid_w;
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
always @(posedge pclk) begin
dvalid_r <= dvalid_w;
end
//dvalid_r
always @(posedge mclk) begin
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_uart_tx <= 0;
else set_uart_tx <= cmd_we & (cmd_a==(SENSIO_DELAYS+0)); // TODO - add Symbolic names
if (mrst) set_uart_ctrl <= 0;
else set_uart_ctrl <= cmd_we & (cmd_a==(SENSIO_DELAYS+1));
if (mrst) set_idelays <= 0;
else set_idelays <= cmd_we & (cmd_a==(SENSIO_DELAYS+2));
if (mrst) set_iclk_phase <= 0;
else set_iclk_phase <= cmd_we & (cmd_a==(SENSIO_DELAYS+3));
if (mrst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mrst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mrst) imrst <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_MRST + 1]) imrst <= data_r[SENS_CTRL_MRST];
if (mrst) rst_mmcm <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_RST_MMCM + 1]) rst_mmcm <= data_r[SENS_CTRL_RST_MMCM];
if (mrst) ld_idelay <= 0;
else ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY];
if (mrst) gp_r[1:0] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 2]) gp_r[1:0] <= data_r[SENS_CTRL_GP0+:2];
if (mrst) gp_r[3:2] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP1 + 2]) gp_r[3:2] <= data_r[SENS_CTRL_GP1+:2];
if (mrst) gp_r[5:4] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP2 + 2]) gp_r[5:4] <= data_r[SENS_CTRL_GP2+:2];
if (mrst) gp_r[7:6] <= 0;
else if (set_ctrl_r && data_r[SENS_CTRL_GP3 + 2]) gp_r[7:6] <= data_r[SENS_CTRL_GP3+:2];
if (mrst) extif_en <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_EXTIF_EN + 1]) extif_en <= data_r[SENS_UART_EXTIF_EN];
if (mrst) xmit_rst <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_XMIT_RST + 1]) xmit_rst <= data_r[SENS_UART_XMIT_RST];
if (mrst) recv_rst <= 0;
else if (set_uart_ctrl && data_r[SENS_UART_RECV_RST + 1]) recv_rst <= data_r[SENS_UART_RECV_RST];
xmit_start <= !mrst && set_uart_ctrl && data_r[SENS_UART_XMIT_START];
recv_next <= !mrst && set_uart_ctrl && data_r[SENS_UART_RECV_NEXT];
if (mrst || set_iclk_phase || set_idelays) hact_alive <= 0;
else if (hact_mclk) hact_alive <= 1;
if (mrst || set_ctrl_r) perr_persistent <= 0;
else if (perr_mclk) perr_persistent <= 1;
end
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (3),
.DATA_WIDTH (32)
) cmd_deser_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(26) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_r), // input
.wd (data_r[7:0]), // input[7:0]
.status (status), // input[22:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
serial_103993 #(
.START_FRAME_BYTE (START_FRAME_BYTE), // 'h8E),
.END_FRAME_BYTE (END_FRAME_BYTE), // 'hAE),
.ESCAPE_BYTE (ESCAPE_BYTE), // 'h9E),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE), // 'h81),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE), // 'hA1),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE), // 60),
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output
.rxd (rxd), // input
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst), // input
.extif_en (extif_en), // input
.xmit_rst (xmit_rst), // input
.xmit_start (xmit_start), // input
.xmit_data (data_r[7:0]), // input[7:0]
.xmit_stb (set_uart_tx), // input
.xmit_busy (xmit_busy), // output
.recv_rst (recv_rst), // input
.recv_next (recv_next), // input
.recv_prgrs (recv_prgrs), // output
.recv_dav (recv_dav), // output fifo not empty
.recv_data (recv_data) // output[7:0]
);
sens_103993_l3 #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), // 37.037),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), // (30),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), // (0.000),
.PCLK_PHASE (PCLK_PHASE), // (0.000),
.IPCLK2X_PHASE (IPCLK2X_PHASE), //(0.000),
.BUF_PCLK (BUF_PCLK), // "BUFR"),
.BUF_IPCLK2X (BUF_IPCLK2X), // "BUFR"),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), // 1),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), // 0.010),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), // 0.010),
.SENS_SS_EN (SENS_SS_EN), // "FALSE"),
.SENS_SS_MODE (SENS_SS_MODE), // "CENTER_HIGH"),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), // 10000),
.NUMLANES (NUMLANES), // 3),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK), // "FALSE"),
.LVDS_MMCM (LVDS_MMCM), // "TRUE"),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE), // "DONT_CARE"),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM), // "TRUE"),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT), // "FALSE"),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS), // "TRUE"),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE), // "0"),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR), // "TRUE"),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE), // "AUTO"),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD) // "DIFF_SSTL18_I")
) sens_103993_l3_i (
.pclk (pclk), // output
.sns_dp (sns_dp), // input[2:0]
.sns_dn (sns_dn), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.pxd_out (pxd), // output[15:0]
.vsync (vsync), // output
.hsync (hsync), // output
.dvalid (dvalid_w), // output
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r[23:0]), // input[23:0]
.set_idelay ({NUMLANES{set_idelays}}),// input[2:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
.rst_mmcm (rst_mmcm), // input
.perr (perr), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pclk), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
mpullup i_senspgm_pullup (sns_pgm);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_pgm_i (
.O (senspgmin), // output
.IO (sns_pgm), // inout
.I (1'b0), // input
.T (1'b1) // input
);
// generate ext_sync
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_sync_i (
.O (sns_ext_sync), // output
.I (ext_sync) // input
);
// generate MRST
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) sns_mrst_i (
.O (sns_mrst), // output
.I (imrst) // input
);
// General purpose I/O - reserved for future use
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp0_i (
.O (gp[0]), // output
.IO (sns_gp0), // inout
.I (gp_r[1]), // input
.T (~|gp_r[1:0]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp1_i (
.O (gp[1]), // output
.IO (sns_gp1), // inout
.I (gp_r[3]), // input
.T (~|gp_r[3:2]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp2_i (
.O (gp[2]), // output
.IO (sns_gp2), // inout
.I (gp_r[5]), // input
.T (~|gp_r[5:4]) // input
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) gp3_i (
.O (gp[3]), // output
.IO (sns_gp3), // inout
.I (gp_r[7]), // input
.T (~|gp_r[7:6]) // input
);
// READ RXD
ibuf_ibufg #(
.CAPACITANCE (PXD_CAPACITANCE),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD (PXD_IOSTANDARD)
) rxd_i (
.O(rxd), // output
.I(sns_rxd) // input
);
// generate TXD
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) txd_i (
.O (sns_txd), // output
.I (txd) // input
);
// perr - cross clocks
pulse_cross_clock perr_mclk_i (
.rst (1'b0), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (perr), // input
.out_pulse (perr_mclk), // output
.busy () // output
);
// just to verify hact is active
pulse_cross_clock hact_mclk_i (
.rst (1'b0), // input
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (dvalid_w && !dvalid_r), // input
.out_pulse (hact_mclk), // output
.busy () // output
);
endmodule
sensor/sens_103993_clock.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_hispi_clock
* @file sens_103993_clock.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Recover iclk/iclk2x from the 103993 differntial clock
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// Used with delay
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [7:0] phase,
input set_phase,
input load, // only used when delay, not phase
input rst_mmcm,
input clp_p,
input clk_n,
// output ipclk, // 165 MHz
output ipclk2x, // 330 MHz
output pclk, // 27 MHz
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire pclk_pre;
wire ipclk2x_pre; // output
wire clk_fb;
wire prst = mrst;
wire clk_in;
wire clk_int;
wire set_phase_w = (LVDS_DELAY_CLK == "TRUE") ? 1'b0: set_phase;
wire [7:0] phase_w = (LVDS_DELAY_CLK == "TRUE") ? 8'b0: phase;
wire ps_rdy_w;
wire [7:0] ps_out_w;
assign ps_rdy = (LVDS_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (LVDS_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
generate
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (clk_int), // output
.I (clp_p), // input
.IB (clk_n) // input
);
end
endgenerate
generate
if (LVDS_DELAY_CLK == "TRUE") begin
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) clk_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_phase),
.ld (load),
.delay (phase[4:0]),
.data_in (clk_int),
.data_out (clk_in)
);
end else begin
assign clk_in = clk_int;
end
endgenerate
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor)
generate
if (LVDS_MMCM == "TRUE") begin
mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("TRUE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
.SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin1 (clk_in), // input 27MHz
.clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.psclk (mclk), // input
.ps_we (set_phase_w), // input
.ps_din (phase_w), // input[7:0]
.ps_ready (ps_rdy_w), // output
.ps_dout (ps_out_w), // output[7:0] reg
.clkout0 (pclk_pre), // output -> 27MHz
.clkout1 (ipclk2x_pre), // output 270Mhz
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkout6(), // output
.clkout0b(), // output
.clkout1b(), // output
.clkout2b(), // output
.clkout3b(), // output
.clkfbout (clk_fb), // output
.clkfboutb(), // output
.locked (locked_pxd_mmcm),
.clkin_stopped (clkin_pxd_stopped_mmcm), // output
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output
);
end else begin
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT_SENSOR), // 30
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.REF_JITTER1 (SENS_REF_JITTER1),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin (clk_in), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (pclk_pre), // output -> 27MHz
.clkout1 (ipclk2x_pre), // output 270Mhz
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout (clk_fb), // output
.locked (locked_pxd_mmcm)
// output
);
assign clkin_pxd_stopped_mmcm = 0;
assign clkfb_pxd_stopped_mmcm = 0;
assign ps_rdy_w = 1;
assign ps_out_w = 0; // alternatively - register delay written
end
endgenerate
generate
if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
else assign ipclk2x = ipclk2x_pre;
endgenerate
generate
if (BUF_PCLK == "BUFG") BUFG clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFH") BUFH clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFR") BUFR clk2x_i (.O(pclk), .I(pclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_PCLK == "BUFMR") BUFMR clk2x_i (.O(pclk), .I(pclk_pre));
else if (BUF_PCLK == "BUFIO") BUFIO clk2x_i (.O(pclk), .I(pclk_pre));
else assign pclk = pclk_pre;
endgenerate
endmodule
sensor/sens_103993_deser10.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> sens_103993_deser10
* @file sens_103993_deser10.v
* @date 2020-12-16
* @author eyesis
*
* @brief 10:1 deserializer for 103993 (270MHz->27MHz)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_103993_deser10.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_deser10.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_deser10(
input pclk10,
input pclk,
input din,
output [9:0] dout
);
reg [9:0] sr;
reg [9:0] dout_r;
assign dout = dout_r;
always @(posedge pclk10) begin
sr <= {sr[8:0], din};
end
always @(posedge pclk) begin
dout_r <= sr;
end
endmodule
sensor/sens_103993_din.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993_din
* @file sens_hispi_din.v
* @date 2020-12-16
* @author Andrey Filippov
*
* @brief Input differential receivers for HiSPi lanes
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993_din.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_din.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module sens_103993_din #(
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter NUMLANES = 3,
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)(
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input pclk, // 27 MHz
// input ipclk, // 165 MHz
input ipclk2x, // 330 MHz
// input irst, // reset @posedge iclk
input [NUMLANES-1:0] din_p,
input [NUMLANES-1:0] din_n,
output [NUMLANES * 10-1:0] dout
);
wire [NUMLANES-1:0] din;
wire [NUMLANES-1:0] din_dly;
generate
genvar i;
for (i=0; i < NUMLANES; i=i+1) begin: din_block
if (LVDS_UNTUNED_SPLIT == "TRUE") begin
ibufds_ibufgds_50 #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end else begin
ibufds_ibufgds #(
.CAPACITANCE (LVDS_CAPACITANCE),
.DIFF_TERM (LVDS_DIFF_TERM),
.DQS_BIAS (LVDS_DQS_BIAS),
.IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.IOSTANDARD (LVDS_IOSTANDARD)
) ibufds_ibufgds0_i (
.O (din[i]), // output
.I (din_p[i]), // input
.IB (din_n[i]) // input
);
end
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) pxd_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_idelay[i]),
.ld (ld_idelay),
.delay (dly_data[3 + 8*i +: 5]),
.data_in (din[i]),
.data_out (din_dly[i])
);
sens_103993_deser10 sens_103993_deser10_i (
.pclk10 (ipclk2x), // input
.pclk (pclk), // input
.din (din_dly[i]), // input
.dout (dout[10*i +: 10]) // output[9:0]
);
end
endgenerate
endmodule
sensor/sens_103993_l3.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b>sens_103993_l3
* @file sens_hispi12l4.v
* @date 2015-10-13
* @author Andrey Filippov
*
* @brief data from 103993 over 3 lanes
*
* @copyright Copyright (c) 2020 Elphel, Inc .
*
* <b>License:</b>
*
* sens_103993_l3.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_103993_l3.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`define MON_HISPI // moved to system_defines
module sens_103993_l3#(
parameter IODELAY_GRP = "IODELAY_SENSOR",
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter PCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter BUF_PCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter NUMLANES = 3,
parameter LVDS_DELAY_CLK = "FALSE",
parameter LVDS_MMCM = "TRUE",
parameter LVDS_CAPACITANCE = "DONT_CARE",
parameter LVDS_DIFF_TERM = "TRUE",
parameter LVDS_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter LVDS_DQS_BIAS = "TRUE",
parameter LVDS_IBUF_DELAY_VALUE = "0",
parameter LVDS_IBUF_LOW_PWR = "TRUE",
parameter LVDS_IFD_DELAY_VALUE = "AUTO",
parameter LVDS_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
)(
output pclk, // global clock input, pixel rate (27MHz for 103993) (220MHz for MT9F002)
// I/O pads
input [NUMLANES-1:0] sns_dp,
input [NUMLANES-1:0] sns_dn,
input sns_clkp,
input sns_clkn,
// output
output [15:0] pxd_out,
output vsync,
output hsync,
output dvalid,
// delay control inputs
input mclk,
input mrst,
input [NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input [NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idelay value
input set_clk_phase, // mclk synchronous set idelay value
input rst_mmcm,
// MMCP output status
output perr, // parity error
output ps_rdy, // output
output [7:0] ps_out, // output[7:0] reg
output locked_pxd_mmcm,
output clkin_pxd_stopped_mmcm, // output
output clkfb_pxd_stopped_mmcm // output
);
wire ipclk2x;// re-generated HiSPi clock (270 MHa) 330 MHz)
wire [NUMLANES * 10-1:0] sns_d;
reg [15:0] pxd_out_r;
reg vsync_r;
reg hsync_r;
reg dvalid_r;
reg perr_r;
reg cp_r;
assign pxd_out = pxd_out_r;
assign vsync = vsync_r;
assign hsync = hsync_r;
assign dvalid = dvalid_r;
assign perr = perr_r;
sens_103993_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (PCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_PCLK),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.LVDS_DELAY_CLK (LVDS_DELAY_CLK),
.LVDS_MMCM (LVDS_MMCM),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD)
) sens_103993_clock_i (
.mclk (mclk), // input
.mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input
.load (ld_idelay), // input
.rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input
.pclk (pclk), // output 27MHz
.ipclk2x (ipclk2x), // output
.ps_rdy (ps_rdy), // output
.ps_out (ps_out), // output[7:0]
.locked_pxd_mmcm (locked_pxd_mmcm), // output
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
);
sens_103993_din #(
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.NUMLANES (NUMLANES),
.LVDS_CAPACITANCE (LVDS_CAPACITANCE),
.LVDS_DIFF_TERM (LVDS_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (LVDS_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (LVDS_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (LVDS_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (LVDS_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (LVDS_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (LVDS_IOSTANDARD)
) sens_103993_din_i (
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (dly_data), // input[31:0]
.set_idelay (set_idelay), // input[3:0]
.ld_idelay (ld_idelay), // input
.pclk (pclk), // input
.ipclk2x (ipclk2x), // input
.din_p (sns_dp), // input[2:0]
.din_n (sns_dn), // input[2:0]
.dout (sns_d) // output[29:0]
);
always @(posedge pclk) begin
pxd_out_r <= {sns_d[19:12],sns_d[9:2]};
vsync_r <= sns_d[1]; // input - active high
hsync_r <= sns_d[11]; // input - active high
dvalid_r <= sns_d[21]; // input - active hight
cp_r <= sns_d [0];
perr_r <= ~ cp_r ^ (^pxd_out_r) ^ vsync_r ^ hsync_r ^ dvalid_r;
end
endmodule
sensor/sens_boson.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> sens_boson
* @file sens_boson.v
* @date 2020-12-14
* @author eyesis
*
* @brief senosr port for Boson LWIR sensor
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* sens_boson.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sens_boson.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`include "system_defines.vh" // just for debugging histograms
module sens_boson#(
parameter SENSIO_ADDR = 'h330,
parameter SENSIO_ADDR_MASK = 'h7f8,
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_STATUS_REG = 'h21
)(
);
endmodule
sensor/sens_parallel12.v
View file @ 043d4849
...@@ -68,12 +68,12 @@ module sens_parallel12 #( ...@@ -68,12 +68,12 @@ module sens_parallel12 #(
parameter LINE_WIDTH_BITS = 16, parameter LINE_WIDTH_BITS = 16,
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT", parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE", parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
......
sensor/sensor_channel.v
View file @ 043d4849
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* *
* @brief Top module for a sensor channel * @brief Top module for a sensor channel
* *
* @copyright Copyright (c) 2015 Elphel, Inc. * @copyright Copyright (c) 2015-2020 Elphel, Inc.
* *
* <b>License:</b> * <b>License:</b>
* *
...@@ -41,7 +41,8 @@ ...@@ -41,7 +41,8 @@
module sensor_channel#( module sensor_channel#(
// parameters, individual to sensor channels and those likely to be modified // parameters, individual to sensor channels and those likely to be modified
parameter SENSOR_NUMBER = 0, // sensor number (0..3) // Moving to the end to be always present
// parameter SENSOR_NUMBER = 0, // sensor number (0..3)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x30, x32, x34, x36 parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x30, x32, x34, x36
...@@ -111,7 +112,9 @@ module sensor_channel#( ...@@ -111,7 +112,9 @@ module sensor_channel#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period) parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8, parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter SENSI2C_STATUS = 'h1, parameter SENSI2C_STATUS = 'h1,
parameter SENS_GAMMA_RADDR = 'h38, //4, 'h38..'h3b parameter SENS_GAMMA_RADDR = 'h38, //4, 'h38..'h3b
...@@ -157,45 +160,78 @@ module sensor_channel#( ...@@ -157,45 +160,78 @@ module sensor_channel#(
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8, parameter SENSIO_ADDR_MASK = 'h7f8,
`ifdef LWIR
parameter SENSIO_CTRL = 'h0,
parameter SENSIO_STATUS = 'h1, parameter SENSIO_STATUS = 'h1,
`else parameter SENSIO_CTRL = 'h0,
`ifdef LWIR
// parameter SENSIO_CTRL = 'h0,
// parameter SENSIO_STATUS = 'h1,
`else // all not LWIR
// sens_parallel12 registers // sens_parallel12 registers
parameter SENSIO_CTRL = 'h0, // parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits // SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0 parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2 `ifndef BOSON
parameter SENS_CTRL_ARO = 4, // 5: 4 parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6 parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENSIO_JTAG = 'h2, // not used for BOSON:
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`endif
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
parameter SENS_CTRL_LD_DLY = 10, // 10
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`endif // `ifdef LWIR / else
`ifdef HISPI `ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8 parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`else `elsif PAR12
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8 parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif `endif
parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI `ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12 parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15 parameter SENS_CTRL_GP1= 15, // 17:15
`else `elsif BOSON
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6, parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_ODD = 6, // parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved) parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
`elsif PAR12
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
parameter SENS_CTRL_ODD = 6, //
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
`endif `endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2, `ifdef PAR12
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif `endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`ifdef HISPI `ifdef HISPI
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
parameter SENSOR_TIMING_START = 16, // bit # in JTAB control word to start timing measurement (now f = 660/4 = 165)
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
/*
`elsif BOSON
`ifdef MON_HISPI `ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43 parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
...@@ -205,8 +241,10 @@ module sensor_channel#( ...@@ -205,8 +241,10 @@ module sensor_channel#(
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif `endif
`endif */
`endif `endif //`ifdef HISPI
//// `endif // seems to be extra?
// 4 of 8-bit delays per register // 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR) // sensor_i2c_io command/data write registers s (relative to SENSOR_BASE_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
...@@ -231,8 +269,7 @@ module sensor_channel#( ...@@ -231,8 +269,7 @@ module sensor_channel#(
parameter NUM_FRAME_BITS = 4, parameter NUM_FRAME_BITS = 4,
`ifdef HISPI `ifdef LWIR
`elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16) parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE", parameter VOSPI_IBUF_LOW_PWR = "TRUE",
parameter VOSPI_IOSTANDARD = "LVCMOS25", parameter VOSPI_IOSTANDARD = "LVCMOS25",
...@@ -278,38 +315,50 @@ module sensor_channel#( ...@@ -278,38 +315,50 @@ module sensor_channel#(
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap) parameter VOSPI_MRST_MS = 200, // master reset duration in ms (so even all channels would overlap)
parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer parameter VOSPI_MRST_AFTER_MS = 2000, // Wait after master reset and generate SOF pulse to advance sequencer
parameter VOSPI_SPI_TIMEOUT_MS = 185 // Wait to tymeout SPI when needed to re-sync parameter VOSPI_SPI_TIMEOUT_MS = 185, // Wait to tymeout SPI when needed to re-sync
`else `elsif PAR12
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7, parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif `endif
// start with comma! // start with comma!
`ifdef LWIR `ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS25" parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`else `elsif HISPI
// sens_parallel12 other parameters
,parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE", parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4, parameter PXD_CLK_DIV_BITS = 4,
//`else //`else
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps // parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
`elsif BOSON
parameter PXD_CAPACITANCE = "DONT_CARE",
// parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
// parameter PXD_CLK_DIV_BITS = 4,
`elsif PAR12
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
// parameter integer IDELAY_VALUE = 0,
/// parameter integer PXD_DRIVE = 12,
/// parameter PXD_IBUF_LOW_PWR = "TRUE",
/// parameter PXD_SLEW = "SLOW",
// parameter real SENS_REFCLK_FREQUENCY = 300.0,
// parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`endif `endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`ifdef LWIR
`else
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW",
parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real SENS_REFCLK_FREQUENCY = 200, // was300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for the phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`endif
// parameters for the sensor-synchronous clock PLL // parameters for the sensor-synchronous clock PLL
`ifdef HISPI `ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
...@@ -319,7 +368,16 @@ module sensor_channel#( ...@@ -319,7 +368,16 @@ module sensor_channel#(
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18", parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18", parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `elsif BOSON
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
//IPCLK* will be used as PCLK*
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif PAR12 // no LWIR
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
...@@ -329,21 +387,22 @@ module sensor_channel#( ...@@ -329,21 +387,22 @@ module sensor_channel#(
parameter SENSI2C_IOSTANDARD = "LVCMOS25", parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
`ifdef LWIR
`else // all but LWIR
parameter BUF_IPCLK = "BUFR", parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR", parameter BUF_IPCLK2X = "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999) parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010, parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
`endif `endif
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE", parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE", parameter HISPI_MMCM = "TRUE",
...@@ -358,16 +417,39 @@ module sensor_channel#( ...@@ -358,16 +417,39 @@ module sensor_channel#(
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA) parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`elsif BOSON
// ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 3,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
// parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter HISPI_FIFO_DEPTH = 4,
// parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 parameter DEBUG_CMD_LATENCY = 2,
`endif `endif
// parameter real REFCLK_FREQUENCY = 200.0,
// parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENSOR_NUMBER = 0 // sensor number (0..3)
) ( ) (
`ifdef PCLK_MASTER // for Boson
output pclk,
output locked_pclk,
`else
input pclk, // global clock input, pixel rate (96MHz for MT9P006) input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`endif
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones) // TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase? // How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame? // Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
...@@ -386,6 +468,13 @@ module sensor_channel#( ...@@ -386,6 +468,13 @@ module sensor_channel#(
inout [7:4] sns_dn74, inout [7:4] sns_dn74,
input sns_clkp, input sns_clkp,
input sns_clkn, input sns_clkn,
`elsif BOSON
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp,
input sns_clkn,
`elsif LWIR `elsif LWIR
inout [ 4:0] sns_dp40, inout [ 4:0] sns_dp40,
inout [ 4:0] sns_dn40, inout [ 4:0] sns_dn40,
...@@ -395,8 +484,7 @@ module sensor_channel#( ...@@ -395,8 +484,7 @@ module sensor_channel#(
inout [ 7:6] sns_dn76, inout [ 7:6] sns_dn76,
input sns_clkp, input sns_clkp,
input sns_clkn, input sns_clkn,
`elsif PAR12
`else
inout [7:0] sns_dp, inout [7:0] sns_dp,
inout [7:0] sns_dn, inout [7:0] sns_dn,
inout sns_clkp, inout sns_clkp,
...@@ -406,7 +494,11 @@ module sensor_channel#( ...@@ -406,7 +494,11 @@ module sensor_channel#(
inout sns_sda, inout sns_sda,
`ifdef HISPI `ifdef HISPI
output sns_ctl, output sns_ctl,
`else `elsif BOSON
output sns_ctl,
`elsif LWIR
inout sns_ctl,
`elsif PAR12
inout sns_ctl, inout sns_ctl,
`endif `endif
inout sns_pg, inout sns_pg,
...@@ -445,10 +537,10 @@ module sensor_channel#( ...@@ -445,10 +537,10 @@ module sensor_channel#(
,input ext_rst_in, ,input ext_rst_in,
input ext_rstseq_in, input ext_rstseq_in,
output ext_rst_out, output ext_rst_out,
output ext_rstseq_out output ext_rstseq_out,
`endif
// currently used only for LWIR // currently used only for LWIR
,input khz // 1 KHz 50% @mclk input khz // 1 KHz 50% @mclk
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -481,6 +573,12 @@ module sensor_channel#( ...@@ -481,6 +573,12 @@ module sensor_channel#(
`ifdef MON_HISPI `ifdef MON_HISPI
localparam SENSOR_TIMING_STATUS_REG = (SENSOR_TIMING_STATUS_REG_BASE + SENSOR_NUMBER * SENSOR_TIMING_STATUS_REG_INC); localparam SENSOR_TIMING_STATUS_REG = (SENSOR_TIMING_STATUS_REG_BASE + SENSOR_NUMBER * SENSOR_TIMING_STATUS_REG_INC);
`endif `endif
/*
`elsif BOSON
`ifdef MON_HISPI
localparam SENSOR_TIMING_STATUS_REG = (SENSOR_TIMING_STATUS_REG_BASE + SENSOR_NUMBER * SENSOR_TIMING_STATUS_REG_INC);
`endif
*/
`endif `endif
localparam SENS_SYNC_ADDR = SENSOR_BASE_ADDR + SENS_SYNC_RADDR; localparam SENS_SYNC_ADDR = SENSOR_BASE_ADDR + SENS_SYNC_RADDR;
// parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address // parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address
...@@ -506,19 +604,33 @@ module sensor_channel#( ...@@ -506,19 +604,33 @@ module sensor_channel#(
wire [7:0] sens_phys_status_ad; wire [7:0] sens_phys_status_ad;
wire sens_phys_status_rq; wire sens_phys_status_rq;
wire sens_phys_status_start; wire sens_phys_status_start;
`ifndef HISPI `ifdef PAR12
`ifndef LWIR
wire ipclk; // Use in FIFO wire ipclk; // Use in FIFO
wire [11:0] pxd_to_fifo; wire [11:0] pxd_to_fifo;
wire vact_to_fifo; // frame active @posedge ipclk wire vact_to_fifo; // frame active @posedge ipclk
wire hact_to_fifo; // line active @posedge ipclk wire hact_to_fifo; // line active @posedge ipclk
`endif
`endif `endif
// only used for Boson
`ifdef BOSON
wire extif_dav; // data byte available for external interface
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
wire [1:0] extif_sel; // interface type (0 - internal, 1 - uart, 2,3 - reserved)
wire [7:0] extif_byte; // data to external interface (first - extif_sa)
wire extif_ready;// acknowledges extif_dav
wire extif_rst; // reset interface from i2c modulet
`endif
// data from FIFO // data from FIFO
`ifdef LWIR `ifdef LWIR
wire [15:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk wire [15:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`else `elsif BOSON
wire [15:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`elsif HISPI
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`elsif PAR12
wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk wire [11:0] pxd; // TODO: align MSB? parallel data, @posedge ipclk
`endif `endif
wire hact; // line active @posedge ipclk wire hact; // line active @posedge ipclk
...@@ -608,18 +720,18 @@ module sensor_channel#( ...@@ -608,18 +720,18 @@ module sensor_channel#(
`ifdef DEBUG_RING `ifdef DEBUG_RING
`ifdef HISPI `ifdef HISPI
`elsif BOSON
`elsif LWIR `elsif LWIR
`elsif PAR12
`else
reg vact_to_fifo_r; reg vact_to_fifo_r;
`endif `endif
`ifdef LWIR `ifdef LWIR
// reg hact_to_fifo_r; // reg hact_to_fifo_r;
reg [15:0] debug_line_cntr = 0; reg [15:0] debug_line_cntr = 0;
reg [15:0] debug_lines = 0; reg [15:0] debug_lines = 0;
reg [15:0] hact_cntr = 0; reg [15:0] hact_cntr = 0;
// reg [15:0] vact_cntr; // reg [15:0] vact_cntr;
`else `else
reg hact_to_fifo_r; reg hact_to_fifo_r;
reg [15:0] debug_line_cntr; reg [15:0] debug_line_cntr;
reg [15:0] debug_lines; reg [15:0] debug_lines;
...@@ -642,6 +754,23 @@ module sensor_channel#( ...@@ -642,6 +754,23 @@ module sensor_channel#(
if (prst) vact_cntr <= 0; if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1; else if (sof) vact_cntr <= vact_cntr + 1;
end
`elsif BOSON
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
hact_to_fifo_r <= hact;
if (sof) debug_line_cntr <= 0;
else if (hact && !hact_to_fifo_r) debug_line_cntr <= debug_line_cntr + 1;
if (sof) debug_lines <= debug_line_cntr;
if (prst) hact_cntr <= 0;
else if (hact && !hact_to_fifo_r) hact_cntr <= hact_cntr + 1;
if (prst) vact_cntr <= 0;
else if (sof) vact_cntr <= vact_cntr + 1;
end end
`elsif LWIR `elsif LWIR
// Something here? // Something here?
...@@ -683,6 +812,8 @@ module sensor_channel#( ...@@ -683,6 +812,8 @@ module sensor_channel#(
12'b0, 12'b0,
`elsif LWIR `elsif LWIR
12'b0, 12'b0,
`elsif BOSON
12'b0,
`else `else
pxd_to_fifo[11:0], pxd_to_fifo[11:0],
`endif `endif
...@@ -795,6 +926,8 @@ module sensor_channel#( ...@@ -795,6 +926,8 @@ module sensor_channel#(
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) .SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period) .SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS), .SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS),
.SENSI2C_DRIVE (SENSI2C_DRIVE), .SENSI2C_DRIVE (SENSI2C_DRIVE),
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR), .SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD), .SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
...@@ -813,13 +946,30 @@ module sensor_channel#( ...@@ -813,13 +946,30 @@ module sensor_channel#(
// division as in sof_out_mclk // division as in sof_out_mclk
.frame_num_seq (frame_num_seq), // input[3:0] .frame_num_seq (frame_num_seq), // input[3:0]
.scl (sns_scl), // inout .scl (sns_scl), // inout
.sda (sns_sda) // inout .sda (sns_sda), // inout
// interface for uart in write-only mode for short commands
`ifdef BOSON
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready), // input
.extif_rst (extif_rst) // output
`else
.extif_dav (), // output
// .extif_last (), // output
.extif_sel (), // output[1:0]
.extif_byte (), // output[7:0]
.extif_ready (1'b0), // input
.extif_rst () // output
`endif
); );
// debug_hist_mclk is never active, alive_hist0_rq == 0 // debug_hist_mclk is never active, alive_hist0_rq == 0
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk}; // assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, alive_hist0_gr, alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
// assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk}; // assign status_alive = {last_in_line_1cyc_mclk, dout_valid_1cyc_mclk, debug_hist_mclk[0], alive_hist0_rq, sof_out_mclk, eof_mclk, sof_mclk, sol_mclk};
`ifndef HISPI `ifndef HISPI
`ifndef BOSON
localparam STATUS_ALIVE_WIDTH = 8; localparam STATUS_ALIVE_WIDTH = 8;
`ifndef LWIR `ifndef LWIR
reg hact_r; // hact delayed by 1 cycle to generate start pulse reg hact_r; // hact delayed by 1 cycle to generate start pulse
...@@ -893,7 +1043,8 @@ module sensor_channel#( ...@@ -893,7 +1043,8 @@ module sensor_channel#(
.busy() // output .busy() // output
); );
`endif `endif
`endif `endif // `ifndef BOSON
`endif // `ifndef HISPI
//`ifndef LWIR //`ifndef LWIR
pulse_cross_clock pulse_cross_clock_eof_mclk_i ( pulse_cross_clock pulse_cross_clock_eof_mclk_i (
...@@ -916,14 +1067,14 @@ module sensor_channel#( ...@@ -916,14 +1067,14 @@ module sensor_channel#(
.SENSIO_JTAG (SENSIO_JTAG), .SENSIO_JTAG (SENSIO_JTAG),
.SENSIO_DELAYS (SENSIO_DELAYS), .SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG), .SENSIO_STATUS_REG (SENSIO_STATUS_REG),
`ifdef MON_HISPI `ifdef MON_HISPI
.SENSOR_TIMING_BITS (SENSOR_TIMING_BITS), .SENSOR_TIMING_BITS (SENSOR_TIMING_BITS),
.TIM_START (SENSOR_TIMING_START), .TIM_START (SENSOR_TIMING_START),
.TIM_LANE (SENSOR_TIMING_LANE), .TIM_LANE (SENSOR_TIMING_LANE),
.TIM_FROM (SENSOR_TIMING_FROM), .TIM_FROM (SENSOR_TIMING_FROM),
.TIM_TO (SENSOR_TIMING_TO), .TIM_TO (SENSOR_TIMING_TO),
.SENSOR_TIMING_STATUS_REG(SENSOR_TIMING_STATUS_REG), // localparam .SENSOR_TIMING_STATUS_REG(SENSOR_TIMING_STATUS_REG), // localparam
`endif `endif
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN), .SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG), .SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK), .SENS_JTAG_TCK (SENS_JTAG_TCK),
...@@ -1012,6 +1163,109 @@ module sensor_channel#( ...@@ -1012,6 +1163,109 @@ module sensor_channel#(
.sof (sof), // output .sof (sof), // output
.eof (eof) // output .eof (eof) // output
); );
`elsif BOSON
wire vsync;
wire dvalid;
sens_103993 #(
.SENSIO_ADDR (SENSIO_ADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.PCLK_PHASE (IPCLK_PHASE), // use IPCLK* for PCLK*
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_PCLK (BUF_IPCLK), // use IPCLK* for PCLK*
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.NUMLANES (HISPI_NUMLANES),
.LVDS_DELAY_CLK (HISPI_DELAY_CLK),
.LVDS_MMCM (HISPI_MMCM),
.LVDS_CAPACITANCE (HISPI_CAPACITANCE),
.LVDS_DIFF_TERM (HISPI_DIFF_TERM),
.LVDS_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.LVDS_DQS_BIAS (HISPI_DQS_BIAS),
.LVDS_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.LVDS_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.LVDS_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.LVDS_IOSTANDARD (HISPI_IOSTANDARD),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.PXD_CAPACITANCE (PXD_CAPACITANCE)
) sens_103993_i (
.pclk (pclk), // output
.locked_pclk (locked_pclk), // output
.prst (prst), // input
.prsts (prsts), // output
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_ad), // input[7:0]
.cmd_stb (cmd_stb), // input
.status_ad (sens_phys_status_ad), // output[7:0]
.status_rq (sens_phys_status_rq), // output
.status_start (sens_phys_status_start), // input
// .trigger_mode (trigger_mode), // input
.ext_sync (trig), // input
.sns_dp (sns_dp[2:0]), // input[2:0]
.sns_dn (sns_dn[2:0]), // input[2:0]
.sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input
.sns_gp2 (sns_dn74[6]), // inout
.sns_pgm (sns_pg), // inout
.sns_ext_sync (sns_ctl), // output
.sns_mrst (sns_dp74[7]), // output
.sns_gp3 (sns_dn74[7]), // output
.sns_gp0 (sns_dp74[5]), // output
.sns_gp1 (sns_dn74[5]), // output
.sns_txd (sns_dp74[4]), // input
.sns_rxd (sns_dn74[4]), // input
.pxd (pxd), // output[11:0]
.vsync (vsync), // output
.hsync (), // hsync), // output
.dvalid (dvalid), // output
// interface for uart in write-only mode for short commands
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst) // input
);
reg vsync_d;
always @(posedge pclk) begin
vsync_d <= vsync;
end
assign sof = vsync && !vsync_d;
assign eof = !vsync && vsync_d;
assign hact = dvalid;
`elsif LWIR `elsif LWIR
sens_lepton3 #( sens_lepton3 #(
.SENSIO_ADDR (SENSIO_ADDR), .SENSIO_ADDR (SENSIO_ADDR),
...@@ -1099,9 +1353,9 @@ module sensor_channel#( ...@@ -1099,9 +1353,9 @@ module sensor_channel#(
.dn2 (sns_dn40[2]), // input reserved .dn2 (sns_dn40[2]), // input reserved
.dn6 (sns_dn76[6]), // input reserved .dn6 (sns_dn76[6]), // input reserved
// reset synchronization // reset synchronization
.ext_rst_in (ext_rst_in), // input .ext_rst_in (ext_rst_in), // input
.ext_rstseq_in (ext_rstseq_in), // input .ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out), // output .ext_rst_out (ext_rst_out), // output
.ext_rstseq_out (ext_rstseq_out), // output .ext_rstseq_out (ext_rstseq_out), // output
.khz (khz) // input 1 KHz 50% duty @ mclk .khz (khz) // input 1 KHz 50% duty @ mclk
); );
...@@ -1133,11 +1387,11 @@ module sensor_channel#( ...@@ -1133,11 +1387,11 @@ module sensor_channel#(
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH), .SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN), .SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE), .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH), .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
...@@ -1190,7 +1444,7 @@ module sensor_channel#( ...@@ -1190,7 +1444,7 @@ module sensor_channel#(
.status_start (sens_phys_status_start) // input .status_start (sens_phys_status_start) // input
); );
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the // TODO NC393: This delay may be too long for serial sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
// just continue. // just continue.
......
sensor/sensor_i2c.v
View file @ 043d4849
...@@ -74,6 +74,8 @@ module sensor_i2c#( ...@@ -74,6 +74,8 @@ module sensor_i2c#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period) parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8, parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
parameter NUM_FRAME_BITS = 4 parameter NUM_FRAME_BITS = 4
)( )(
input mrst, // @ posedge mclk input mrst, // @ posedge mclk
...@@ -95,10 +97,14 @@ module sensor_i2c#( ...@@ -95,10 +97,14 @@ module sensor_i2c#(
output scl_out, // i2c SCL output output scl_out, // i2c SCL output
output sda_out, // i2c SDA output output sda_out, // i2c SDA output
output scl_en, // i2c SCL enable output scl_en, // i2c SCL enable
output sda_en // i2c SDA enable output sda_en, // i2c SDA enable
// output busy, // interface for uart in write-only mode for short commands
// output [3:0] frame_num output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready, // acknowledges extif_dav
output extif_rst
); );
// TODO: Make sure that using more than 64 commands will just send them during next frame, not loose? // TODO: Make sure that using more than 64 commands will just send them during next frame, not loose?
// 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame // 0x0..0xf write directly to the frame number [3:0] modulo 16, except if you write to the frame
...@@ -116,12 +122,12 @@ module sensor_i2c#( ...@@ -116,12 +122,12 @@ module sensor_i2c#(
// [8] - set duration of quarter i2c cycle in system clock cycles - nominal value 100 (0x64) // [8] - set duration of quarter i2c cycle in system clock cycles - nominal value 100 (0x64)
// [7:0] - duration of quater i2c cycle (applied if [8] is set) // [7:0] - duration of quater i2c cycle (applied if [8] is set)
wire we_abs; wire we_abs;
wire we_rel; wire we_rel;
wire we_cmd; wire we_cmd;
wire wen; wire wen;
wire [31:0] di; wire [31:0] di;
wire [3:0] wa; wire [3:0] wa;
reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long reg [31:0] di_r; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
reg [3:0] wpage0; // FIFO page where ASAP writes go reg [3:0] wpage0; // FIFO page where ASAP writes go
reg [3:0] wpage_prev; // unused page, currently being cleared reg [3:0] wpage_prev; // unused page, currently being cleared
...@@ -230,7 +236,7 @@ module sensor_i2c#( ...@@ -230,7 +236,7 @@ module sensor_i2c#(
assign sda_out = i2c_enrun? sda_hard: sda_soft ; assign sda_out = i2c_enrun? sda_hard: sda_soft ;
assign sda_en = i2c_enrun? sda_en_hard: sda_en_soft ; assign sda_en = i2c_enrun? sda_en_hard: sda_en_soft ;
assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1); assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
assign extif_rst = reset_cmd;
/* /*
reg alive_fs; reg alive_fs;
...@@ -451,7 +457,9 @@ module sensor_i2c#( ...@@ -451,7 +457,9 @@ module sensor_i2c#(
.SENSI2C_TBL_NBRD_BITS (SENSI2C_TBL_NBRD_BITS), .SENSI2C_TBL_NBRD_BITS (SENSI2C_TBL_NBRD_BITS),
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) .SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period) .SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS) .SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS)
) sensor_i2c_prot_i( ) sensor_i2c_prot_i(
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -460,7 +468,8 @@ module sensor_i2c#( ...@@ -460,7 +468,8 @@ module sensor_i2c#(
.active_sda (active_sda), // input .active_sda (active_sda), // input
.early_release_0 (early_release_0), // input .early_release_0 (early_release_0), // input
.tand (di_r[SENSI2C_CMD_TAND]), // input .tand (di_r[SENSI2C_CMD_TAND]), // input
.td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0] // .td (di_r[SENSI2C_CMD_TAND-1:0]), // input[27:0]
.td (di_r), // input[27:0]
.twe (twe), // input .twe (twe), // input
.sda_in (sda_in), // input .sda_in (sda_in), // input
.sda (sda_hard), // output .sda (sda_hard), // output
...@@ -472,7 +481,13 @@ module sensor_i2c#( ...@@ -472,7 +481,13 @@ module sensor_i2c#(
.seq_mem_re (seq_mem_re), // output[1:0] .seq_mem_re (seq_mem_re), // output[1:0]
.seq_rd (i2c_data), // input[7:0] .seq_rd (i2c_data), // input[7:0]
.rdata (i2c_rdata), // output[7:0] .rdata (i2c_rdata), // output[7:0]
.rvalid (i2c_rvalid) // output .rvalid (i2c_rvalid), // output
// interface for uart in write-only mode for short commands
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready) // input
); );
......
sensor/sensor_i2c_io.v
View file @ 043d4849
...@@ -73,6 +73,8 @@ module sensor_i2c_io#( ...@@ -73,6 +73,8 @@ module sensor_i2c_io#(
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period) parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8, parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2,
// I/O parameters // I/O parameters
parameter integer SENSI2C_DRIVE = 12, parameter integer SENSI2C_DRIVE = 12,
parameter SENSI2C_IBUF_LOW_PWR = "TRUE", parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
...@@ -95,7 +97,14 @@ module sensor_i2c_io#( ...@@ -95,7 +97,14 @@ module sensor_i2c_io#(
input eof_mclk, // End of frame for i2c sequencer (will not work for linescan mode: either disable or make division upsteram input eof_mclk, // End of frame for i2c sequencer (will not work for linescan mode: either disable or make division upsteram
input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c) input [NUM_FRAME_BITS-1:0] frame_num_seq, // frame number from the command sequencer (to sync i2c)
inout scl, inout scl,
inout sda inout sda,
// interface for uart in write-only mode for short commands
output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready, // acknowledges extif_dav
output extif_rst // reset external interface from i2c command
); );
wire scl_in; wire scl_in;
wire sda_in; wire sda_in;
...@@ -137,6 +146,8 @@ module sensor_i2c_io#( ...@@ -137,6 +146,8 @@ module sensor_i2c_io#(
.SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) .SENSI2C_TBL_NABRD (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
.SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period) .SENSI2C_TBL_DLY (SENSI2C_TBL_DLY), // bit delay (number of mclk periods in 1/4 of SCL period)
.SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS), .SENSI2C_TBL_DLY_BITS (SENSI2C_TBL_DLY_BITS),
.SENSI2C_TBL_EXTIF (SENSI2C_TBL_EXTIF),
.SENSI2C_TBL_EXTIF_BITS (SENSI2C_TBL_EXTIF_BITS),
.NUM_FRAME_BITS (NUM_FRAME_BITS) .NUM_FRAME_BITS (NUM_FRAME_BITS)
) sensor_i2c_i ( ) sensor_i2c_i (
.mrst (mrst), // input .mrst (mrst), // input
...@@ -154,7 +165,14 @@ module sensor_i2c_io#( ...@@ -154,7 +165,14 @@ module sensor_i2c_io#(
.scl_out (scl_out), // output .scl_out (scl_out), // output
.sda_out (sda_out), // output .sda_out (sda_out), // output
.scl_en (scl_en), // output .scl_en (scl_en), // output
.sda_en (sda_en) // output .sda_en (sda_en), // output
// interface for uart in write-only mode for short commands
.extif_dav (extif_dav), // output
// .extif_last (extif_last), // output
.extif_sel (extif_sel), // output[1:0]
.extif_byte (extif_byte), // output[7:0]
.extif_ready (extif_ready), // input
.extif_rst (extif_rst) // output
); );
iobuf #( iobuf #(
......
sensor/sensor_i2c_prot.v
View file @ 043d4849
...@@ -50,7 +50,9 @@ module sensor_i2c_prot#( ...@@ -50,7 +50,9 @@ module sensor_i2c_prot#(
parameter SENSI2C_TBL_NBRD_BITS = 3, parameter SENSI2C_TBL_NBRD_BITS = 3,
parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes) parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period) parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
parameter SENSI2C_TBL_DLY_BITS= 8 parameter SENSI2C_TBL_DLY_BITS= 8,
parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
parameter SENSI2C_TBL_EXTIF_BITS= 2
)( )(
input mrst, // @ posedge mclk input mrst, // @ posedge mclk
input mclk, // global clock input mclk, // global clock
...@@ -60,7 +62,8 @@ module sensor_i2c_prot#( ...@@ -60,7 +62,8 @@ module sensor_i2c_prot#(
input early_release_0,// global config bit: release SDA immediately after end of SCL if next bit is 1 (for ACKN). Data hold time by slow 0->1 input early_release_0,// global config bit: release SDA immediately after end of SCL if next bit is 1 (for ACKN). Data hold time by slow 0->1
// setup LUT to translate address page into SA, actual address MSB and number of bytes to write (second word bypasses translation) // setup LUT to translate address page into SA, actual address MSB and number of bytes to write (second word bypasses translation)
input tand, // table address/not data input tand, // table address/not data
input [27:0] td, // table address/data in // input [27:0] td, // table address/data in
input [31:0] td, // table address/data in
input twe, // table write enable input twe, // table write enable
input sda_in, // data from sda pad input sda_in, // data from sda pad
output sda, output sda,
...@@ -72,7 +75,15 @@ module sensor_i2c_prot#( ...@@ -72,7 +75,15 @@ module sensor_i2c_prot#(
output [ 1:0] seq_mem_re, // [0] - re, [1] - regen to the sequencer memory output [ 1:0] seq_mem_re, // [0] - re, [1] - regen to the sequencer memory
input [ 7:0] seq_rd, // data from the sequencer memory input [ 7:0] seq_rd, // data from the sequencer memory
output [ 7:0] rdata, output [ 7:0] rdata,
output rvalid output rvalid,
// interface for uart in write-only mode for short commands
// output extif_rst, // reset external uinterface - use i2c_rst
output extif_dav, // data byte available for external interface
// output extif_last, // last byte for external interface (with extif_dav)
output [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
// output [6:0] extif_sa, // "slave address" - used as extra attributes (data width) - valid during extif_run
output [7:0] extif_byte, // data to external interface (first - extif_sa)
input extif_ready // acknowledges extif_dav
); );
/* /*
Sequencer provides 4 bytes per command, read one byte at a time as seq_rd[7:0] with byte address provided by seq_mem_ra[1:0], Sequencer provides 4 bytes per command, read one byte at a time as seq_rd[7:0] with byte address provided by seq_mem_ra[1:0],
...@@ -111,27 +122,21 @@ module sensor_i2c_prot#( ...@@ -111,27 +122,21 @@ module sensor_i2c_prot#(
reg [ 6:0] run_reg_wr; // run register write [6] - start, [5] - send sa, [4] - send high byte (from table),..[0] - send stop reg [ 6:0] run_reg_wr; // run register write [6] - start, [5] - send sa, [4] - send high byte (from table),..[0] - send stop
reg [ 4:0] run_extra_wr; // continue register write (if more than sa + 4bytes) [4] - byte 3, .. [1]- byte0, [0] - stop reg [ 4:0] run_extra_wr; // continue register write (if more than sa + 4bytes) [4] - byte 3, .. [1]- byte0, [0] - stop
reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop
reg [ 4:0] run_reg_ext_wr; // [4] - SA (attr), [3] - RA_msb (module) [2] - RA_lsb (func), [1] - DH, [0] - DL (DH, DL - optional)?
reg run_extra_wr_d; // any of run_extra_wr bits, delayed by 1 reg run_extra_wr_d; // any of run_extra_wr bits, delayed by 1
reg run_any_d; // any of command states, delayed by 1 reg run_any_d; // any of command states, delayed by 1
reg [1:0] pre_cmd; // from i2c_start until run_any_d will be active reg [1:0] pre_cmd; // from i2c_start until run_any_d will be active
reg first_mem_re; reg first_mem_re;
// reg i2c_done;
// wire i2c_next_byte;
reg [ 2:0] mem_re; reg [ 2:0] mem_re;
reg mem_valid; reg mem_valid;
reg [ 2:0] table_re; reg [ 2:0] table_re;
// reg read_mem_msb; wire is_extif = (|tdout[SENSI2C_TBL_EXTIF +: SENSI2C_TBL_EXTIF_BITS]);
// wire decode_reg_rd = &seq_rd[7:4]; wire start_wr_seq_w = table_re[2] && !is_extif && !tdout[SENSI2C_TBL_RNWREG]; // [8]
// wire start_wr_seq_w = !run_extra_wr_d && !decode_reg_rd && read_mem_msb; wire start_rd_seq_w = table_re[2] && !is_extif && tdout[SENSI2C_TBL_RNWREG]; // [8]
wire start_wr_seq_w = table_re[2] && !tdout[SENSI2C_TBL_RNWREG];
wire start_rd_seq_w = table_re[2] && tdout[SENSI2C_TBL_RNWREG];
wire start_extra_seq_w = i2c_start && (bytes_left_send !=0); wire start_extra_seq_w = i2c_start && (bytes_left_send !=0);
wire start_extif_w = table_re[2] && (is_extif);
// wire snd_start_w = run_reg_wr[6] || 1'b0; // add start & restart of read
// wire snd_stop_w = run_reg_wr[0] || 1'b0; // add stop of read
// wire snd9_w = (|run_reg_wr[5:1]) || 1'b0; // add for read and extra write;
reg snd_start; reg snd_start;
reg snd_stop; reg snd_stop;
reg snd9; reg snd9;
...@@ -152,7 +157,14 @@ module sensor_i2c_prot#( ...@@ -152,7 +157,14 @@ module sensor_i2c_prot#(
reg next_cmd; // i2c command (start/stop/data) accepted, proceed to the next stage reg next_cmd; // i2c command (start/stop/data) accepted, proceed to the next stage
reg next_cmd_d; // next cycle after next_cmd (first at new state) reg next_cmd_d; // next cycle after next_cmd (first at new state)
wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy; wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy;
reg next_byte_wr; wire next_byte_wr_w;
// reg next_byte_wr;
reg next_byte_wr_or_ext; // write byte or extrenal command
reg extif_dav_r;
reg extif_run;
wire extif_next_w;
// reg extif_ackn;
wire pre_next_extif = extif_run && extif_ready && extif_dav && !next_cmd && !next_cmd_d; // TODO: Verify last terms
reg read_address_bytes; // 0 - single-byte register adderss, 1 - two-byte register address reg read_address_bytes; // 0 - single-byte register adderss, 1 - two-byte register address
reg [ 2:0] read_data_bytes; // 1..8 bytes to read from the i2c slave (0 is 8!) reg [ 2:0] read_data_bytes; // 1..8 bytes to read from the i2c slave (0 is 8!)
...@@ -163,59 +175,94 @@ module sensor_i2c_prot#( ...@@ -163,59 +175,94 @@ module sensor_i2c_prot#(
wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1]; wire pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1];
reg rnw; // last command was read (not write) - do not increment bytes_left_send reg rnw; // last command was read (not write) - do not increment bytes_left_send
// reg [ 6:0] extif_sa_r;
// wire dout_stb; // rvalid reg [ 7:0] extif_byte_r;
reg [ 1:0] extif_sel_r;
wire extif_last;
assign seq_mem_re = mem_re[1:0]; assign seq_mem_re = mem_re[1:0];
// assign rvalid = dout_stb && run_reg_rd[1]; assign next_byte_wr_w = snd9 && i2c_rdy && !run_reg_wr[5] && !rnw;
assign extif_dav = extif_dav_r;
assign extif_next_w = |run_reg_ext_wr[3:0];
// assign extif_sa = extif_sa_r;
assign extif_byte = extif_byte_r;
assign extif_sel = extif_sel_r;
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
assign extif_last = bytes_left_send == 0;
// assign extif_last = extif_last_w;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0; if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0;
else if (start_rd_seq_w) rnw <= 1; else if (start_rd_seq_w) rnw <= 1;
run_extra_wr_d <= |run_extra_wr; run_extra_wr_d <= |run_extra_wr;
run_any_d <= (|run_reg_wr) || (|run_extra_wr) || (|run_reg_rd); run_any_d <= (|run_reg_wr) || (|run_extra_wr) || (|run_reg_rd) || extif_run; // includes external interface
if (mrst || i2c_rst) first_mem_re <= 0; if (mrst || i2c_rst) first_mem_re <= 0;
else if (i2c_start) first_mem_re <= 1; else if (i2c_start) first_mem_re <= 1;
else if (mem_re[2]) first_mem_re <= 0; else if (mem_re[2]) first_mem_re <= 0;
if (mrst || i2c_rst) pre_cmd <= 0; if (mrst || i2c_rst) pre_cmd <= 0;
else if (i2c_start) pre_cmd <= 1; else if (i2c_start) pre_cmd <= 1; // extif also
else if (run_any_d) pre_cmd <= 0; else if (run_any_d) pre_cmd <= 0;
if (mrst || i2c_rst) i2c_run <= 0; if (mrst || i2c_rst) i2c_run <= 0;
else i2c_run <= i2c_start || pre_cmd || run_any_d; else i2c_run <= i2c_start || pre_cmd || run_any_d;
if (mrst || i2c_rst) i2c_busy <= 0; if (mrst || i2c_rst) i2c_busy <= 0;
else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open; else i2c_busy <= i2c_start || pre_cmd || run_any_d || bus_busy || bus_open; // includes external interface
table_re <= {table_re[1:0], pre_table_re}; // start_wr_seq_w}; table_re <= {table_re[1:0], pre_table_re}; // start_wr_seq_w};
if (table_re[2]) begin if (table_re[2]) begin
reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0]; // MSB of the register address (instead of the byte 2) reg_ah <= tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; // [ 7:0]; // MSB of the register address (instead of the byte 2)
num_bytes_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS] ; // [19:16]; // number of bytes to send (if more than 4 will skip stop and continue with next data num_bytes_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS] ; // [19:16]; // number of bytes to send (if more than 4 will skip stop and continue with next data
i2c_dly <= tdout[SENSI2C_TBL_DLY +: SENSI2C_TBL_DLY_BITS]; //[27:20]; i2c_dly <= tdout[SENSI2C_TBL_DLY +: SENSI2C_TBL_DLY_BITS]; // [27:20];
extif_sel_r <= tdout[SENSI2C_TBL_EXTIF +: SENSI2C_TBL_EXTIF_BITS]; // [30:31]
end end
if (table_re[2]) slave_a_rah <= {tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS], 1'b0}; // {tdout[15:9], 1'b0}; if (table_re[2]) slave_a_rah <= {tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS], 1'b0}; // {tdout[15:9], 1'b0};
else if (next_cmd && run_reg_wr[5]) slave_a_rah <= reg_ah; // will copy even if not used else if (next_cmd && run_reg_wr[5]) slave_a_rah <= reg_ah; // will copy even if not used
// wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy;
next_cmd <= pre_next_cmd; // if (table_re[2]) extif_sa_r <= tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS];
if (table_re[2]) extif_byte_r <= {1'b0, tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS]};
else if (next_cmd && extif_run) extif_byte_r <= run_reg_ext_wr[4]? reg_ah : seq_rd;
next_cmd <= pre_next_cmd || pre_next_extif;
next_cmd_d <= next_cmd; next_cmd_d <= next_cmd;
next_byte_wr <= snd9 && i2c_rdy && !run_reg_wr[5] && !rnw; // (|run_reg_rd); // same time as next_cmd, no pulse when sending SA during write // same time as next_cmd, no pulse when sending SA during write
// next_byte_wr <= next_byte_wr_w; // snd9 && i2c_rdy && !run_reg_wr[5] && !rnw; // (|run_reg_rd); // same time as next_cmd, no pulse when sending SA during write
// snd_start <= snd_start_w; // add & i2c_ready? Not really needed as any i2c stage will be busy for long enough next_byte_wr_or_ext <= next_byte_wr_w || extif_next_w;
// snd_stop <= snd_stop_w;
// snd9 <= snd9_w;
// counting bytes (and address) in extif mode also
if (mrst || i2c_rst) bytes_left_send <= 0; if (mrst || i2c_rst) bytes_left_send <= 0;
else if (start_wr_seq_w) bytes_left_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS]; // num_bytes_send; else if (start_wr_seq_w || start_extif_w) bytes_left_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS]; // num_bytes_send;
else if (next_byte_wr) bytes_left_send <= bytes_left_send - 1; /// else if (next_byte_wr) bytes_left_send <= bytes_left_send - 1;
else if (next_byte_wr_or_ext) bytes_left_send <= bytes_left_send - 1;
// extif_ackn <= !i2c_rst && extif_ready && extif_dav;
if (mrst || i2c_rst) extif_run <= 0;
else if (start_extif_w) extif_run <= 1;
else if (extif_ready && extif_dav && extif_last) extif_run <= 0;
if (mrst || i2c_rst) extif_dav_r <= 0;
else if (start_extif_w || (extif_run && mem_re[2]) || (run_reg_ext_wr[3] && next_cmd_d)) extif_dav_r <= 1;
else if (next_cmd) extif_dav_r <= 0;
// calculate stages for each type of commands // calculate stages for each type of commands
// start and write sa and some bytes, stop if number of bytes <= 4 at the end // start and write sa and some bytes, stop if number of bytes <= 4 at the end
if (mrst || i2c_rst) run_reg_ext_wr <= 0;
else if (start_extif_w) run_reg_ext_wr <= 5'h10;
else if (next_cmd) run_reg_ext_wr <= {1'b0, // SA (attr)
run_reg_ext_wr[4], // RA_msb (module) - always after SA (attr)
run_reg_ext_wr[3], // RA_lsb (func)
run_reg_ext_wr[2] & (num_bytes_send == 4'h2), // DH
run_reg_ext_wr[1] | (run_reg_ext_wr[2] & (num_bytes_send == 4'h1)) // DL
};
if (mrst || i2c_rst) run_reg_wr <= 0; if (mrst || i2c_rst) run_reg_wr <= 0;
else if (start_wr_seq_w) run_reg_wr <= 7'h40; else if (start_wr_seq_w) run_reg_wr <= 7'h40;
else if (next_cmd) run_reg_wr <= {1'b0, // first "start" else if (next_cmd) run_reg_wr <= {1'b0, // first "start"
...@@ -226,6 +273,8 @@ module sensor_i2c_prot#( ...@@ -226,6 +273,8 @@ module sensor_i2c_prot#(
run_reg_wr[2] | (run_reg_wr[5] & (num_bytes_send == 4'h1)), // byte 0 (from input) run_reg_wr[2] | (run_reg_wr[5] & (num_bytes_send == 4'h1)), // byte 0 (from input)
run_reg_wr[1] & (bytes_left_send == 4'h1) run_reg_wr[1] & (bytes_left_send == 4'h1)
}; };
// send just bytes (up to 4), stop if nothing left // send just bytes (up to 4), stop if nothing left
if (mrst || i2c_rst) run_extra_wr <= 0; if (mrst || i2c_rst) run_extra_wr <= 0;
else if (start_extra_seq_w) run_extra_wr <= { else if (start_extra_seq_w) run_extra_wr <= {
...@@ -243,18 +292,13 @@ module sensor_i2c_prot#( ...@@ -243,18 +292,13 @@ module sensor_i2c_prot#(
run_extra_wr[1] & (bytes_left_send == 4'h1) run_extra_wr[1] & (bytes_left_send == 4'h1)
}; };
// reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop
// if (table_re[2] && tdout[8]) read_address_bytes <= tdout[19];
if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_address_bytes <= tdout[SENSI2C_TBL_NABRD]; // [19]; if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_address_bytes <= tdout[SENSI2C_TBL_NABRD]; // [19];
// if (table_re[2] && tdout[8]) read_data_bytes <= tdout[18:16];
if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_data_bytes <= tdout[SENSI2C_TBL_NBRD +: SENSI2C_TBL_NBRD_BITS]; if (table_re[2] && tdout[SENSI2C_TBL_RNWREG]) read_data_bytes <= tdout[SENSI2C_TBL_NBRD +: SENSI2C_TBL_NBRD_BITS];
else if (run_reg_rd[1] && next_cmd) read_data_bytes <= read_data_bytes - 1; else if (run_reg_rd[1] && next_cmd) read_data_bytes <= read_data_bytes - 1;
// read i2c data // read i2c data
if (mrst || i2c_rst) run_reg_rd <= 0; if (mrst || i2c_rst) run_reg_rd <= 0;
// else if (!run_extra_wr_d && decode_reg_rd && read_mem_msb) run_reg_rd <= 8'h80;
else if (start_rd_seq_w) run_reg_rd <= 8'h80; else if (start_rd_seq_w) run_reg_rd <= 8'h80;
else if (next_cmd) run_reg_rd <= {1'b0, // first "start" else if (next_cmd) run_reg_rd <= {1'b0, // first "start"
run_reg_rd[7], // slave_addr - always after start (bit0 = 0) run_reg_rd[7], // slave_addr - always after start (bit0 = 0)
...@@ -267,13 +311,14 @@ module sensor_i2c_prot#( ...@@ -267,13 +311,14 @@ module sensor_i2c_prot#(
}; };
// read sequencer memory byte (for the current word) // read sequencer memory byte (for the current word)
mem_re <= {mem_re[1:0], i2c_start | next_cmd_d & ( mem_re <= {mem_re[1:0], i2c_start | next_cmd_d & (
(~extif_last & (|run_reg_ext_wr[3:0])) |
(|run_reg_wr[3:1]) | (|run_reg_wr[3:1]) |
(|run_extra_wr[4:1]) | (|run_extra_wr[4:1]) |
(|run_reg_rd[6:4]))}; (|run_reg_rd[6:4]))};
initial_address <= initial_address_w[1:0]; // if bytes left to send is 0 mod 4 - will be 3 (read MSB) initial_address <= initial_address_w[1:0]; // if bytes left to send is 0 mod 4 - will be 3 (read MSB)
seq_mem_ra <= i2c_start ? initial_address : { // run_extra_wr[4] is not needed - it will be read by i2c_start seq_mem_ra <= i2c_start ? initial_address : { // run_extra_wr[4] is not needed - it will be read by i2c_start
run_reg_wr[3] | run_extra_wr[3] | run_reg_rd[6], run_reg_wr[3] | run_extra_wr[3] | run_reg_rd[6] | run_reg_ext_wr[3], //?
run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5] run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5] | run_reg_ext_wr[1] //?
}; };
if (mrst || i2c_rst || i2c_start || next_cmd ) mem_valid <= 0; if (mrst || i2c_rst || i2c_start || next_cmd ) mem_valid <= 0;
else if (mem_re[2]) mem_valid <= 1; else if (mem_re[2]) mem_valid <= 1;
...@@ -302,6 +347,8 @@ module sensor_i2c_prot#( ...@@ -302,6 +347,8 @@ module sensor_i2c_prot#(
2'h3: sr_in <= {8'hff,(read_data_bytes == 3'h1)}; 2'h3: sr_in <= {8'hff,(read_data_bytes == 3'h1)};
endcase endcase
end end
sensor_i2c_scl_sda sensor_i2c_scl_sda_i ( sensor_i2c_scl_sda sensor_i2c_scl_sda_i (
...@@ -349,7 +396,8 @@ module sensor_i2c_prot#( ...@@ -349,7 +396,8 @@ module sensor_i2c_prot#(
.waddr ({1'b0, twa}), // input[8:0] .waddr ({1'b0, twa}), // input[8:0]
.we (twe && !tand), // input .we (twe && !tand), // input
.web (4'hf), // input[3:0] .web (4'hf), // input[3:0]
.data_in ({4'b0, td}) // input[31:0] // .data_in ({4'b0, td}) // input[31:0]
.data_in (td) // input[31:0]
); );
......
sensor/sensors393.v
View file @ 043d4849
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* @brief 4-channel sensor subsystem * @brief 4-channel sensor subsystem
* Uniform, assuming the same sensors/multiplexers, common pixel clock * Uniform, assuming the same sensors/multiplexers, common pixel clock
* *
* @copyright Copyright (c) 2015 Elphel, Inc . * @copyright Copyright (c) 2015-2020 Elphel, Inc .
* *
* <b>License:</b> * <b>License:</b>
* *
...@@ -41,8 +41,9 @@ ...@@ -41,8 +41,9 @@
module sensors393 #( module sensors393 #(
// parameters, individual to sensor channels and those likely to be modified // parameters, individual to sensor channels and those likely to be modified
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address // moving to the end to be always present
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel // parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
// parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
...@@ -162,18 +163,34 @@ module sensors393 #( ...@@ -162,18 +163,34 @@ module sensors393 #(
// sens_parallel12 registers // sens_parallel12 registers
parameter SENSIO_CTRL = 'h0, parameter SENSIO_CTRL = 'h0,
parameter SENS_CTRL_MRST = 0, // 1: 0 parameter SENS_CTRL_MRST = 0, // 1: 0
`ifndef BOSON
parameter SENS_CTRL_ARST = 2, // 3: 2 parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4 parameter SENS_CTRL_ARO = 4, // 5: 4
`endif
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6 parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
`ifdef HISPI `ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8 parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
`elsif BOSON
// ???
`else `else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8 parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
`endif `endif
parameter SENS_CTRL_LD_DLY = 10, // 10 parameter SENS_CTRL_LD_DLY = 10, // 10
`ifdef HISPI `ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 14:12 parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15 parameter SENS_CTRL_GP1= 15, // 17:15
`elsif BOSON
parameter SENS_CTRL_GP0= 12, // 14:12
parameter SENS_CTRL_GP1= 15, // 17:15
parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
parameter SENS_UART_EXTIF_EN = 0, // 1: 0
parameter SENS_UART_XMIT_RST = 2, // 3: 2
parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7
`else `else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6, parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
...@@ -181,15 +198,20 @@ module sensors393 #( ...@@ -181,15 +198,20 @@ module sensors393 #(
parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved) parameter SENS_CTRL_QUADRANTS_EN = 20, // 18:12, enable - 20 (1 bits reserved)
`endif `endif
parameter SENSIO_STATUS = 'h1, parameter SENSIO_STATUS = 'h1,
`ifndef BOSON
parameter SENSIO_JTAG = 'h2, parameter SENSIO_JTAG = 'h2,
parameter SENS_JTAG_PGMEN = 8, parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6, parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4, parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2, parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0, parameter SENS_JTAG_TDI = 0,
`ifndef HISPI `endif
`ifdef HISPI
`elsif BOSON
`else
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
`endif `endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7 parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
`endif // `ifdef LWIR `endif // `ifdef LWIR
...@@ -204,6 +226,18 @@ module sensors393 #( ...@@ -204,6 +226,18 @@ module sensors393 #(
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif `endif
`elsif BOSON
/*
`ifdef MON_HISPI
parameter SENSOR_TIMING_STATUS_REG_BASE = 'h40, // 4 locations" x40, x41, x42, x43
parameter SENSOR_TIMING_STATUS_REG_INC = 1, // increment to the next sensor
parameter SENSOR_TIMING_BITS = 24, // increment to the next sensor
parameter SENSOR_TIMING_START = 16, // bit # in JTAB control word to start timing measurement (now f = 660/4 = 165)
parameter SENSOR_TIMING_LANE = 14, // 15:14 - select lane
parameter SENSOR_TIMING_FROM = 12, // select from 0 - sof, 1 - sol, 2 - eof, 3 eol
parameter SENSOR_TIMING_TO = 10, // select to 0 - sof, 1 - sol, 2 - eof, 3 eol
`endif
*/
`endif `endif
// 4 of 8-bit delays per register // 4 of 8-bit delays per register
...@@ -229,6 +263,7 @@ module sensors393 #( ...@@ -229,6 +263,7 @@ module sensors393 #(
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifdef HISPI `ifdef HISPI
`elsif BOSON
`elsif LWIR `elsif LWIR
parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16) parameter integer VOSPI_DRIVE = 16, // 12, (4,8,12,16)
parameter VOSPI_IBUF_LOW_PWR = "TRUE", parameter VOSPI_IBUF_LOW_PWR = "TRUE",
...@@ -297,63 +332,67 @@ module sensors393 #( ...@@ -297,63 +332,67 @@ module sensors393 #(
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof) parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 4, // 15, // number of lines to delay late frame sync parameter SENS_SYNC_LATE_DFLT = 4, // 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130 // minimal frame period (in pclk/mclk?) parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters // sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels? // parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
// start with comma
`ifdef LWIR `ifdef LWIR
`else `else
,parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 200, // was 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE" parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
`endif `endif
// start with comma
`ifdef HISPI `ifdef HISPI
,parameter PXD_CAPACITANCE = "DONT_CARE", parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4 parameter PXD_CLK_DIV_BITS = 4,
`elsif BOSON
parameter PXD_CAPACITANCE = "DONT_CARE",
`endif `endif
// start with comma
`ifdef LWIR `ifdef LWIR
`else `else
.parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors) parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_BANDWIDTH = "OPTIMIZED" //"OPTIMIZED", "HIGH","LOW" parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
`endif `endif
// start with comma
`ifdef LWIR `ifdef LWIR
,parameter SENSI2C_IOSTANDARD = "LVCMOS18" parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif HISPI `elsif HISPI
,parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18", parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18" parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `elsif BOSON
,parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`elsif PAR12
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25", parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25" parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
// start with comma
`ifdef LWIR `ifdef LWIR
`else `else
,parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR", parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3 parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR", parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
...@@ -366,12 +405,12 @@ module sensors393 #( ...@@ -366,12 +405,12 @@ module sensors393 #(
parameter SENS_REF_JITTER2 = 0.010, parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
`endif `endif
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "FALSE", parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE", parameter HISPI_DELAY_CLK1= "FALSE",
...@@ -392,24 +431,61 @@ module sensors393 #( ...@@ -392,24 +431,61 @@ module sensors393 #(
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA) parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`elsif BOSON
// parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 3,
parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE",
parameter HISPI_DELAY_CLK2= "FALSE",
parameter HISPI_DELAY_CLK3= "FALSE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
// parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
// parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
// parameter HISPI_FIFO_DEPTH = 4,
// parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,parameter DEBUG_CMD_LATENCY = 2 parameter DEBUG_CMD_LATENCY = 2,
`endif `endif
// parameter real REFCLK_FREQUENCY = 200.0,
// parameter HIGH_PERFORMANCE_MODE = "FALSE"
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040 // increment for sesor channel
) ( ) (
// input rst, // input rst,
// will generate it here // will generate it here
`ifdef PCLK_MASTER
output [3:0] pclk,
output [3:0] locked_pclk,
`else
input pclk, // global clock input, pixel rate (96MHz for MT9P006) input pclk, // global clock input, pixel rate (96MHz for MT9P006)
`endif
`ifdef USE_PCLK2X `ifdef USE_PCLK2X
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006) input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
`endif `endif
input ref_clk, // IODELAY calibration input ref_clk, // IODELAY calibration
input dly_rst, input dly_rst,
input mrst, // @posedge mclk, sync reset input mrst, // @posedge mclk, sync reset
`ifdef PCLK_MASTER
input [3:0] prst,
`else
input prst, // @posedge pclk, sync reset input prst, // @posedge pclk, sync reset
`endif
input arst, // @posedge aclk, sync reset input arst, // @posedge aclk, sync reset
// programming interface // programming interface
...@@ -419,7 +495,6 @@ module sensors393 #( ...@@ -419,7 +495,6 @@ module sensors393 #(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
// I/O pads, pin names match circuit diagram (each sensor) // I/O pads, pin names match circuit diagram (each sensor)
`ifdef HISPI `ifdef HISPI
input [15:0] sns_dp, input [15:0] sns_dp,
...@@ -428,6 +503,13 @@ module sensors393 #( ...@@ -428,6 +503,13 @@ module sensors393 #(
inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif BOSON
input [15:0] sns_dp,
input [15:0] sns_dn,
inout [15:0] sns_dp74, // SuppressThisWarning all - unused yet
inout [15:0] sns_dn74, // SuppressThisWarning all - unused yet
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`elsif LWIR `elsif LWIR
inout [19:0] sns_dp40, inout [19:0] sns_dp40,
inout [19:0] sns_dn40, inout [19:0] sns_dn40,
...@@ -448,6 +530,8 @@ module sensors393 #( ...@@ -448,6 +530,8 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
`elsif BOSON
inout [3:0] sns_ctl, // SuppressThisWarning all - output-only in HiSPi mode
`else `else
inout [3:0] sns_ctl, inout [3:0] sns_ctl,
`endif `endif
...@@ -507,8 +591,10 @@ module sensors393 #( ...@@ -507,8 +591,10 @@ module sensors393 #(
`ifdef DEBUG_SENS_MEM_PAGES `ifdef DEBUG_SENS_MEM_PAGES
,output [2 * 4 - 1 : 0] dbg_rpage ,output [2 * 4 - 1 : 0] dbg_rpage
,output [2 * 4 - 1 : 0] dbg_wpage ,output [2 * 4 - 1 : 0] dbg_wpage
`endif `endif
`ifdef LWIR
,input khz // 1 KHz 50% @mclk ,input khz // 1 KHz 50% @mclk
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,output debug_do, // output to the debug ring ,output debug_do, // output to the debug ring
...@@ -545,7 +631,8 @@ module sensors393 #( ...@@ -545,7 +631,8 @@ module sensors393 #(
wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0}; wire [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs wire [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
`ifdef LWIR
wire ext_rst_in; wire ext_rst_in;
wire ext_rstseq_in; wire ext_rstseq_in;
wire [3:0] ext_rst_out; wire [3:0] ext_rst_out;
...@@ -553,6 +640,7 @@ module sensors393 #( ...@@ -553,6 +640,7 @@ module sensors393 #(
assign ext_rst_in = |ext_rst_out; assign ext_rst_in = |ext_rst_out;
assign ext_rstseq_in = |ext_rstseq_out; assign ext_rstseq_in = |ext_rstseq_out;
`endif
always @ (posedge mclk) begin always @ (posedge mclk) begin
cmd_ad <= cmd_ad_in; cmd_ad <= cmd_ad_in;
...@@ -563,7 +651,8 @@ module sensors393 #( ...@@ -563,7 +651,8 @@ module sensors393 #(
genvar i; genvar i;
for (i=0; i < 4; i=i+1) begin: sensor_channel_block for (i=0; i < 4; i=i+1) begin: sensor_channel_block
sensor_channel #( sensor_channel #(
.SENSOR_NUMBER (i), // moving to the end to be always present
// .SENSOR_NUMBER (i),
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR), .SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC), .SENSOR_BASE_INC (SENSOR_BASE_INC),
.SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE), .SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE),
...@@ -662,11 +751,16 @@ module sensors393 #( ...@@ -662,11 +751,16 @@ module sensors393 #(
`else `else
.SENSIO_CTRL (SENSIO_CTRL), .SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST), .SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifndef BOSON
.SENS_CTRL_ARST (SENS_CTRL_ARST), .SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO), .SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM), `endif
`ifdef HISPI `ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED), .SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`elsif BOSON
// Anything for BOSON?
`else `else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK), .SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif `endif
...@@ -674,6 +768,16 @@ module sensors393 #( ...@@ -674,6 +768,16 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0), .SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1), .SENS_CTRL_GP1 (SENS_CTRL_GP1),
`elsif BOSON
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
`else `else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS), .SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
...@@ -681,13 +785,17 @@ module sensors393 #( ...@@ -681,13 +785,17 @@ module sensors393 #(
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN), .SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif `endif
.SENSIO_STATUS (SENSIO_STATUS), .SENSIO_STATUS (SENSIO_STATUS),
`ifndef BOSON
.SENSIO_JTAG (SENSIO_JTAG), .SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN), .SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG), .SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK), .SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS), .SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI), .SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI `endif
`ifdef HISPI
`elsif BOSON
`else
.SENSIO_WIDTH (SENSIO_WIDTH), .SENSIO_WIDTH (SENSIO_WIDTH),
`endif `endif
.SENSIO_DELAYS (SENSIO_DELAYS), .SENSIO_DELAYS (SENSIO_DELAYS),
...@@ -703,7 +811,19 @@ module sensors393 #( ...@@ -703,7 +811,19 @@ module sensors393 #(
.SENSOR_TIMING_FROM (SENSOR_TIMING_FROM), .SENSOR_TIMING_FROM (SENSOR_TIMING_FROM),
.SENSOR_TIMING_TO (SENSOR_TIMING_TO), .SENSOR_TIMING_TO (SENSOR_TIMING_TO),
`endif `endif
`endif `elsif BOSON
/*
`ifdef MON_HISPI
.SENSOR_TIMING_STATUS_REG_BASE (SENSOR_TIMING_STATUS_REG_BASE),
.SENSOR_TIMING_STATUS_REG_INC (SENSOR_TIMING_STATUS_REG_INC),
.SENSOR_TIMING_BITS (SENSOR_TIMING_BITS),
.SENSOR_TIMING_START (SENSOR_TIMING_START),
.SENSOR_TIMING_LANE (SENSOR_TIMING_LANE),
.SENSOR_TIMING_FROM (SENSOR_TIMING_FROM),
.SENSOR_TIMING_TO (SENSOR_TIMING_TO),
`endif
*/
`endif
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR), .SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR), .SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK), .SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
...@@ -721,6 +841,11 @@ module sensors393 #( ...@@ -721,6 +841,11 @@ module sensors393 #(
.SENSI2C_SLEW (SENSI2C_SLEW), .SENSI2C_SLEW (SENSI2C_SLEW),
.NUM_FRAME_BITS (NUM_FRAME_BITS), .NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifdef HISPI `ifdef HISPI
.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`elsif BOSON
.PXD_CAPACITANCE (PXD_CAPACITANCE),
`elsif LWIR `elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE), .VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR), .VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
...@@ -766,37 +891,23 @@ module sensors393 #( ...@@ -766,37 +891,23 @@ module sensors393 #(
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4 .VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap) .VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000 .VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS) // 185 .VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
`else `else // parallel only
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH), .SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH), .SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY) .SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
`endif `endif
// start with comma // aLL SENSORS
`ifdef LWIR
`else
,.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE) .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`endif
// start with comma .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
`ifdef LWIR
`elsif HISPI
,.PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
// start with comma
`ifdef LWIR
`else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH), .SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), .CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), .CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
...@@ -810,11 +921,9 @@ module sensors393 #( ...@@ -810,11 +921,9 @@ module sensors393 #(
.SENS_REF_JITTER2 (SENS_REF_JITTER2), .SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD) .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
`endif
`ifdef HISPI `ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )), .HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
...@@ -830,19 +939,51 @@ module sensors393 #( ...@@ -830,19 +939,51 @@ module sensors393 #(
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE), .HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR), .HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE), .HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD) .HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`elsif BOSON
// .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
// .HISPI_KEEP_IRST (HISPI_KEEP_IRST),
// .HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
// .HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
// .HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_UNTUNED_SPLIT (HISPI_UNTUNED_SPLIT),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY) .DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
`endif `endif
// .REFCLK_FREQUENCY (REFCLK_FREQUENCY), // 200.0,
// .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), // = "FALSE"
.SENSOR_NUMBER (i)
) sensor_channel_i ( ) sensor_channel_i (
`ifdef PCLK_MASTER
.pclk (pclk[i]), // input
.locked_pclk (locked_pclk[i]), // input
`else
.pclk (pclk), // input .pclk (pclk), // input
`endif
`ifdef USE_PCLK2X `ifdef USE_PCLK2X
.pclk2x (pclk2x), // input .pclk2x (pclk2x), // input
`endif `endif
.mrst (mrst), // input .mrst (mrst), // input
`ifdef PCLK_MASTER
.prst (prst[i]), // input
`else
.prst (prst), // input .prst (prst), // input
`endif
`ifdef HISPI `ifdef HISPI
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0] .sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0] .sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
...@@ -850,6 +991,13 @@ module sensors393 #( ...@@ -850,6 +991,13 @@ module sensors393 #(
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0] .sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input .sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input .sns_clkn (sns_clkn[i]), // input
`elsif BOSON
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
.sns_dp74 (sns_dp74[i * 4 +: 4]), // input[3:0]
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input
`elsif LWIR `elsif LWIR
.sns_dp40 (sns_dp40[i * 5 +: 5]), // input[4:0] .sns_dp40 (sns_dp40[i * 5 +: 5]), // input[4:0]
.sns_dn40 (sns_dn40[i * 5 +: 5]), // input[4:0] .sns_dn40 (sns_dn40[i * 5 +: 5]), // input[4:0]
...@@ -898,8 +1046,8 @@ module sensors393 #( ...@@ -898,8 +1046,8 @@ module sensors393 #(
.ext_rstseq_in (ext_rstseq_in), // input .ext_rstseq_in (ext_rstseq_in), // input
.ext_rst_out (ext_rst_out[i]), // output .ext_rst_out (ext_rst_out[i]), // output
.ext_rstseq_out (ext_rstseq_out[i]) // output .ext_rstseq_out (ext_rstseq_out[i]) // output
`endif
,.khz (khz) // input 1 KHz 50% duty ,.khz (khz) // input 1 KHz 50% duty
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output ,.debug_do (debug_ring[i]), // output
...@@ -911,8 +1059,13 @@ module sensors393 #( ...@@ -911,8 +1059,13 @@ module sensors393 #(
sensor_membuf #( sensor_membuf #(
.WADDR_WIDTH(9) .WADDR_WIDTH(9)
) sensor_membuf_i ( ) sensor_membuf_i (
`ifdef PCLK_MASTER
.pclk (pclk[i]), // input
.prst (prst[i]), // input
`else
.pclk (pclk), // input .pclk (pclk), // input
.prst (prst), // input .prst (prst), // input
`endif
.mrst (mrst), // input .mrst (mrst), // input
.frame_run_mclk(frame_run_mclk[i]), // input @mclk - memory channel is ready to accept data from the sensor .frame_run_mclk(frame_run_mclk[i]), // input @mclk - memory channel is ready to accept data from the sensor
.px_data (px_data[16 * i +: 16]), // input[15:0] .px_data (px_data[16 * i +: 16]), // input[15:0]
......
sensor/serial_103993.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_103993
* @file serial_103993.v
* @date 2020-12-18
* @author eyesis
*
* @brief Serial interface to communicate with Boson (software r/w any, sequencer - short writes)
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_103993.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_103993.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_103993#(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60,
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst, // reset seq xmit and sequence number
// software interface (byte R/W)
input extif_en, // enable transmission from the sequencer
input xmit_rst, // reset (soft xmit only)
input xmit_start, // all in programmatic FIFO
input [7:0] xmit_data, // write data byte
input xmit_stb, // write data strobe
output xmit_busy,
input recv_rst, // reset read uart FIFO
input recv_next,
output recv_prgrs, // read in progress
output recv_dav, // read byte available
output [7:0] recv_data
);
wire [ 7:0] xmit_fifo_out;
wire [ 1:0] xmit_fifo_re_regen;
wire [10:0] xmit_fifo_waddr;
wire [10:0] xmit_fifo_raddr;
// wire [11:0] xmit_fifo_fill;
// reg xmit_fifo_rd;
wire xmit_fifo_nempty;
wire recv_fifo_wr;
wire [ 1:0] recv_fifo_re_regen;
wire [10:0] recv_fifo_waddr;
wire [10:0] recv_fifo_raddr;
// wire [11:0] recv_fifo_fill;
wire [ 7:0] recv_fifo_din;
reg xmit_pend; // initiated soft xmit
reg xmit_run; // runing soft xmit
reg xmit_run_d; // runing soft xmit, delayed
reg extif_run; // running xmit from the sequencer
reg extif_run_d; // running xmit from the sequencer
wire [ 7:0] xmit_extif_data; // data byte to transmit from the sequencer
reg xmit_stb_fifo;
reg xmit_stb_seq;
reg xmit_over_fifo;
reg xmit_over_seq;
reg xmit_stb_d;
reg xmit_over_d;
reg stuffer_busy_d;
reg xmit_busy_r;
wire xmit_start_out_fifo;
wire xmit_start_out_seq;
wire xmit_start_out;
reg xmit_done; // any mode - soft or seq;
wire extif_rq_w;
wire [ 7:0] xmit_any_data;
wire xmit_stb_any;
wire xmit_over;
wire tx_rdy; // transmit IF ready to accept byte
wire pre_tx_stb;
wire stuffer_busy; // output processing packet (not including UART)
wire uart_tx_busy; // output UART busy ('or' with stuffer_busy?)
// // soft seq number may always use >0xffff to distinguish
wire packet_ready_seq;
wire packet_over_seq;
// wire packet_sent;
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
assign xmit_stb_any = extif_run ? xmit_stb_seq : xmit_stb_fifo;
assign xmit_over = extif_run ? xmit_over_seq : xmit_over_fifo;
assign xmit_start_out_fifo = xmit_run && !xmit_run_d;
assign xmit_start_out_seq = extif_run && !extif_run_d;
assign xmit_start_out = xmit_start_out_fifo || xmit_start_out_seq;
assign pre_tx_stb = !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
assign xmit_busy = xmit_busy_r;
// assign packet_sent = xmit_over && !xmit_over_d;
always @(posedge mclk) begin
xmit_busy_r <= uart_tx_busy || stuffer_busy_d || xmit_pend || xmit_run || extif_run;
if (mrst || xmit_rst) xmit_pend <= 0;
else if (xmit_start) xmit_pend <= 1;
else if (xmit_start_out_fifo) xmit_pend <= 0;
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && extif_run) xmit_run <= 1;
else if (xmit_done) xmit_run <= 0; // no need to condition with xmit_run
// else if (!stuffer_busy && !xmit_fifo_nempty) xmit_run <= 0; // no need to condition with xmit_run
xmit_run_d <= xmit_run && !mrst && !xmit_rst;
if (mrst || extif_rst) extif_run <= 0;
else if (!xmit_run && !xmit_pend && extif_rq_w) extif_run <= 1;
else if (xmit_done) extif_run <= 0; // no need to condition with xmit_run
extif_run_d <= extif_run && !mrst && !extif_rst;
xmit_stb_d <= xmit_stb_any;
xmit_over_d <= xmit_over;
stuffer_busy_d <= stuffer_busy;
xmit_done <= stuffer_busy_d && !stuffer_busy;
// transmit soft (from fifo) (FIFO should always be not empty until last byte (should nit be replenished)
xmit_stb_fifo <= pre_tx_stb && xmit_fifo_nempty; // also advances FIFO read
xmit_over_fifo <= pre_tx_stb && !xmit_fifo_nempty;
// Generate sequencer packet and transmit it
xmit_stb_seq <= pre_tx_stb && packet_ready_seq;
xmit_over_seq <= pre_tx_stb && packet_over_seq;
end
/* Instance template for module serial_103993_extif */
serial_103993_extif #(
.EXTIF_MODE (EXTIF_MODE) // 1)
) serial_103993_extif_i (
.mclk (mclk), // input
.mrst (mrst), // input
.extif_en (extif_en), // input
.extif_dav (extif_dav), // input
.extif_sel (extif_sel), // input[1:0]
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst), // input
.packet_ready (packet_ready_seq), // output
.packet_byte (xmit_extif_data), // output[7:0]
.packet_byte_stb (xmit_stb_seq), // input
.packet_over (packet_over_seq), // output
.packet_sent (xmit_done) // input
);
serial_fslp #(
.START_FRAME_BYTE (START_FRAME_BYTE), // 'h8E),
.END_FRAME_BYTE (END_FRAME_BYTE), // 'hAE),
.ESCAPE_BYTE (ESCAPE_BYTE), // 'h9E),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE), // 'h81),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE), // 'hA1),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE), // 'h91),
.INITIAL_CRC16 (INITIAL_CRC16), // 16'h1d0f),
.CLK_DIV (CLK_DIV), // 217),
.RX_DEBOUNCE (RX_DEBOUNCE) // 60)
) serial_fslp_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output serial data out
.rxd (rxd), // input serial data in
.tx_start (xmit_start_out), // input start transmit packet
.tx_done (xmit_over), // input end transmit packet
.tx_stb (xmit_stb_any), // input transmit byte strobe
.tx_byte (xmit_any_data), // input[7:0] transmit byte input
.tx_rdy (tx_rdy), // output crc16 ready to accept tx_in_stb
.stuffer_busy (stuffer_busy), // output processing packet (not including UART)
.uart_tx_busy (uart_tx_busy), // output UART busy ('or' with stuffer_busy?)
.rx_byte (recv_fifo_din), // output[7:0] received byte output
.rx_stb (recv_fifo_wr), // output received byte strobe
.rx_packet_run (recv_prgrs), // output run received packet
.rx_packet_done () // output finished receiving packet (last 2 bytes - crc16)
);
fifo_sameclock_control #(
.WIDTH(11)
) fifo_xmit_control_i (
.clk (mclk), // input
.rst (mrst || xmit_rst), // input
.wr (xmit_stb), // input
.rd (xmit_stb_fifo), // input
.nempty (xmit_fifo_nempty), // output
.fill_in (), // output[11:0]
.mem_wa (xmit_fifo_waddr), // output[10:0] reg
.mem_ra (xmit_fifo_raddr), // output[10:0] reg
.mem_re (xmit_fifo_re_regen[0]), // output
.mem_regen(xmit_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (3),
.LOG2WIDTH_RD (3)
) fifo_xmit_i (
.rclk (mclk), // input
.raddr (xmit_fifo_raddr), // input[10:0]
.ren (xmit_fifo_re_regen[0]), // input
.regen (xmit_fifo_re_regen[1]), // input
.data_out (xmit_fifo_out), // output[7:0]
.wclk (mclk), // input
.waddr (xmit_fifo_waddr), // input[10:0]
.we (xmit_stb), // input
.web (4'hf), // input[3:0]
.data_in (xmit_data) // input[7:0]
);
fifo_sameclock_control #(
.WIDTH(11)
) fifo_recv_control_i (
.clk (mclk), // input
.rst (mrst || recv_rst), // input
.wr (recv_fifo_wr), // input
.rd (recv_next), // input
.nempty (recv_dav), // output
.fill_in (), // recv_fifo_fill), // output[11:0]
.mem_wa (recv_fifo_waddr), // output[10:0] reg
.mem_ra (recv_fifo_raddr), // output[10:0] reg
.mem_re (recv_fifo_re_regen[0]), // output
.mem_regen(recv_fifo_re_regen[1]), // output
.over (), // output reg
.under () //h2d_under) // output reg
);
ram18_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (3),
.LOG2WIDTH_RD (3)
) fifo_recv_i (
.rclk (mclk), // input
.raddr (recv_fifo_raddr), // input[10:0]
.ren (recv_fifo_re_regen[0]), // input
.regen (recv_fifo_re_regen[1]), // input
.data_out (recv_data), // output[7:0]
.wclk (mclk), // input
.waddr (recv_fifo_waddr), // input[10:0]
.we (recv_fifo_wr), // input
.web (4'hf), // input[3:0]
.data_in (recv_fifo_din) // input[7:0]
);
endmodule
sensor/serial_103993_extif.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_103993_extif
* @file serial_103993_extif.v
* @date 2020-12-19
* @author eyesis
*
* @brief convert sequencer data to 103993 serial packet data
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_103993_extif.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_103993_extif.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_103993_extif #(
parameter EXTIF_MODE = 1 // 1,2 or 3 if there are several different extif
)(
input mclk,
input mrst,
// sequencer interface
// sequencer always provides 4 payload bytes (5 total)
// interface for uart in write-only mode for short commands
// 1-st byte - SA (use 2 LSB to select 0,1,2 data bytes
// 2-nd byte module
// 3-rd byte function
// 4 (optional) data[15:8] or data[7:0] if last
// 5 (optional) data[7:0]
input extif_en, // enable receiving new packet data
input extif_dav, // data byte available for external interface
// input extif_last, // last byte for external interface (with extif_dav)
input [1:0] extif_sel, // interface type (0 - internal, 1 - uart, 2,3 - reserved)
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst, // reset seq xmit and sequence number
output packet_ready,// packet ready, later next packet byte ready
output [7:0] packet_byte,
input packet_byte_stb, // packet byte read out - should be >2(?) cycles apart
// output packet_byte_rdy, // packet byte ready
output packet_over,
input packet_sent
);
reg [3:0] packet_mode; // 1 - zero bytes, 2 - 1 byte, 4 - 2 bytes, 8 - 4 bytes
reg packet_nempty_r; // ~ready to receive packet
// reg packet_ready_r;
reg [2:0] in_bytes;
// reg packet_in; // receiving packet bytes (after mode)
reg extif_ready_r;
reg [7:0] payload_ram [0:3]; // module (1 byte), function (1 byte) , data[15:8], data[7:0]
wire recv_start; // receive first byte - mode
wire recv_next; // receive next byte
wire reset_in_bytes;
reg [17:0] packet_gen_state;
reg inc_ra;
reg [1:0] ra;
reg [7:0] payload_r; // registered payload byte
reg use_mem; // output payload from memory
reg use_ff; // 0xff byte
reg [15:0] seq_num; // 16-bit sequence number
reg [7:0] packet_byte_r;
reg [1:0] packet_byte_stb_d;
assign packet_ready = in_bytes[2] && !packet_byte_stb_d[0] && !packet_byte_stb_d[1]; //
assign recv_start = !packet_nempty_r && extif_en && extif_dav && (extif_sel == EXTIF_MODE) && extif_ready_r;
assign recv_next = packet_nempty_r && extif_dav && !extif_ready_r;
assign reset_in_bytes = mrst || extif_rst || !packet_nempty_r;
assign packet_byte = packet_byte_r;
assign extif_ready = extif_ready_r;
assign packet_over = packet_gen_state[17];
always @(posedge mclk) begin
if (mrst || extif_rst) packet_byte_stb_d <= 0;
else packet_byte_stb_d <= {packet_byte_stb_d[0], packet_byte_stb};
if (mrst || extif_rst || !extif_dav) extif_ready_r <= 0;
else if (recv_start || recv_next) extif_ready_r <= 1;
if (mrst || extif_rst) packet_nempty_r <= 0;
else if (recv_start) packet_nempty_r <= 1;
else if (packet_sent) packet_nempty_r <= 0;
if (recv_start) packet_mode <= {
extif_byte[1] & extif_byte[0], // 3 - 4 bytes
extif_byte[1] & ~extif_byte[0], // 2 - 2 bytes
~extif_byte[1] & extif_byte[0], // 1 - 1 byte
~extif_byte[1] & ~extif_byte[0]};// 0 - 0 bytes
// if (reset_in_bytes) packet_in <= 0;
if (reset_in_bytes) in_bytes <= 0;
else if (recv_next) in_bytes <= in_bytes + 1;
if (recv_next) payload_ram[in_bytes] <= extif_byte;
payload_r <= payload_ram[ra];
// Generating packet
if (!in_bytes[2]) packet_gen_state <= 1;
else if (packet_byte_stb) packet_gen_state <= {
(packet_gen_state[12] & packet_mode[0]) | packet_gen_state[16], // 17
(packet_gen_state[12] & packet_mode[1]) | packet_gen_state[15], // 16
(packet_gen_state[12] & packet_mode[2]) | packet_gen_state[14], // 15
packet_gen_state[13], // 14
packet_gen_state[12] & packet_mode[3], // 13
packet_gen_state[11:0], // 1..12
1'b0}; // 0
inc_ra <= packet_byte_stb & (
packet_gen_state[6] | packet_gen_state[8] | packet_gen_state[15] | ( | packet_gen_state[9] & packet_mode[1]));
if (!in_bytes[2]) ra <= 0;
else if (inc_ra) ra <= ra + 1;
if (mrst || extif_rst) seq_num <= 0;
else if (packet_sent) seq_num <= seq_num + 1;
use_mem <= packet_gen_state[6] | packet_gen_state[8] | packet_gen_state[15] | packet_gen_state[16];
use_ff <= packet_gen_state[9] | packet_gen_state[10] | packet_gen_state[11] | packet_gen_state[12];
packet_byte_r <= (
{8{use_mem}} & payload_r) |
{8{use_ff}} |
({8{packet_gen_state[3]}} & seq_num[15:8]) |
({8{packet_gen_state[4]}} & seq_num[ 7:0]);
end
/*
reg [7:0] payload_r; // registered payload byte
reg use_mem; // output payload from memory
reg use_ff; // 0xff byte
reg [15:0] seq_num; // 16-bit sequence number
reg use_mem;
reg use_ff;
fifo_same_clock #(
.DATA_WIDTH(8),
.DATA_DEPTH(4)
) fifo_same_clock_i2c_rdata_i (
.rst (1'b0), // input
.clk (mclk), // input
.sync_rst (mrst | extif_rst), // input
.we (i2c_rvalid), // input
.re (i2c_fifo_rd), // input
.data_in (i2c_rdata), // input[15:0]
.data_out (i2c_fifo_dout), // output[15:0]
.nempty (i2c_fifo_nempty), // output
.half_full () // output reg
);
*/
endmodule
sensor/serial_destuffer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_destuffer
* @file serial_destuffer.v
* @date 2020-12-13
* @author eyesis
*
* @brief unwrap serial packet from fslp
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_destuffer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_destuffer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_destuffer#(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input [7:0] rxd_in, // data byte from uart
input rx_in_stb, // data strob from uart
output [7:0] rxd_out, // destuffed payload (including channel and CRC, excluding START/END
output rx_stb, // output data strobe
output packet_run, // receiving packet (debug output)
output packet_done // single-cycle packet end indicator
);
reg [1:0] packet_run_r;
reg packet_done_r;
reg payload;
reg [7:0] rxd_in_r;
reg [2:0] in_stb;
reg is_esc;
reg [7:0] rxd_r;
reg [2:0] replaced;
reg thru; // pass input data through
reg [1:0] out_stb;
wire flsp_start;
wire flsp_end;
wire is_esc_w;
wire [2:0] replaced_w;
assign flsp_start = in_stb[0] && (rxd_in_r == START_FRAME_BYTE);
assign flsp_end = in_stb[0] && (rxd_in_r == END_FRAME_BYTE);
assign is_esc_w = rxd_in_r == ESCAPE_BYTE;
assign replaced_w = {
(rxd_in_r == REPLACED_START_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_END_FRAME_BYTE) ? 1'b1: 1'b0,
(rxd_in_r == REPLACED_ESCAPE_BYTE) ? 1'b1: 1'b0};
assign packet_run = packet_run_r[0];
assign rxd_out = rxd_r;
assign rx_stb = out_stb[1];
assign packet_done = packet_done_r;
always @(posedge mclk) begin
if (mrst) in_stb <= 0;
else in_stb <= {in_stb[1:0], rx_in_stb};
if (mrst) rxd_in_r <= 0;
else if (rx_in_stb) rxd_in_r <= rxd_in;
if (mrst) packet_run_r[0] <= 0;
else if (flsp_start) packet_run_r[0] <= 1;
else if (flsp_end) packet_run_r[0] <= 0;
packet_run_r[1] <= packet_run_r[0];
if (!packet_run || flsp_end) payload <= 0;
else if (in_stb[0]) payload <= 1;
if (mrst) is_esc <= 0;
else if (in_stb[0]) is_esc <= is_esc_w;
if (mrst) replaced <= 0;
else if (in_stb[0]) replaced <= {3{is_esc}} & replaced_w;
if (in_stb[0]) thru <= !is_esc_w && !is_esc;
if (mrst) out_stb <= 0;
else out_stb <= {out_stb[0], in_stb[1] & payload & ~is_esc};
if (out_stb[0]) rxd_r <=
({8{thru}} & rxd_in_r) |
({8{replaced[0]}} & START_FRAME_BYTE) |
({8{replaced[1]}} & END_FRAME_BYTE) |
({8{replaced[2]}} & ESCAPE_BYTE);
packet_done_r <= !packet_run_r[0] && packet_run_r[1];
end
endmodule
sensor/serial_fslp.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_fslp
* @file serial_fslp.v
* @date 2020-12-13
* @author eyesis
*
* @brief implementation of the FSLP for Boson
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_fslp.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_fslp.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_fslp #(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91,
parameter INITIAL_CRC16 = 16'h1d0f,
// parameter BOSON_BAUD = 921600,
parameter CLK_DIV = 217,
parameter RX_DEBOUNCE = 60
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output txd, // serial data out
input rxd, // serial data in
input tx_start, // start transmit packet
input tx_done, // end transmit packet
input tx_stb, // transmit byte strobe
input [7:0] tx_byte, // transmit byte input
output tx_rdy, // crc16 ready to accept tx_in_stb
output stuffer_busy, // processing packet (not including UART)
output uart_tx_busy, // UART busy ('or' with stuffer_busy?)
output [7:0] rx_byte, // received byte output
output rx_stb, // received byte strobe
output rx_packet_run, // run received packet
output rx_packet_done // finished receiving packet (last 2 bytes - crc16)
);
wire [7:0] uart_txd;
wire [7:0] uart_rxd;
wire uart_tx_stb;
wire uart_tx_rdy;
wire stuffer_rdy;
wire uart_rx_stb;
wire [7:0] crc16_txd;
wire crc16_stb;
wire crc16_busy;
boson_uart #(
.CLK_DIV (CLK_DIV),
.RX_DEBOUNCE (RX_DEBOUNCE)
) boson_uart_i (
.mrst (mrst), // input
.mclk (mclk), // input
.txd (txd), // output
.rxd (rxd), // input
.tx_byte (uart_txd[7:0]), // input[7:0]
.tx_stb (uart_tx_stb), // input
.tx_busy (uart_tx_busy), // output
.tx_rdy (uart_tx_rdy), // output
.rx_byte (uart_rxd[7:0]), // output[7:0]
.rx_stb (uart_rx_stb) // output
);
crc16_xmodem #(
.INITIAL_CRC16(INITIAL_CRC16)
) crc16_xmodem_i (
.mrst (mrst), // input
.mclk (mclk), // input
.tx_start (tx_start), // input
.txd_in (tx_byte[7:0]), // input[7:0]
.tx_in_stb (tx_stb), // input
.tx_over (tx_done), // input
.tx_rdy (stuffer_rdy), // input
.tx_in_rdy (tx_rdy), // output
.txd_out (crc16_txd[7:0]), // output[7:0]
.tx_out_stb (crc16_stb), // output
.tx_busy (crc16_busy) // output
);
serial_stuffer #(
.START_FRAME_BYTE (START_FRAME_BYTE),
.END_FRAME_BYTE (END_FRAME_BYTE),
.ESCAPE_BYTE (ESCAPE_BYTE),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE)
) serial_stuffer_i (
.mrst (mrst), // input
.mclk (mclk), // input
.packet_run (crc16_busy), // input
.tx_in_stb (crc16_stb), // input
.txd_in (crc16_txd[7:0]), // input[7:0]
.stuffer_rdy (stuffer_rdy), // output
.uart_rdy (uart_tx_rdy), // input
.uart_stb (uart_tx_stb), // output
.uart_txd (uart_txd[7:0]), // output[7:0]
.stuffer_busy (stuffer_busy) // output
);
serial_destuffer #(
.START_FRAME_BYTE (START_FRAME_BYTE),
.END_FRAME_BYTE (END_FRAME_BYTE),
.ESCAPE_BYTE (ESCAPE_BYTE),
.REPLACED_START_FRAME_BYTE (REPLACED_START_FRAME_BYTE),
.REPLACED_END_FRAME_BYTE (REPLACED_END_FRAME_BYTE),
.REPLACED_ESCAPE_BYTE (REPLACED_ESCAPE_BYTE)
) serial_destuffer_i (
.mrst (mrst), // input
.mclk (mclk), // input
.rxd_in (uart_rxd[7:0]), // input[7:0]
.rx_in_stb (uart_rx_stb), // input
.rxd_out (rx_byte[7:0]), // output[7:0]
.rx_stb (rx_stb), // output
.packet_run (rx_packet_run), // output
.packet_done (rx_packet_done) // output
);
endmodule
sensor/serial_stuffer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> serial_stuffer
* @file serial_stuffer.v
* @date 2020-12-13
* @author eyesis
*
* @brief wrap serial packet for fslp
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* serial_stuffer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* serial_stuffer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module serial_stuffer #(
parameter START_FRAME_BYTE = 'h8E,
parameter END_FRAME_BYTE = 'hAE,
parameter ESCAPE_BYTE = 'h9E,
parameter REPLACED_START_FRAME_BYTE = 'h81,
parameter REPLACED_END_FRAME_BYTE = 'hA1,
parameter REPLACED_ESCAPE_BYTE = 'h91
)(
input mrst, // @posedge mclk, sync reset
input mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input packet_run, // goes inactive after last txd_in_stb
input tx_in_stb,
input [7:0] txd_in,
output stuffer_rdy, // stuffer ready to accept tx_in_stb
input uart_rdy, // uart ready to accept byte
output uart_stb, // write byte to UART
output [7:0] uart_txd, // byte to uart
output stuffer_busy // processing packet (not including UART)
);
reg stuffer_busy_r;
reg [1:0] stuffer_start;
reg stuffer_finsh;
reg packet_trailer;
reg packet_header;
reg escape_cyc0;
reg [2:0] escape_cyc1;
reg uart_stb_r;
reg [7:0] txd_in_r;
reg [2:0] tx_in_stb_r;
reg [2:0] need_escape;
reg [1:0] byte_out_set; //
reg [7:0] uart_txd_r;
reg tx_dav;
reg copy_in_byte;
reg stuffer_rdy_r;
assign stuffer_busy = stuffer_busy_r;
assign uart_stb = uart_stb_r;
assign uart_txd = uart_txd_r;
assign stuffer_rdy = stuffer_rdy_r;
always @(posedge mclk) begin
stuffer_start <= {stuffer_start[0], ~stuffer_busy_r & packet_run};
if (mrst) stuffer_busy_r <= 0;
else if (stuffer_start[0]) stuffer_busy_r <= 1;
else if (packet_trailer && uart_stb_r) stuffer_busy_r <= 0;
if (mrst) stuffer_rdy_r <= 0;
else if (stuffer_start || tx_in_stb || stuffer_finsh) stuffer_rdy_r <= 0;
else if (byte_out_set[1] && (!escape_cyc0)) stuffer_rdy_r <= 1;
tx_in_stb_r <= {tx_in_stb_r[1:0],tx_in_stb};
if (tx_in_stb) txd_in_r <= txd_in;
if (tx_in_stb_r[0]) need_escape <= {
(txd_in_r == START_FRAME_BYTE)? 1'b1 : 1'b0,
(txd_in_r == END_FRAME_BYTE)? 1'b1 : 1'b0,
(txd_in_r == ESCAPE_BYTE)? 1'b1 : 1'b0};
if (mrst) escape_cyc0 <= 0;
else if (tx_in_stb_r[1]) escape_cyc0 <= |need_escape;
else if (uart_stb_r) escape_cyc0 <= 0;
if (mrst) escape_cyc1 <= 0;
else if (uart_stb_r) escape_cyc1 <= {3{escape_cyc0}} & need_escape;
if (mrst) byte_out_set <= 0;
else byte_out_set <= {byte_out_set[0], tx_in_stb_r[2] | stuffer_start[1] | stuffer_finsh};
if (mrst) packet_header <= 0;
else if (stuffer_start[1]) packet_header <= 1;
else if (byte_out_set[1]) packet_header <= 0;
if (!stuffer_busy_r) packet_trailer <= 0;
else if (!packet_run) packet_trailer <= 1;
stuffer_finsh <= stuffer_rdy_r && stuffer_busy_r && packet_trailer; // !packet_run
copy_in_byte <= !need_escape && !packet_header && !packet_trailer;
if (byte_out_set[1]) uart_txd_r <=
({8{packet_header}} & START_FRAME_BYTE) |
({8{packet_trailer}} & END_FRAME_BYTE) |
({8{escape_cyc0}} & ESCAPE_BYTE) |
({8{escape_cyc1[0]}} & REPLACED_START_FRAME_BYTE) |
({8{escape_cyc1[1]}} & REPLACED_END_FRAME_BYTE) |
({8{escape_cyc1[2]}} & REPLACED_ESCAPE_BYTE) |
({8{copy_in_byte}} & txd_in_r);
if (mrst) tx_dav <= 0;
else if (byte_out_set[1]) tx_dav <= 1;
else if (uart_stb_r) tx_dav <= 0;
if (mrst) uart_stb_r <= 0;
else uart_stb_r <= !uart_stb_r && tx_dav && uart_rdy;
end
endmodule
simulation_modules/simul_103993_serializer.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> simul_103993_serializer
* @file simul_103993_serializer.v
* @date 2020-12-23
* @author eyesis
*
* @brief Serializer for Boson640 output based on SN65LVDS301
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* simul_103993_serializer.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_103993_serializer.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_103993_serializer#(
parameter PCLK_FREQ_MHZ = 27.0
)(
input [7:0] red,
input [7:0] green,
input [7:0] blue,
input hs,
input vs,
input de,
input pclk,
output [2:0] dp,
output [2:0] dn,
output clkp,
output clkn
);
localparam PERIOD = 1000.0/PCLK_FREQ_MHZ;
wire [9:0] dclocks;
assign #(PERIOD/20) dclocks[9:0] = ~{dclocks[8:0], pclk};
/*
assign #(PERIOD/20) dclocks[0] = pclk;
assign #(PERIOD/20) dclocks[1] = dclocks[0];
assign #(PERIOD/20) dclocks[2] = dclocks[1];
assign #(PERIOD/20) dclocks[3] = dclocks[2];
assign #(PERIOD/20) dclocks[4] = dclocks[3];
assign #(PERIOD/20) dclocks[5] = dclocks[4];
assign #(PERIOD/20) dclocks[6] = dclocks[5];
assign #(PERIOD/20) dclocks[7] = dclocks[6];
assign #(PERIOD/20) dclocks[8] = dclocks[7];
assign #(PERIOD/20) dclocks[9] = dclocks[8];
*/
wire clk10 = ^dclocks[9:0];
reg [9:0] r_red;
reg [9:0] r_green;
reg [9:0] r_blue;
reg [9:0] sr_red;
reg [9:0] sr_green;
reg [9:0] sr_blue;
reg [9:0] sr_clk;
reg [1:0] clk_r;
reg set_sr;
wire cp = (^red) ^ (^green) ^ (^blue) ^ vs ^ hs ^ de;
assign dp = {sr_blue[9],sr_green[9], sr_red[9]};
assign dn = ~{sr_blue[9],sr_green[9], sr_red[9]};
assign clkp = sr_clk [9];
assign clkn = ~sr_clk [9];
always @ (posedge pclk) begin
r_red <= {red, vs, cp};
r_green <= {green, hs, 1'b0};
r_blue <= {blue, de, 1'b0};
end
always @ (posedge clk10) begin
clk_r <= {clk_r[0], pclk};
set_sr <= clk_r[0] && !clk_r[0];
if (set_sr) begin
sr_red <= r_red;
sr_green <= r_green;
sr_blue <= r_blue;
sr_clk <= 10'b1111100000;
end else begin
sr_red <= {sr_red[8:0], 1'b0};
sr_green <= {sr_green[8:0], 1'b0};
sr_blue <= {sr_blue[8:0], 1'b0};
sr_clk <= {sr_clk[8:0], 1'b0};
end
end
endmodule
simulation_modules/simul_boson640.v 0 → 100644
View file @ 043d4849
/*!
* <b>Module:</b> simul_boson640
* @file simul_boson640.v
* @date 2020-12-23
* @author eyesis
*
* @brief Simulating Boson640
*
* @copyright Copyright (c) 2020 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* simul_boson640.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_boson640.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_boson640#(
parameter DATA_FILE = "/input_data/pattern_160_120_16.dat", //
parameter WIDTH = 640, // overwrite with 160
parameter HEIGHT = 513, // overwrite with 120
parameter OUT_BITS = 16,
parameter FPS = 60.0, // actual fps of the internal generator
parameter HSW = 8, // horizontal sync width
parameter FP_BP = 102,
parameter FP = 52, // FP_BP = 52+50
parameter VSW = 87 // with telemetry, in eows
)(
input mrst,
input single,
input ext_sync,
output [15:0] pxd,
output pclk,
output dvalid,
output vsync,
output hsync,
input uart_in,
output uart_out // will just copy when not reset;
);
`ifndef ROOTPATH
`include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used
`ifndef ROOTPATH
`define ROOTPATH "."
`endif
`endif
localparam CLK_PER_FRAME = 450000;
localparam CLK_PERIOD = 1000000000.0/ (FPS * CLK_PER_FRAME); // ns
localparam BP = FP_BP - FP;
reg [OUT_BITS-1:0] sensor_data[0 : WIDTH * HEIGHT - 1]; // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [OUT_BITS-1:0] pxd_r;
reg pclk_r = 0;
reg [1:0] frame_state; // 00 - reset, 01 vsync, 10 - out lines
// reg [1:0] frame_state_d; // previous state
reg [3:0] line_state;
reg ext_sync_d;
integer pix_cntr;
integer line_cntr;
integer frame_pixel;
wire last_in_line;
wire start_frame;
wire start_line;
wire last_line;
wire pre_dav;
reg dvalid_r;
localparam FSTATE_IDLE = 2'b00;
localparam FSTATE_VSYNC = 2'b01;
localparam FSTATE_OUT = 2'b10;
localparam LSTATE_IDLE = 4'b0000;
localparam LSTATE_HS = 4'b0001;
localparam LSTATE_FP = 4'b0010;
localparam LSTATE_OUT = 4'b0100;
localparam LSTATE_BP = 4'b1000;
assign pclk = ~pclk_r;
assign uart_out = uart_in && !mrst;
assign last_line = (frame_state == FSTATE_OUT) && (line_cntr == 0);
assign last_in_line = (line_state == LSTATE_BP) && (pix_cntr == 0);
assign start_frame = ((frame_state == FSTATE_IDLE) || (last_line && last_in_line)) && (!single | (ext_sync && !ext_sync_d));
assign start_line = start_frame || ((frame_state != FSTATE_IDLE) && !last_line && last_in_line);
assign pre_dav = (frame_state == FSTATE_OUT) && ((pix_cntr == 0)? (line_state == LSTATE_FP) : (line_state == LSTATE_OUT));
assign dvalid = dvalid_r;
assign pxd = pxd_r;
assign vsync = frame_state != FSTATE_VSYNC; // active low
assign hsync = line_state != LSTATE_HS; // active low
initial begin
$readmemh({`ROOTPATH,DATA_FILE},sensor_data);
end
always #(CLK_PERIOD/2) pclk_r <= mrst ? 1'b0: ~pclk_r;
always @ (posedge pclk_r) begin
dvalid_r <= pre_dav && !mrst;
if (mrst) ext_sync_d <= 0;
else ext_sync_d <= ext_sync;
// frame_state_d <=frame_state;
if (mrst) begin
frame_state <= FSTATE_IDLE;
end else begin
case (frame_state)
FSTATE_IDLE: begin
if (!single | (ext_sync && !ext_sync_d)) begin
frame_state <= FSTATE_VSYNC;
line_cntr <= VSW - 1;
end
end
FSTATE_VSYNC: if (last_in_line) begin
if (line_cntr == 0) begin
frame_state <= FSTATE_OUT;
line_cntr <= HEIGHT - 1;
end else begin
line_cntr <= line_cntr - 1;
end
end
FSTATE_OUT: if (last_in_line) begin
if (line_cntr == 0) begin
frame_state <= (!single | (ext_sync && !ext_sync_d)) ? FSTATE_VSYNC : FSTATE_IDLE;
line_cntr <= VSW - 1;
end else begin
line_cntr <= line_cntr - 1;
end
end
default: frame_state <= FSTATE_IDLE;
endcase
end
if (mrst) begin
line_state <= 0;
pix_cntr <= HSW - 1;
end else if (start_line) begin
line_state <= LSTATE_HS;
pix_cntr <= HSW - 1;
end else begin
case (line_state)
LSTATE_HS: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_FP;
pix_cntr <= FP - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_FP: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_OUT;
pix_cntr <= WIDTH - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_OUT: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_BP;
pix_cntr <= BP - 1;
end else begin
pix_cntr <= pix_cntr -1;
end
end
LSTATE_BP: begin
if (pix_cntr == 0) begin
line_state <= LSTATE_IDLE;
end else begin
pix_cntr <= pix_cntr -1;
end
end
default: line_state <= LSTATE_IDLE;
endcase
end
if (start_frame) frame_pixel <= 0;
else if (pre_dav) frame_pixel <= frame_pixel + 1;
if (pre_dav) pxd_r <= sensor_data[frame_pixel];
end
endmodule
system_defines.vh
View file @ 043d4849
...@@ -64,8 +64,23 @@ ...@@ -64,8 +64,23 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
`define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/ `define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/ // `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`ifdef BOSON
`elsif LWIR
`elsif HISPI
`else
`define PAR12 // use default sensors interface
`endif
`ifdef BOSON
`define PCLK_MASTER /* pclk is generated by the sensors, no global pclk and prst!*/
`endif
`define MON_HISPI // Measure HISPI timing `define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
......
util_modules/fifo_sameclock_control.v
View file @ 043d4849
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* @date 2016-01-20 * @date 2016-01-20
* @author Andrey Filippov * @author Andrey Filippov
* *
* @brief BRAM-based fifo control, uses BARM output registers * @brief BRAM-based fifo control, uses BRAM output registers
* *
* @copyright Copyright (c) 2016 Elphel, Inc . * @copyright Copyright (c) 2016 Elphel, Inc .
* *
......
util_modules/status_read.v
View file @ 043d4849
...@@ -104,7 +104,8 @@ module status_read#( ...@@ -104,7 +104,8 @@ module status_read#(
ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor ram [DATA_2DEPTH-1] = 1; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor
`elsif LWIR `elsif LWIR
ram [DATA_2DEPTH-1] = 2; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor ram [DATA_2DEPTH-1] = 2; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor
`elsif BOSON
ram [DATA_2DEPTH-1] = 3; //0 - parallel sensor, 1 - HiSPi sensor, 2 - LWIR 160x120 sensor 3- BOSON 640x512
`endif `endif
end end
always @ (posedge axi_clk) begin always @ (posedge axi_clk) begin
......
x393.v
View file @ 043d4849
...@@ -87,6 +87,51 @@ module x393 #( ...@@ -87,6 +87,51 @@ module x393 #(
inout sns4_sda, inout sns4_sda,
inout sns4_ctl, inout sns4_ctl,
inout sns4_pg, inout sns4_pg,
`elsif BOSON
input [3:0] sns1_dp,
input [3:0] sns1_dn,
inout [7:4] sns1_dp74, // other non-diff signals
inout [7:4] sns1_dn74, // other non-diff signals
input sns1_clkp,
input sns1_clkn,
inout sns1_scl,
inout sns1_sda,
inout sns1_ctl,
inout sns1_pg,
input [3:0] sns2_dp,
input [3:0] sns2_dn,
inout [7:4] sns2_dp74, // other non-diff signals
inout [7:4] sns2_dn74, // other non-diff signals
input sns2_clkp,
input sns2_clkn,
inout sns2_scl,
inout sns2_sda,
inout sns2_ctl,
inout sns2_pg,
input [3:0] sns3_dp,
input [3:0] sns3_dn,
inout [7:4] sns3_dp74, // other non-diff signals
inout [7:4] sns3_dn74, // other non-diff signals
input sns3_clkp,
input sns3_clkn,
inout sns3_scl,
inout sns3_sda,
inout sns3_ctl,
inout sns3_pg,
input [3:0] sns4_dp,
input [3:0] sns4_dn,
inout [7:4] sns4_dp74, // other non-diff signals
inout [7:4] sns4_dn74, // other non-diff signals
input sns4_clkp,
input sns4_clkn,
inout sns4_scl,
inout sns4_sda,
inout sns4_ctl,
inout sns4_pg,
`elsif LWIR `elsif LWIR
inout [4:0] sns1_dp40, inout [4:0] sns1_dp40,
inout [4:0] sns1_dn40, inout [4:0] sns1_dn40,
...@@ -314,8 +359,16 @@ module x393 #( ...@@ -314,8 +359,16 @@ module x393 #(
// sensor pixel rate clock likely to originate from the external clock // sensor pixel rate clock likely to originate from the external clock
//TODO: Create missing clocks //TODO: Create missing clocks
`ifdef PCLK_MASTER
wire [3:0] pclk; // global clock, sensor pixel rate (96 MHz)
wire [3:0] prst; // @ posedge pclk
wire [3:0] locked_pclk; // display all/any?
`else
wire pclk; // global clock, sensor pixel rate (96 MHz) wire pclk; // global clock, sensor pixel rate (96 MHz)
wire prst; // @ posedge pclk
wire locked_pclk;
`endif
`ifdef USE_PCLK2X `ifdef USE_PCLK2X
wire pclk2x; // global clock, sensor double pixel rate (192 MHz) wire pclk2x; // global clock, sensor double pixel rate (192 MHz)
`endif `endif
...@@ -330,7 +383,7 @@ module x393 #( ...@@ -330,7 +383,7 @@ module x393 #(
assign logger_clk = camsync_clk; assign logger_clk = camsync_clk;
wire mrst; // @ posedge mclk wire mrst; // @ posedge mclk
wire prst; // @ posedge pclk // wire prst; // @ posedge pclk
wire xrst; // @ posedge xclk wire xrst; // @ posedge xclk
wire crst; // @ posedge camsync_clk wire crst; // @ posedge camsync_clk
wire lrst; // @ posedge logger_clk; wire lrst; // @ posedge logger_clk;
...@@ -339,7 +392,7 @@ module x393 #( ...@@ -339,7 +392,7 @@ module x393 #(
wire locked_sync_clk; wire locked_sync_clk;
wire locked_xclk; wire locked_xclk;
wire locked_pclk; // wire locked_pclk;
wire locked_hclk; wire locked_hclk;
wire idelay_ctrl_reset; // to reset idelay_cntrl wire idelay_ctrl_reset; // to reset idelay_cntrl
...@@ -614,8 +667,9 @@ module x393 #( ...@@ -614,8 +667,9 @@ module x393 #(
// Timestamp messages (@mclk) - combine to a single ts_data? // Timestamp messages (@mclk) - combine to a single ts_data?
wire ts_pre_logger_stb; // input logger timestamp sync (@logger_clk) wire ts_pre_logger_stb; // input logger timestamp sync (@logger_clk)
wire [7:0] ts_logegr_data; // input[7:0] loger timestamp data (@logger_clk) wire [7:0] ts_logegr_data; // input[7:0] loger timestamp data (@logger_clk)
`ifdef LWIR
wire khz; // 1 KHz 50% duty wire khz; // 1 KHz 50% duty
`endif
// Compressor signals for interrupts generation // Compressor signals for interrupts generation
wire [3:0] eof_written_mclk; // output // SuppressThisWarning VEditor - (yet) unused wire [3:0] eof_written_mclk; // output // SuppressThisWarning VEditor - (yet) unused
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
...@@ -1702,8 +1756,9 @@ assign axi_grst = axi_rst_pre; ...@@ -1702,8 +1756,9 @@ assign axi_grst = axi_rst_pre;
wire [ 1:0] saxi1_bresp; wire [ 1:0] saxi1_bresp;
sensors393 #( sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR), // moving to the end to be always present
.SENSOR_BASE_INC (SENSOR_BASE_INC), // .SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
// .SENSOR_BASE_INC (SENSOR_BASE_INC),
.HIST_SAXI_ADDR_REL (HIST_SAXI_ADDR_REL), .HIST_SAXI_ADDR_REL (HIST_SAXI_ADDR_REL),
.HIST_SAXI_MODE_ADDR_REL (HIST_SAXI_MODE_ADDR_REL), .HIST_SAXI_MODE_ADDR_REL (HIST_SAXI_MODE_ADDR_REL),
.SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE), .SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE),
...@@ -1793,11 +1848,15 @@ assign axi_grst = axi_rst_pre; ...@@ -1793,11 +1848,15 @@ assign axi_grst = axi_rst_pre;
`else `else
.SENSIO_CTRL (SENSIO_CTRL), .SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST), .SENS_CTRL_MRST (SENS_CTRL_MRST),
`ifndef BOSON
.SENS_CTRL_ARST (SENS_CTRL_ARST), .SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO), .SENS_CTRL_ARO (SENS_CTRL_ARO),
`endif
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM), .SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
`ifdef HISPI `ifdef HISPI
.SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED), .SENS_CTRL_IGNORE_EMBED (SENS_CTRL_IGNORE_EMBED),
`elsif BOSON
//??
`else `else
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK), .SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
`endif `endif
...@@ -1805,6 +1864,16 @@ assign axi_grst = axi_rst_pre; ...@@ -1805,6 +1864,16 @@ assign axi_grst = axi_rst_pre;
`ifdef HISPI `ifdef HISPI
.SENS_CTRL_GP0 (SENS_CTRL_GP0), .SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1), .SENS_CTRL_GP1 (SENS_CTRL_GP1),
`elsif BOSON
.SENS_CTRL_GP0 (SENS_CTRL_GP0),
.SENS_CTRL_GP1 (SENS_CTRL_GP1),
.SENS_CTRL_GP2 (SENS_CTRL_GP2),
.SENS_CTRL_GP3 (SENS_CTRL_GP3),
.SENS_UART_EXTIF_EN (SENS_UART_EXTIF_EN),
.SENS_UART_XMIT_RST (SENS_UART_XMIT_RST),
.SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
`else `else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS), .SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
...@@ -1812,13 +1881,17 @@ assign axi_grst = axi_rst_pre; ...@@ -1812,13 +1881,17 @@ assign axi_grst = axi_rst_pre;
.SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN), .SENS_CTRL_QUADRANTS_EN (SENS_CTRL_QUADRANTS_EN),
`endif `endif
.SENSIO_STATUS (SENSIO_STATUS), .SENSIO_STATUS (SENSIO_STATUS),
`ifndef BOSON
.SENSIO_JTAG (SENSIO_JTAG), .SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN), .SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG), .SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK), .SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS), .SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI), .SENS_JTAG_TDI (SENS_JTAG_TDI),
`ifndef HISPI `endif
`ifdef HISPI
`elsif BOSON
`else
.SENSIO_WIDTH (SENSIO_WIDTH), .SENSIO_WIDTH (SENSIO_WIDTH),
`endif `endif
.SENSIO_DELAYS (SENSIO_DELAYS), .SENSIO_DELAYS (SENSIO_DELAYS),
...@@ -1839,6 +1912,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1839,6 +1912,7 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD), .SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW), .SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI `ifdef HISPI
`elsif BOSON
`elsif LWIR `elsif LWIR
.VOSPI_DRIVE (VOSPI_DRIVE), .VOSPI_DRIVE (VOSPI_DRIVE),
.VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR), .VOSPI_IBUF_LOW_PWR (VOSPI_IBUF_LOW_PWR),
...@@ -1886,12 +1960,10 @@ assign axi_grst = axi_rst_pre; ...@@ -1886,12 +1960,10 @@ assign axi_grst = axi_rst_pre;
.VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap) .VOSPI_MRST_MS (VOSPI_MRST_MS), // 200, // master reset duration in ms (so even all channels would overlap)
.VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000 .VOSPI_MRST_AFTER_MS (VOSPI_MRST_AFTER_MS), // 2000
.VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185 .VOSPI_SPI_TIMEOUT_MS (VOSPI_SPI_TIMEOUT_MS), // 185
`else `else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH), .SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH), .SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY), .SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
`endif `endif
.HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK), .HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK),
.HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH), .HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH),
...@@ -1905,30 +1977,27 @@ assign axi_grst = axi_rst_pre; ...@@ -1905,30 +1977,27 @@ assign axi_grst = axi_rst_pre;
.SENS_SYNC_LBITS (SENS_SYNC_LBITS), .SENS_SYNC_LBITS (SENS_SYNC_LBITS),
.SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT), .SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT),
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS), .SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER) .SENS_SYNC_MINPER (SENS_SYNC_MINPER),
// start with comma
`ifdef LWIR `ifdef LWIR
`else `else
,.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE) .SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
`endif `endif
// start with comma
`ifdef HISPI `ifdef HISPI
,.PXD_CAPACITANCE (PXD_CAPACITANCE), .PXD_CAPACITANCE (PXD_CAPACITANCE),
.PXD_CLK_DIV (PXD_CLK_DIV), .PXD_CLK_DIV (PXD_CLK_DIV),
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS) .PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif `endif
// start with comma
`ifdef LWIR `ifdef LWIR
`else `else
,.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH), .SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_BANDWIDTH (SENS_BANDWIDTH), .SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR), .CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR), .CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
...@@ -1949,12 +2018,10 @@ assign axi_grst = axi_rst_pre; ...@@ -1949,12 +2018,10 @@ assign axi_grst = axi_rst_pre;
.SENS_REF_JITTER2 (SENS_REF_JITTER2), .SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD) .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
`endif `endif
`ifdef HISPI `ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0), .HISPI_DELAY_CLK0 (HISPI_DELAY_CLK0),
.HISPI_DELAY_CLK1 (HISPI_DELAY_CLK1), .HISPI_DELAY_CLK1 (HISPI_DELAY_CLK1),
...@@ -1975,21 +2042,28 @@ assign axi_grst = axi_rst_pre; ...@@ -1975,21 +2042,28 @@ assign axi_grst = axi_rst_pre;
.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE), .HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR), .HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE), .HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD) .HISPI_IOSTANDARD (HISPI_IOSTANDARD),
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY) .DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY),
`endif `endif
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC)
) sensors393_i ( ) sensors393_i (
// .rst (axi_rst), // input // .rst (axi_rst), // input
.pclk (pclk), // input `ifdef PCLK_MASTER
.pclk (pclk), // output [3:0]
.locked_pclk (locked_pclk), // output [3:0]
`else
.pclk (pclk), // input / output [3:0]
`endif
`ifdef USE_PCLK2X `ifdef USE_PCLK2X
.pclk2x (pclk2x), // input .pclk2x (pclk2x), // input
`endif `endif
.ref_clk (ref_clk), // input .ref_clk (ref_clk), // input
.dly_rst (idelay_ctrl_reset), // input .dly_rst (idelay_ctrl_reset), // input
.mrst (mrst), // input .mrst (mrst), // input
.prst (prst), // input .prst (prst), // input / input [3:0]
.arst (arst), // input .arst (arst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -2003,6 +2077,11 @@ assign axi_grst = axi_rst_pre; ...@@ -2003,6 +2077,11 @@ assign axi_grst = axi_rst_pre;
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0] .sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug .sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug .sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
`elsif BOSON
.sns_dp ({sns4_dp, sns3_dp, sns2_dp, sns1_dp}), // input[3:0]
.sns_dn ({sns4_dn, sns3_dn, sns2_dn, sns1_dn}), // input[3:0]
.sns_dp74 ({sns4_dp74, sns3_dp74, sns2_dp74, sns1_dp74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
.sns_dn74 ({sns4_dn74, sns3_dn74, sns2_dn74, sns1_dn74}), // inout[7:4] @SuppressThisWarning VEditor vdt-bug
`elsif LWIR `elsif LWIR
.sns_dp40 ({sns4_dp40, sns3_dp40, sns2_dp40, sns1_dp40}), // input[19:0] .sns_dp40 ({sns4_dp40, sns3_dp40, sns2_dp40, sns1_dp40}), // input[19:0]
.sns_dn40 ({sns4_dn40, sns3_dn40, sns2_dn40, sns1_dn40}), // input[19:0] .sns_dn40 ({sns4_dn40, sns3_dn40, sns2_dn40, sns1_dn40}), // input[19:0]
...@@ -2069,8 +2148,10 @@ assign axi_grst = axi_rst_pre; ...@@ -2069,8 +2148,10 @@ assign axi_grst = axi_rst_pre;
`ifdef DEBUG_SENS_MEM_PAGES `ifdef DEBUG_SENS_MEM_PAGES
,.dbg_rpage (dbg_rpage[7:0]) // output[7:0] ,.dbg_rpage (dbg_rpage[7:0]) // output[7:0]
,.dbg_wpage (dbg_wpage[7:0]) // output[7:0] ,.dbg_wpage (dbg_wpage[7:0]) // output[7:0]
`endif `endif
`ifdef LWIR
,.khz (khz) // input 1 KHz 50% duty ,.khz (khz) // input 1 KHz 50% duty
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.debug_do (debug_ring[0]), // output ,.debug_do (debug_ring[0]), // output
.debug_sl (debug_sl), // input .debug_sl (debug_sl), // input
...@@ -2432,7 +2513,11 @@ assign axi_grst = axi_rst_pre; ...@@ -2432,7 +2513,11 @@ assign axi_grst = axi_rst_pre;
.ts_logger_snap (logger_snap), // input .ts_logger_snap (logger_snap), // input
.ts_logger_stb (ts_pre_logger_stb), // output .ts_logger_stb (ts_pre_logger_stb), // output
.ts_logger_data (ts_logegr_data), // output[7:0] .ts_logger_data (ts_logegr_data), // output[7:0]
`ifdef LWIR
.khz (khz) // output // 1 KHz 50% output .khz (khz) // output // 1 KHz 50% output
`else
.khz () // output // 1 KHz 50% output
`endif
); );
event_logger #( event_logger #(
...@@ -2654,7 +2739,11 @@ assign axi_grst = axi_rst_pre; ...@@ -2654,7 +2739,11 @@ assign axi_grst = axi_rst_pre;
.ffclk1n_pad (ffclk1n), // input .ffclk1n_pad (ffclk1n), // input
.aclk (axi_aclk), // output .aclk (axi_aclk), // output
.hclk (hclk), // output .hclk (hclk), // output
`ifdef PCLK_MASTER
.pclk (), // output // generated by each sensor
`else
.pclk (pclk), // output .pclk (pclk), // output
`endif
`ifdef USE_PCLK2X `ifdef USE_PCLK2X
.pclk2x (pclk2x), // output .pclk2x (pclk2x), // output
`endif `endif
...@@ -2668,17 +2757,25 @@ assign axi_grst = axi_rst_pre; ...@@ -2668,17 +2757,25 @@ assign axi_grst = axi_rst_pre;
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0] .extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
.locked_sync_clk (locked_sync_clk), // output // always 1 .locked_sync_clk (locked_sync_clk), // output // always 1
.locked_xclk (locked_xclk), // output // always 1 .locked_xclk (locked_xclk), // output // always 1
`ifdef PCLK_MASTER
.locked_pclk (), // output
`else
.locked_pclk (locked_pclk), // output .locked_pclk (locked_pclk), // output
`endif
.locked_hclk (locked_hclk) // output .locked_hclk (locked_hclk) // output
); );
sync_resets #( sync_resets #(
.WIDTH(7), `ifdef PCLK_MASTER
.WIDTH(10), // pclk[3:0], prst[3:0], locked_pclk[3:0]
`else
.WIDTH(7), // pclk, prst, locked_pclk
`endif
.REGISTER(4) .REGISTER(4)
) sync_resets_i ( ) sync_resets_i (
.arst (axi_rst_pre), // input .arst (axi_rst_pre), // input
.locked ({locked_hclk, 1'b1, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked}), // input .locked ({locked_hclk, 1'b1, locked_sync_clk, locked_sync_clk, locked_xclk, locked_pclk, mcntrl_locked}), // input
.clk ({hclk, axi_aclk, logger_clk, camsync_clk, xclk, pclk, mclk}), // input[6:0] .clk ({hclk, axi_aclk, logger_clk, camsync_clk, xclk, pclk, mclk}), // input[6:0]
.rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0] .rst ({hrst, arst, lrst, crst, xrst, prst, mrst}) // output[6:0]
); );
// Changed aclk to master (it is the source of most orthers) // Changed aclk to master (it is the source of most orthers)
......
x393_global.tcl
View file @ 043d4849
...@@ -52,11 +52,23 @@ while { [gets $infile line] >= 0 } { ...@@ -52,11 +52,23 @@ while { [gets $infile line] >= 0 } {
} }
} }
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile close $infile
if { $LWIR} { if { $LWIR} {
puts "x393_global.tcl: using LWIR sensors" puts "x393_global.tcl: using LWIR sensors"
} elseif { $HISPI} { } elseif { $HISPI} {
puts "x393_global.tcl: using HISPI sensors" puts "x393_global.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else { } else {
puts "x393_global.tcl: using parallel sensors" puts "x393_global.tcl: using parallel sensors"
} }
......
x393_placement.tcl
View file @ 043d4849
...@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } { ...@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } {
} }
} }
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile close $infile
if { $LWIR} { if { $LWIR} {
puts "x393_placement.tcl: using LWIR sensors" puts "x393_placement.tcl: using LWIR sensors"
} elseif { $HISPI} { } elseif { $HISPI} {
puts "x393_placement.tcl: using HISPI sensors" puts "x393_placement.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else { } else {
puts "x393_placement.tcl: using parallel sensors" puts "x393_placement.tcl: using parallel sensors"
} }
...@@ -139,7 +151,25 @@ set_property PACKAGE_PIN W13 [get_ports {ffclk1n}] ...@@ -139,7 +151,25 @@ set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# ================= Sensor port 0 ================= # ================= Sensor port 0 =================
if { $LWIR } { # BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp74[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn74[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp74[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn74[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp74[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn74[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp74[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN T10 [get_ports {sns1_dp40[0]}] set_property PACKAGE_PIN T10 [get_ports {sns1_dp40[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn40[0]}] set_property PACKAGE_PIN T9 [get_ports {sns1_dn40[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp40[1]}] set_property PACKAGE_PIN U10 [get_ports {sns1_dp40[1]}]
...@@ -200,7 +230,25 @@ set_property PACKAGE_PIN U8 [get_ports {sns1_pg}] ...@@ -200,7 +230,25 @@ set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 ================= # ================= Sensor port 1 =================
if { $LWIR } { # BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp74[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn74[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp74[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn74[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp74[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn74[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp74[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN U15 [get_ports {sns2_dp40[0]}] set_property PACKAGE_PIN U15 [get_ports {sns2_dp40[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn40[0]}] set_property PACKAGE_PIN U14 [get_ports {sns2_dn40[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp40[1]}] set_property PACKAGE_PIN V15 [get_ports {sns2_dp40[1]}]
...@@ -260,7 +308,25 @@ set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}] ...@@ -260,7 +308,25 @@ set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}] set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 ================= # ================= Sensor port 2 =================
if { $LWIR } { # BOSON same as HISPI
if { $BOSON } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp74[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn74[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp74[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn74[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp74[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn74[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp74[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp40[0]}] set_property PACKAGE_PIN AA22 [get_ports {sns3_dp40[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn40[0]}] set_property PACKAGE_PIN AB22 [get_ports {sns3_dn40[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp40[1]}] set_property PACKAGE_PIN W21 [get_ports {sns3_dp40[1]}]
...@@ -320,7 +386,24 @@ set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}] ...@@ -320,7 +386,24 @@ set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}] set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 ================= # ================= Sensor port 3 =================
if { $LWIR } { if { $BOSON } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp74[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn74[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp74[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn74[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp74[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn74[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp74[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn74[7]}]
} elseif { $LWIR } {
set_property PACKAGE_PIN V17 [get_ports {sns4_dp40[0]}] set_property PACKAGE_PIN V17 [get_ports {sns4_dp40[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn40[0]}] set_property PACKAGE_PIN W18 [get_ports {sns4_dn40[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp40[1]}] set_property PACKAGE_PIN Y19 [get_ports {sns4_dp40[1]}]
......
x393_timing.tcl
View file @ 043d4849
...@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } { ...@@ -51,11 +51,23 @@ while { [gets $infile line] >= 0 } {
} }
} }
set BOSON 0
seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
set BOSON 1
break
}
}
close $infile close $infile
if { $LWIR} { if { $LWIR} {
puts "x393_timing.tcl: using LWIR sensors" puts "x393_timing.tcl: using LWIR sensors"
} elseif { $HISPI} { } elseif { $HISPI} {
puts "x393_timing.tcl: using HISPI sensors" puts "x393_timing.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
} else { } else {
puts "x393_timing.tcl: using parallel sensors" puts "x393_timing.tcl: using parallel sensors"
} }
...@@ -77,7 +89,9 @@ create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}] ...@@ -77,7 +89,9 @@ create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated #Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ] create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
if { $LWIR} { if { $BOSON} {
# Nothing here yet
} elseif { $LWIR} {
# Nothing here yet # Nothing here yet
} elseif {$HISPI} { } elseif {$HISPI} {
#WARNING: [Vivado 12-4777] Setting CLOCK_DEDICATED_ROUTE constraint on the PARENT net instead of the specified net segment (net name: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in). Placer only honors CLOCK_DEDICATED_ROUTE when set on the PARENT net, e.g. net segment directly connected to the driver. To eliminate this message, please update your constraint to specify the PARENT net instead. [/home/xilinx/vdt/x393/x393_timing.tcl:68] #WARNING: [Vivado 12-4777] Setting CLOCK_DEDICATED_ROUTE constraint on the PARENT net instead of the specified net segment (net name: sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in). Placer only honors CLOCK_DEDICATED_ROUTE when set on the PARENT net, e.g. net segment directly connected to the driver. To eliminate this message, please update your constraint to specify the PARENT net instead. [/home/xilinx/vdt/x393/x393_timing.tcl:68]
......
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