working on boson implementaion, fixed old bug in python code (043d4849) · Commits · Elphel / x393

cocotb/x393_dut.v

+219 −57

Original line number	Original line	Diff line number	Diff line
	@@ -44,7 +44,7 @@
	`include "system_defines.vh"		`include "system_defines.vh"
	module x393_dut#(		module x393_dut#(
	`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used		`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
	`include "includes/x393_simulation_parameters.vh"		`include "includes/x393_simulation_parameters.vh" //SuppressThisWarning Veditor UNUSED
	)(		)(
	output dutm0_aclk,		output dutm0_aclk,
	output reset_out,		output reset_out,
	@@ -409,7 +409,7 @@ module x393_dut#(
	parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor		parameter BLANK_ROWS_BEFORE= 8; // 1; //8; ///2+2 - a little faster than compressor
	parameter BLANK_ROWS_AFTER= 8; // 1; //8;		parameter BLANK_ROWS_AFTER= 8; // 1; //8;
	`endif		`endif
	parameter TRIG_LINES= 8;		parameter TRIG_LINES= 8; //SuppressThisWarning Veditor UNUSED
	parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED		parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
	parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used		parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG // SuppressThisWarning VEditor - not used
	`ifdef PF		`ifdef PF
	@@ -422,21 +422,21 @@ module x393_dut#(
	`endif		`endif
	parameter WOI_MARGINS = 0; // 4;		parameter WOI_MARGINS = 0; // 4;

	parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;		parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK; //SuppressThisWarning Veditor UNUSED
	parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED		parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
	parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED		parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
	parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used		parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
	parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;		parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
	parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;		parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
	// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
	// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
	// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);


	// ========================== end of parameters from x353 ===================================		// ========================== end of parameters from x353 ===================================
	reg [639:0] TEST_TITLE="abcdef"; //SuppressThisWarning VEditor		reg [639:0] TEST_TITLE="abcdef"; //SuppressThisWarning VEditor

	// Sensor signals - as on sensor pads		// Sensor signals - as on sensor pads
			`ifdef LWIR
			`elsif BOSON
			`else // PAR12 od HISPI
	wire PX1_MCLK; // input sensor input clock		wire PX1_MCLK; // input sensor input clock
	wire PX1_MRST; // input		wire PX1_MRST; // input
	wire PX1_ARO; // input		wire PX1_ARO; // input
	@@ -485,8 +485,9 @@ module x393_dut#(
	wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused		wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
	wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused		wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
	wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused		wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
			`endif
	// for LWIR -		// for LWIR -
			`ifdef LWIR
	wire LWIR1_SPI_MISO;		wire LWIR1_SPI_MISO;
	wire LWIR1_SPI_MOSI;		wire LWIR1_SPI_MOSI;
	wire LWIR1_SPI_CS;		wire LWIR1_SPI_CS;
	@@ -550,7 +551,7 @@ module x393_dut#(
	wire LWIR4_MIPI_DN; // not implemented		wire LWIR4_MIPI_DN; // not implemented
	wire LWIR4_MIPI_CLKP; // not implemented		wire LWIR4_MIPI_CLKP; // not implemented
	wire LWIR4_MIPI_CLKN; // not implemented		wire LWIR4_MIPI_CLKN; // not implemented
			`endif



	@@ -596,8 +597,8 @@ module x393_dut#(
	localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock		localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
	localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock		localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock
	`else		`else
	localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock		localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
	localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock		localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock // SuppressThisWarning VEditor - may be unused
	`endif		`endif
	`ifdef HISPI		`ifdef HISPI
	localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT		localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT
	@@ -695,6 +696,8 @@ module x393_dut#(
	assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor		assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
	assign PX4_ARST = sns4_dn[7]; // same as GP[3]		assign PX4_ARST = sns4_dn[7]; // same as GP[3]
	assign PX4_ARO = sns4_dn[5]; // same as GP[1]		assign PX4_ARO = sns4_dn[5]; // same as GP[1]
			`elsif BOSON

	`elsif LWIR		`elsif LWIR
	// connect LWIR sensor to x393		// connect LWIR sensor to x393
	assign LWIR1_SPI_MOSI = sns1_dn[0];		assign LWIR1_SPI_MOSI = sns1_dn[0];
	@@ -777,7 +780,7 @@ module x393_dut#(
	assign sns4_clkn = LWIR4_MIPI_CLKN;		assign sns4_clkn = LWIR4_MIPI_CLKN;
	assign sns4_clkp = LWIR4_MIPI_CLKP;		assign sns4_clkp = LWIR4_MIPI_CLKP;

	`else		`else // only PAR12
	//connect parallel12 sensor to sensor port 1		//connect parallel12 sensor to sensor port 1
	assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};		assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
	assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor		assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
	@@ -1093,6 +1096,11 @@ module x393_dut#(
	.sns1_dn (sns1_dn[3:0]), // inout[3:0]		.sns1_dn (sns1_dn[3:0]), // inout[3:0]
	.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]		.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
	.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]		.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
			`elsif BOSON
			.sns1_dp (sns1_dp[3:0]), // inout[3:0]
			.sns1_dn (sns1_dn[3:0]), // inout[3:0]
			.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
			.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
	`elsif LWIR		`elsif LWIR
	.sns1_dp40 (sns1_dp[4:0]), // input[4:0]		.sns1_dp40 (sns1_dp[4:0]), // input[4:0]
	.sns1_dn40 (sns1_dn[4:0]), // input[4:0]		.sns1_dn40 (sns1_dn[4:0]), // input[4:0]
	@@ -1116,6 +1124,11 @@ module x393_dut#(
	.sns2_dn (sns2_dn[3:0]), // inout[3:0]		.sns2_dn (sns2_dn[3:0]), // inout[3:0]
	.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]		.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
	.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]		.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
			`elsif BOSON
			.sns2_dp (sns2_dp[3:0]), // inout[3:0]
			.sns2_dn (sns2_dn[3:0]), // inout[3:0]
			.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
			.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
	`elsif LWIR		`elsif LWIR
	.sns2_dp40 (sns2_dp[4:0]), // input[4:0]		.sns2_dp40 (sns2_dp[4:0]), // input[4:0]
	.sns2_dn40 (sns2_dn[4:0]), // input[4:0]		.sns2_dn40 (sns2_dn[4:0]), // input[4:0]
	@@ -1141,6 +1154,11 @@ module x393_dut#(
	.sns3_dn (sns3_dn[3:0]), // inout[3:0]		.sns3_dn (sns3_dn[3:0]), // inout[3:0]
	.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]		.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
	.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]		.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
			`elsif BOSON
			.sns3_dp (sns3_dp[3:0]), // inout[3:0]
			.sns3_dn (sns3_dn[3:0]), // inout[3:0]
			.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
			.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
	`elsif LWIR		`elsif LWIR
	.sns3_dp40 (sns3_dp[4:0]), // input[4:0]		.sns3_dp40 (sns3_dp[4:0]), // input[4:0]
	.sns3_dn40 (sns3_dn[4:0]), // input[4:0]		.sns3_dn40 (sns3_dn[4:0]), // input[4:0]
	@@ -1164,6 +1182,11 @@ module x393_dut#(
	.sns4_dn (sns4_dn[3:0]), // inout[3:0]		.sns4_dn (sns4_dn[3:0]), // inout[3:0]
	.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]		.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
	.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]		.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
			`elsif BOSON
			.sns4_dp (sns4_dp[3:0]), // inout[3:0]
			.sns4_dn (sns4_dn[3:0]), // inout[3:0]
			.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
			.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
	`elsif LWIR		`elsif LWIR
	.sns4_dp40 (sns4_dp[4:0]), // input[4:0]		.sns4_dp40 (sns4_dp[4:0]), // input[4:0]
	.sns4_dn40 (sns4_dn[4:0]), // input[4:0]		.sns4_dn40 (sns4_dn[4:0]), // input[4:0]
	@@ -1705,6 +1728,9 @@ simul_axi_hp_wr #(
	);		);
	`endif		`endif

			`ifdef LWIR
			`elsif BOSON
			`else // PAR12 od HISPI
	simul_clk_mult_div #(		simul_clk_mult_div #(
	.MULTIPLIER (PIX_CLK_MULT),		.MULTIPLIER (PIX_CLK_MULT),
	.DIVISOR (PIX_CLK_DIV),		.DIVISOR (PIX_CLK_DIV),
	@@ -1744,53 +1770,8 @@ simul_axi_hp_wr #(
	.en (1'b1), // input		.en (1'b1), // input
	.clk_out (PX4_MCLK) // output		.clk_out (PX4_MCLK) // output
	);		);
			`endif


	/*
	wire lwir1_miso;
	simul_lwir160x120_vospi #(
	.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
	.WINDOW_WIDTH (160),
	.WINDOW_HEIGHT (120),
	.TELEMETRY (2), // 1),
	.FRAME_PERIOD (946969),
	.FRAME_DELAY (100),
	.MS_PERIOD (25) // 1us instead of 1 ms
	) simul_lwir160x120_vospi_i (
	.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
	.mrst ( PX1_MRST), // input
	.pwdn (1'b1), // input
	.spi_clk ( 1'b0), // input
	.spi_cs ( 1'b0), // inout
	.spi_miso ( lwir1_miso), // output
	.spi_mosi ( 1'bz), // input
	.gpio0 (), // inout
	.gpio1 (), // inout
	.gpio2 (), // inout
	.gpio3 (), // inout
	.i2c_scl (), // input
	.i2c_sda (), // inout
	.mipi_dp (), // output
	.mipi_dn (), // output
	.mipi_clkp (), // output
	.mipi_clkn (), // output

	.telemetry_rev ( 16'h7654), // input[15:0]
	.telemetry_status ( 32'h137f1248), // input[31:0]
	.telemetry_srev (64'h0123456789abcdef), // input[63:0]
	.telemetry_temp_counts ( 16'd59000), // input[15:0]
	.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
	.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
	.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
	.telemetry_agc_roi_top ( 16'd0), // input[15:0]
	.telemetry_agc_roi_left ( 16'd0), // input[15:0]
	.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
	.telemetry_agc_roi_right ( 16'd159), // input[15:0]
	.telemetry_agc_high (16'd19200), // input[15:0]
	.telemetry_agc_low ( 16'd200), // input[15:0]
	.telemetry_video_format (32'haaaa5555) // input[31:0]
	);
	*/
	`ifdef LWIR		`ifdef LWIR
	simul_lwir160x120_vospi #(		simul_lwir160x120_vospi #(
	.DATA_FILE (LWIR_DATA_FILE1),		.DATA_FILE (LWIR_DATA_FILE1),
	@@ -1965,6 +1946,187 @@ simul_axi_hp_wr #(
	);		);


			`elsif BOSON
			wire boson_single = 1;
			wire [BOSON_OUT_BITS-1:0] boson_pxd1;
			wire [BOSON_OUT_BITS-1:0] boson_pxd2;
			wire [BOSON_OUT_BITS-1:0] boson_pxd3;
			wire [BOSON_OUT_BITS-1:0] boson_pxd4;
			wire boson_pclk1;
			wire boson_pclk2;
			wire boson_pclk3;
			wire boson_pclk4;
			wire boson_dvalid1;
			wire boson_dvalid2;
			wire boson_dvalid3;
			wire boson_dvalid4;
			wire boson_vsync1;
			wire boson_vsync2;
			wire boson_vsync3;
			wire boson_vsync4;
			wire boson_hsync1;
			wire boson_hsync2;
			wire boson_hsync3;
			wire boson_hsync4;


			simul_boson640 #(
			.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
			.WIDTH (BOSON_WIDTH), // 160), 640),
			.HEIGHT (BOSON_HEIGHT), // 120), 513),
			.OUT_BITS (BOSON_OUT_BITS), // 16),
			.FPS (BOSON_FPS), // 60.0),
			.HSW (BOSON_HSW), // 8),
			.FP_BP (BOSON_FP_BP), // 22), // 102),
			.FP (BOSON_FP), // 12), 52),
			.VSW (BOSON_VSW) // 7) 87)
			) simul_boson640_1_i (
			.mrst (sns1_dp[7]), // input
			.single (boson_single), // input
			.ext_sync (sns1_ctl), // input
			.pxd (boson_pxd1), // output[15:0]
			.pclk (boson_pclk1), // output
			.dvalid (boson_dvalid1), // output
			.vsync (boson_vsync1), // output
			.hsync (boson_hsync1), // output
			.uart_in (sns1_dp[4]), // input sns_txd
			.uart_out (sns1_dn[4]) // output sns_rxd
			);

			simul_103993_serializer #(
			.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
			) simul_103993_serializer_1_i (
			.red (boson_pxd1[ 7:0]), // input[7:0]
			.green (boson_pxd1[15:8]), // input[7:0]
			.blue (8'h17), // input[7:0]
			.hs (boson_hsync1), // input
			.vs (boson_vsync1), // input
			.de (boson_dvalid1), // input
			.pclk (boson_pclk1), // input
			.dp (sns1_dp[2:0]), // output[2:0]
			.dn (sns1_dn[2:0]), // output[2:0]
			.clkp (sns1_clkp), // output
			.clkn (sns1_clkn) // output
			);

			simul_boson640 #(
			.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
			.WIDTH (BOSON_WIDTH), // 160), 640),
			.HEIGHT (BOSON_HEIGHT), // 120), 513),
			.OUT_BITS (BOSON_OUT_BITS), // 16),
			.FPS (BOSON_FPS), // 60.0),
			.HSW (BOSON_HSW), // 8),
			.FP_BP (BOSON_FP_BP), // 22), // 102),
			.FP (BOSON_FP), // 12), 52),
			.VSW (BOSON_VSW) // 7) 87)
			) simul_boson640_2_i (
			.mrst (sns2_dp[7]), // input
			.single (boson_single), // input
			.ext_sync (sns2_ctl), // input
			.pxd (boson_pxd2), // output[15:0]
			.pclk (boson_pclk2), // output
			.dvalid (boson_dvalid2), // output
			.vsync (boson_vsync2), // output
			.hsync (boson_hsync2), // output
			.uart_in (sns2_dp[4]), // input sns_txd
			.uart_out (sns2_dn[4]) // output sns_rxd
			);

			simul_103993_serializer #(
			.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
			) simul_103993_serializer_2_i (
			.red (boson_pxd2[ 7:0]), // input[7:0]
			.green (boson_pxd2[15:8]), // input[7:0]
			.blue (8'h17), // input[7:0]
			.hs (boson_hsync2), // input
			.vs (boson_vsync2), // input
			.de (boson_dvalid2), // input
			.pclk (boson_pclk2), // input
			.dp (sns2_dp[2:0]), // output[2:0]
			.dn (sns2_dn[2:0]), // output[2:0]
			.clkp (sns2_clkp), // output
			.clkn (sns2_clkn) // output
			);

			simul_boson640 #(
			.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
			.WIDTH (BOSON_WIDTH), // 160), 640),
			.HEIGHT (BOSON_HEIGHT), // 120), 513),
			.OUT_BITS (BOSON_OUT_BITS), // 16),
			.FPS (BOSON_FPS), // 60.0),
			.HSW (BOSON_HSW), // 8),
			.FP_BP (BOSON_FP_BP), // 22), // 102),
			.FP (BOSON_FP), // 12), 52),
			.VSW (BOSON_VSW) // 7) 87)
			) simul_boson640_3_i (
			.mrst (sns3_dp[7]), // input
			.single (boson_single), // input
			.ext_sync (sns3_ctl), // input
			.pxd (boson_pxd3), // output[15:0]
			.pclk (boson_pclk3), // output
			.dvalid (boson_dvalid3), // output
			.vsync (boson_vsync3), // output
			.hsync (boson_hsync3), // output
			.uart_in (sns3_dp[4]), // input sns_txd
			.uart_out (sns3_dn[4]) // output sns_rxd
			);

			simul_103993_serializer #(
			.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
			) simul_103993_serializer_3_i (
			.red (boson_pxd3[ 7:0]), // input[7:0]
			.green (boson_pxd3[15:8]), // input[7:0]
			.blue (8'h17), // input[7:0]
			.hs (boson_hsync3), // input
			.vs (boson_vsync3), // input
			.de (boson_dvalid3), // input
			.pclk (boson_pclk3), // input
			.dp (sns3_dp[2:0]), // output[2:0]
			.dn (sns3_dn[2:0]), // output[2:0]
			.clkp (sns3_clkp), // output
			.clkn (sns3_clkn) // output
			);

			simul_boson640 #(
			.DATA_FILE (BOSON_DATA_FILE), // "/input_data/pattern_160_120_16.dat"),
			.WIDTH (BOSON_WIDTH), // 160), 640),
			.HEIGHT (BOSON_HEIGHT), // 120), 513),
			.OUT_BITS (BOSON_OUT_BITS), // 16),
			.FPS (BOSON_FPS), // 60.0),
			.HSW (BOSON_HSW), // 8),
			.FP_BP (BOSON_FP_BP), // 22), // 102),
			.FP (BOSON_FP), // 12), 52),
			.VSW (BOSON_VSW) // 7) 87)
			) simul_boson640_4_i (
			.mrst (sns4_dp[7]), // input
			.single (boson_single), // input
			.ext_sync (sns4_ctl), // input
			.pxd (boson_pxd4), // output[15:0]
			.pclk (boson_pclk4), // output
			.dvalid (boson_dvalid4), // output
			.vsync (boson_vsync4), // output
			.hsync (boson_hsync4), // output
			.uart_in (sns4_dp[4]), // input sns_txd
			.uart_out (sns4_dn[4]) // output sns_rxd
			);

			simul_103993_serializer #(
			.PCLK_FREQ_MHZ(BOSON_FPS * 0.45) // 27.0)
			) simul_103993_serializer_4_i (
			.red (boson_pxd4[ 7:0]), // input[7:0]
			.green (boson_pxd4[15:8]), // input[7:0]
			.blue (8'h17), // input[7:0]
			.hs (boson_hsync4), // input
			.vs (boson_vsync4), // input
			.de (boson_dvalid4), // input
			.pclk (boson_pclk4), // input
			.dp (sns4_dp[2:0]), // output[2:0]
			.dn (sns4_dn[2:0]), // output[2:0]
			.clkp (sns4_clkp), // output
			.clkn (sns4_clkn) // output
			);



	`else		`else

fpga_version.vh

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -35,7 +35,9 @@
	* contains all the components and scripts required to completely simulate it		* contains all the components and scripts required to completely simulate it
	* with at least one of the Free Software programs.		* with at least one of the Free Software programs.
	*/		*/
	parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm		parameter FPGA_VERSION = 32'h03930200; // Initial Boson implementation
			//BOSON
			// parameter FPGA_VERSION = 32'h03930139; // Adding pullup on senspgm
	// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode		// parameter FPGA_VERSION = 32'h03930138; // Fixing output trigger in free running mode
	// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output		// parameter FPGA_VERSION = 32'h03930137; // longer reset, sync output
	// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq		// parameter FPGA_VERSION = 32'h03930136; // Fiixing spi_seq

includes/x393_parameters.vh

+33 −18

Original line number	Original line	Diff line number	Diff line
	@@ -429,6 +429,8 @@
	parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)		parameter SENSI2C_TBL_NABRD = 19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
	parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)		parameter SENSI2C_TBL_DLY = 20, // bit delay (number of mclk periods in 1/4 of SCL period)
	parameter SENSI2C_TBL_DLY_BITS= 8,		parameter SENSI2C_TBL_DLY_BITS= 8,
			parameter SENSI2C_TBL_EXTIF = 30, // extrenal interface mode (0 - i2c, 1 uart for boson)
			parameter SENSI2C_TBL_EXTIF_BITS= 2,


	parameter SENSI2C_STATUS = 'h1,		parameter SENSI2C_STATUS = 'h1,
	@@ -502,6 +504,14 @@
	//`ifdef HISPI		//`ifdef HISPI
	parameter SENS_CTRL_GP0= 12, // 14:12		parameter SENS_CTRL_GP0= 12, // 14:12
	parameter SENS_CTRL_GP1= 15, // 17:15		parameter SENS_CTRL_GP1= 15, // 17:15
			//`elsif BOSON
			parameter SENS_CTRL_GP2= 18, // 20:18 00 - float, 01 - low, 10 - high, 11 - trigger
			parameter SENS_CTRL_GP3= 21, // 23:21 00 - float, 01 - low, 10 - high, 11 - trigger
			parameter SENS_UART_EXTIF_EN = 0, // 1: 0
			parameter SENS_UART_XMIT_RST = 2, // 3: 2
			parameter SENS_UART_RECV_RST = 4, // 5: 4
			parameter SENS_UART_XMIT_START = 6, // 6
			parameter SENS_UART_RECV_NEXT = 7, // 7
	//`else		//`else
	parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20		parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
	parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,		parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
	@@ -658,6 +668,7 @@
	parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"		parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

	// parameters for the sensor-synchronous clock PLL		// parameters for the sensor-synchronous clock PLL
			// ALL PARAMETERS HERE SHOULD BE DEFINED (for use in C-generator)
	`define TWEAKING_IOSTANDARD		`define TWEAKING_IOSTANDARD
	`ifdef HISPI		`ifdef HISPI
	parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps		parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
	@@ -668,12 +679,18 @@
	`ifdef TWEAKING_IOSTANDARD		`ifdef TWEAKING_IOSTANDARD
	parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage		parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
	parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage		parameter SENSI2C_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
	// parameter PXD_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
	// parameter SENSI2C_IOSTANDARD = "LVCMOS18", // with 1.8 actually applied voltage
	`else		`else
	parameter PXD_IOSTANDARD = "LVCMOS18",		parameter PXD_IOSTANDARD = "LVCMOS18",
	parameter SENSI2C_IOSTANDARD = "LVCMOS18",		parameter SENSI2C_IOSTANDARD = "LVCMOS18",
	`endif		`endif
			`elsif BOSON
			parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
			parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
			parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
			parameter IPCLK_PHASE = 0.000,
			parameter IPCLK2X_PHASE = 0.000,
			parameter PXD_IOSTANDARD = "LVCMOS18",
			parameter SENSI2C_IOSTANDARD = "LVCMOS18",

	`else		`else
	parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps		parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
	@@ -689,8 +706,6 @@
	`ifdef TWEAKING_IOSTANDARD		`ifdef TWEAKING_IOSTANDARD
	parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry		parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry
	parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",		parameter HISPI_DIFF_TERM = "TRUE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
	// parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
	// parameter HISPI_IOSTANDARD = "PPDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
	parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"		parameter HISPI_IOSTANDARD = "LVDS_25", // "LVDS_25", "MINI_LVDS_25", "PPDS_25", "RSDS_25"
	`else		`else
	parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry		parameter HISPI_UNTUNED_SPLIT = "FALSE", // Very power-hungry

includes/x393_simulation_parameters.vh

+21 −4

Original line number	Original line	Diff line number	Diff line
	@@ -53,8 +53,8 @@
	parameter FCLK0_PERIOD = 41.667, // 24MHz		parameter FCLK0_PERIOD = 41.667, // 24MHz
	`endif		`endif
	parameter FCLK1_PERIOD = 0.0,		parameter FCLK1_PERIOD = 0.0,
			// for python (export to C header) all parameters should be defined
	`ifdef LWIR		//`ifdef LWIR
	parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",		parameter LWIR_DATA_FILE1 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
	parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",		parameter LWIR_DATA_FILE2 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
	parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",		parameter LWIR_DATA_FILE3 = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat",
	@@ -83,7 +83,17 @@

	parameter LWIR_GPIO_IN = 4'b0000,		parameter LWIR_GPIO_IN = 4'b0000,

	`endif		parameter BOSON_DATA_FILE = "/input_data/pattern_160_120_16.dat",
			parameter BOSON_WIDTH = 160, // 640
			parameter BOSON_HEIGHT = 120, // 513
			parameter BOSON_OUT_BITS = 16, // 16
			parameter BOSON_FPS = 60.0, // 60.0
			parameter BOSON_HSW = 8, // 8
			parameter BOSON_FP_BP = 22, // 102 (FP+BP)
			parameter BOSON_FP = 12, // 52
			parameter BOSON_VSW = 7, // 87, // in scan lines

			//`endif


	// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks		// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
	@@ -192,9 +202,16 @@
	parameter HISTOGRAM_START_PAGE = 20'h12345,		parameter HISTOGRAM_START_PAGE = 20'h12345,
	parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)		parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)

			`ifdef LWIR
			parameter WOI_WIDTH= 160,
			parameter WOI_HEIGHT= 122,
			`elsif BOSON
			parameter WOI_WIDTH= 160, // 640,
			parameter WOI_HEIGHT= 120, // 513,
			`else
	parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,		parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
	parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,		parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
			`endif
	parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2		parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
	// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]		// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
	parameter SENSOR_PRIORITY = 1000		parameter SENSOR_PRIORITY = 1000

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