starting to modify JPEG/JP4 compressor to remove double-pixel clock

compressor_jp/focus_sharp393.v

@@ -27,7 +27,8 @@
 */
 `include "system_defines.vh" 
 `timescale 1ns/1ps
-//TODO: Modify to work with other modes (now only on color)
+// TODO: Modify to work with other modes (now only on color)
+// NOTE: when removing clk2x, temporarily use clk here, just keep mode ==0 (disabled)
 module focus_sharp393(
     input             clk,          // pixel clock, posedge
     input             clk2x,        // 2x pixel clock

compressor_jp/huffman393.v

@@ -2,9 +2,9 @@
 ** -----------------------------------------------------------------------------**
 ** huffman333.v
 **
-** Huffman encoder for JPEG compressorrdy
+** Huffman encoder for JPEG compressor
 **
-** Copyright (C) 2002-20015 Elphelk, Inc
+** Copyright (C) 2002-20015 Elphel, Inc
 **
 ** -----------------------------------------------------------------------------**
 **  huffman393 is free software - hardware description language (HDL) code.

compressor_jp/huffman_merge_code_literal.v

+/*******************************************************************************
+ * Module: huffman_merge_code_literal
+ * Date:2015-10-22  
+ * Author: andrey     
+ * Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data,
+ * align result to MSB : {huffman,literal, {n{1'b0}}
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * huffman_merge_code_literal.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  huffman_merge_code_literal.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  huffman_merge_code_literal(
+    input             clk,
+    input             in_valid,
+    input      [15:0] huff_code,
+    input      [ 3:0] huff_code_len,
+    input      [10:0] literal,
+    input      [ 3:0] literal_len,
+    output reg        out_valid, // latency 5 from input
+    output reg [26:0] out_bits,  // latency 5 from input
+    output reg [ 4:0] out_len    // latency 5 from input
+);
+    reg        [10:0] lit0;
+    reg        [10:0] lit1;
+    reg        [10:0] lit2;
+    reg        [15:0] huff0; // SR-s will be extracted?
+    reg        [15:0] huff1;
+    reg        [15:0] huff2;
+    reg        [26:0] data3;
+    reg         [3:0] llen0;
+    reg         [3:0] llen1;
+    reg         [3:0] llen2;
+    reg         [4:0] olen3;
+    reg         [3:0] hlen0;
+    reg         [3:0] hlen1;
+    reg         [3:0] hlen2;
+    reg         [3:0] hlen2m1;
+    reg         [1:0] hlen3m1;
+    reg         [3:0] valid;
+    
+    always @ (posedge clk) begin
+        // input layer 0
+        lit0 <= literal;
+        llen0 <= literal_len;
+        huff0 <= huff_code;
+        hlen0 <= huff_code_len;
+        valid[0] <= in_valid;
+        // layer 1
+        casex (llen0[3:2])
+            2'b1x: lit1 <= lit0;
+            2'b01: lit1 <= {lit0[6:0],4'b0};
+            2'b00: lit1 <= {lit0[2:0],8'b0};
+        endcase
+        llen1 <= llen0;
+        huff1 <= huff0;
+        hlen1 <= hlen0;
+        valid[1] <= valid[0];
+        // layer 2
+        case (llen1[1:0])
+            2'b11: lit2 <= lit1;
+            2'b10: lit2 <= {lit1[9:0], 1'b0};
+            2'b01: lit2 <= {lit1[8:0], 2'b0};
+            2'b00: lit2 <= {lit1[7:0], 3'b0};
+        endcase
+        llen2 <= llen1;
+        huff2 <= huff1;
+        hlen2 <= hlen1;
+        hlen2m1 <= hlen1 - 1; // s0 
+        valid[2] <= valid[1];
+        // layer 3
+        olen3 <= hlen2 + llen2;
+        case (hlen2m1[3:2])
+            2'b11: data3 <= {huff2[15:0],lit2[10:0]};
+            2'b10: data3 <= {huff2[11:0],lit2[10:0], 4'b0};
+            2'b01: data3 <= {huff2[ 7:0],lit2[10:0], 8'b0};
+            2'b00: data3 <= {huff2[ 3:0],lit2[10:0],12'b0};
+        endcase
+        hlen3m1 <= hlen2m1[1:0];
+        valid[3] <= valid[2];
+        //layer4
+        out_len <= olen3;
+        case (hlen3m1[1:0])
+            2'b11: out_bits <= data3;
+            2'b10: out_bits <= {data3[25:0], 1'b0};
+            2'b01: out_bits <= {data3[24:0], 2'b0};
+            2'b00: out_bits <= {data3[23:0], 3'b0};
+        endcase
+        out_valid <= valid[3];
+    end    
+    
+
+endmodule
+

compressor_jp/varlen_encode393.v

@@ -39,15 +39,7 @@ module    varlen_encode393 (
     output reg   [3:0] l,        // [3:0] code length
     output reg   [3:0] l_late,// delayed l (sync to q)
     output reg  [10:0] q);    // [10:0]code
-/*
-    varlen_encode393 i_varlen_encode(.clk(clk),
-                                        .en(stuffer_was_rdy), //will enable registers. 0 - freeze
-                                        .start(steps[0]),
-                                        .d(sval[11:0]),        // 12-bit signed
-                                        .l(var_dl[ 3:0]),        // [3:0] code length
-                                        .l_late(var_dl_late[3:0]),
-                                        .q(var_do[10:0]));    // [10:0]code
-*/                                
+
     reg    [11:0] d1;
     reg    [10:0] q0;
     reg     [2:0] cycles;

compressor_jp/varlen_encode_snglclk.v

+/*
+** -----------------------------------------------------------------------------**
+** varlen_encode_snglclk.v
+**
+** Part of the Huffman encoder for JPEG compressor - variable length encoder
+**
+** Copyright (C) 2002-2015 Elphel, Inc
+**
+** -----------------------------------------------------------------------------**
+**  varlen_encode_snglclk.v is free software - hardware description language (HDL) code.
+** 
+**  This program is free software: you can redistribute it and/or modify
+**  it under the terms of the GNU General Public License as published by
+**  the Free Software Foundation, either version 3 of the License, or
+**  (at your option) any later version.
+**
+**  This program is distributed in the hope that it will be useful,
+**  but WITHOUT ANY WARRANTY; without even the implied warranty of
+**  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+**  GNU General Public License for more details.
+**
+**  You should have received a copy of the GNU General Public License
+**  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+** -----------------------------------------------------------------------------**
+**
+*/
+
+module    varlen_encode_snglclk (
+    input             clk,       // posedge
+    input       [11:0] d,        // 12-bit 2-s complement
+    output reg   [3:0] l,        // [3:0] code length, latency 2 clocks
+    output reg  [10:0] q);       // [10:0] literal, latency = 2 clocks
+
+    reg    [11:0] d1;
+
+    wire          this0 =  |d1[ 3:0];
+    wire          this1 =  |d1[ 7:4];
+    wire          this2 =  |d1[10:8];
+    wire    [1:0] codel0 = {|d1[ 3: 2],d1[ 3] || (d1[ 1] & ~d1[ 2])};
+    wire    [1:0] codel1 = {|d1[ 7: 6],d1[ 7] || (d1[ 5] & ~d1[ 6])};
+    wire    [1:0] codel2 = {|d1[   10],          (d1[ 9] & ~d1[10])};
+    wire    [3:0] codel =  this2? {2'b10,codel2[1:0]} :
+                     (this1? {2'b01, codel1[1:0]} :
+                             (this0 ? {2'b00,codel0[1:0]} : 4'b1111));    // after +1 will be 0;
+
+    always @(posedge clk) begin
+        d1[  11]    <=  d[11];
+        d1[10:0]    <=  d[11] ? -d[10:0] : d[10:0];
+    
+        q[10:0]     <= d1[11] ? ~d1[10:0] : d1[10:0];
+        l    <= codel[3:0]+1;    // needed only ASAP, valid only 2 cycles after start
+
+    end
+
+endmodule