minor code fixes to make it simulate with iverilog

.project

@@ -8,4 +8,11 @@
 	</buildSpec>
 	<natures>
 	</natures>
+	<linkedResources>
+		<link>
+			<name>ise_logs/ISEPartgen.log</name>
+			<type>1</type>
+			<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>
+		</link>
+	</linkedResources>
 </projectDescription>

control/camsync.v

@@ -246,8 +246,8 @@ module camsync       (sclk, // @negedge
       if (set_period) rep_en <= !high_zero;
     end
 
-    MSRL16 i_start_pclk16   (.Q(start_pclk16),   .A('hf), .CLK(pclk), .D(start_pclk[2]));
-    MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1));
+    MSRL16 i_start_pclk16   (.Q(start_pclk16),   .A(4'hf), .CLK(pclk), .D(start_pclk[2]));
+    MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));
 
 //! synchronize start from sclk to pclk    
 //! Generating repetition (period should be exactly N, not N+/-1) and output pulse

ddr/ddr.v

@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
     assign    Dq  = Dq_out;
 
     // Debug message
-    wire      Debug = 1'b1;
+//    wire      Debug = 1'b1;
 
     // Timing Check
     time      MRD_chk;

extras/imu_logger.v

@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps (
                         .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
                         .ra({channel[1:0],timestamp_sel[1:0]}),   // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
                         .dout(timestamps_rdata[15:0]));// output data
+wire [0:0] debug_state_unused;
 rs232_rcv i_rs232_rcv (.xclk(xclk),           // half frequency (80 MHz nominal)
                        .bitHalfPeriod(bitHalfPeriod[15:0]),  // half of the serial bit duration, in xclk cycles
                        .ser_di(ser_di),              // rs232 (ttl) serial data in
@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk),           // half frequency (80 MHz nominal)
                        .ser_do(ser_do),         // serial data out(@posedge xclk) LSB first!
                        .ser_do_stb(ser_do_stb),    // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
 //                       .debug(debug_state[4:0]),
-                       .debug(debug_state[15:12]),
+                       .debug({debug_state_unused,debug_state[15:12]}),
                        .bit_dur_cntr(debug_state[31:16]),
                        .bit_cntr(debug_state[11:7])
                        );

memctrl353/descrproc353.v

@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
    reg   [15:0]   linAddr;
 //   wire  [15:0]   linAddr;      //replacing with latches to ease timing
    wire  [15:0]   linAddr_input;
-//   assign linAddr_input[15:0] = (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}) +{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used    
+   wire [4:0] descr_stat_inc=descr_stat[8:4]+1;    
    assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
 
     
     always @ (negedge clk) if (stepsEn[1]) begin      // address should be 1
+//memctrl353/descrproc353.v:504: error: Concatenation operand "((descr_dyn['sd4:'sd0])==(descr_stat['sd13:'sd9]))?((descr_stat['sd8:'sd4])+('sd1)):(5'd0)" has indefinite width.    
+//      seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
+//                           ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
       seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
-                           ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
+                           ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
       sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
       linAddr[15:0]   <= linAddr_input[15:0];
-//      linAddr[15:0]   <= (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]})+{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
       nxtTL <= nxtTLw;
       tileX[ 9:0] <= nxtTLw?  10'b0 : (descr_dyn[9:0]+1);   // bits [9:5] are garbage if (mode==0)
 

sensor/lens_flat.v

@@ -174,14 +174,14 @@ module lens_flat (sclk,      /// system clock @negedge
 //      .A(FXY[17]?18'h1ffff:FXY[17:0]),    // 18-bit multiplier input
       .A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)),    // 18-bit multiplier input
       .B({1'b0,scales[~color[1:0]]}),    // 18-bit multiplier input
-      .BCIN(0), // 18-bit cascade input
+      .BCIN(18'b0), // 18-bit cascade input
       .CEA(lens_corr_out[0]), // Clock enable input for the A port
       .CEB(lens_corr_out[0]), // Clock enable input for the B port
       .CEP(lens_corr_out[1]), // Clock enable input for the P port
       .CLK(pclk), // Clock input
-      .RSTA(0), // Synchronous reset input for the A port
-      .RSTB(0), // Synchronous reset input for the B port
-      .RSTP(0)  // Synchronous reset input for the P port
+      .RSTA(1'b0), // Synchronous reset input for the A port
+      .RSTB(1'b0), // Synchronous reset input for the B port
+      .RSTP(1'b0)  // Synchronous reset input for the P port
    );
 
 
@@ -195,14 +195,14 @@ module lens_flat (sclk,      /// system clock @negedge
       .P(mult_second_res[35:0]),    // 36-bit multiplier output
       .A(pix_zero[17:0]),    // 18-bit multiplier input
       .B(mult_first_scaled[17:0]),    // 18-bit multiplier input - always positive
-      .BCIN(0), // 18-bit cascade input
+      .BCIN(18'b0), // 18-bit cascade input
       .CEA(lens_corr_out[2]), // Clock enable input for the A port
       .CEB(lens_corr_out[0]), // Clock enable input for the B port
       .CEP(lens_corr_out[3]), // Clock enable input for the P port
       .CLK(pclk), // Clock input
-      .RSTA(0), // Synchronous reset input for the A port
-      .RSTB(0), // Synchronous reset input for the B port
-      .RSTP(0)  // Synchronous reset input for the P port
+      .RSTA(1'b0), // Synchronous reset input for the A port
+      .RSTB(1'b0), // Synchronous reset input for the B port
+      .RSTP(1'b0)  // Synchronous reset input for the P port
    );
 
 
@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
            .first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
            .next(newline), /// calcualte next pixel
            .F0(C[18:0]),   /// value of the output in the first column (before saturation), 18 bit, unsigned
-           .ERR0(0),       /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
+           .ERR0(24'b0),       /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
            .A0(AY[18:0]),  /// Ay
            .B0(BY[20:0]),  /// By,  signed
            .F(FY[18:0]),

sensor/sensor_phase353.v

@@ -72,10 +72,11 @@ NET "hact_length*" TIG;
 */
 
   parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width
-
-  parameter IS_SIMUL=0;
-//synthesis translate_off
+`ifdef IVERILOG
   parameter IS_SIMUL=1;
+`else
+  parameter IS_SIMUL=0;
+`endif  
 //synthesis translate_on
 
   input         cclk;       // command clock (posedge, invert on input if needed)

x353.v

@@ -533,23 +533,23 @@ wire       sensor_trigger; // signal to start CMOS sensor in sync mode
 wire       confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor)
                                     // mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation
 `ifdef debug_compressor
-wire [31:0] printk_compressor;
+    wire [31:0] printk_compressor;
 `endif
 //ia
 
 `ifdef debug_stuffer
-wire [7:0]  testwire;
+    wire [7:0]  testwire;
 //wire [31:0] printk;
-wire [3:0]  tst_stuf_etrax;
-reg  [3:0]  tst_cmd_cntr;
-reg         tst_rdy_after_eot;
+    wire [3:0]  tst_stuf_etrax;
+    reg  [3:0]  tst_cmd_cntr;
+    reg         tst_rdy_after_eot;
 //         ,.test1( test_fifo[3:0])
   //       ,.test2( test_dma_wcntr[3:0])
-wire dma0_enabled; // just for debug
-wire dma1_enabled; // just for debug
+    wire dma0_enabled; // just for debug
+    wire dma1_enabled; // just for debug
 `endif
 `ifdef debug_dma_count
-  wire [31:0] printk;
+    wire [31:0] printk;
 `endif
 /*
 //xfer_over_irq