diff --git a/.project b/.project
index 6a1859766d825e19f826fb2d86eeba623858f101..c22a603f47fa87231b18819405bec6f6d93a9eff 100644
--- a/.project
+++ b/.project
@@ -8,4 +8,11 @@
+
+
+ ise_logs/ISEPartgen.log
+ 1
+ /home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log
+
+
diff --git a/control/camsync.v b/control/camsync.v
index aac7c15fda623c00dba888351a5a98224f814ec8..dbf83c96a7c4ab9d8e876f1216448912aa78872b 100644
--- a/control/camsync.v
+++ b/control/camsync.v
@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge
if (set_period) rep_en <= !high_zero;
end
- MSRL16 i_start_pclk16 (.Q(start_pclk16), .A('hf), .CLK(pclk), .D(start_pclk[2]));
- MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1));
+ MSRL16 i_start_pclk16 (.Q(start_pclk16), .A(4'hf), .CLK(pclk), .D(start_pclk[2]));
+ MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));
//! synchronize start from sclk to pclk
//! Generating repetition (period should be exactly N, not N+/-1) and output pulse
diff --git a/coring.dat.v b/coring.dat
similarity index 100%
rename from coring.dat.v
rename to coring.dat
diff --git a/ddr/ddr.v b/ddr/ddr.v
index b182f02ce2f37509ef6013a5db4bc258db245ee4..cfee408cd812bde0bc80c1cab0b0e6ea30dffa99 100644
--- a/ddr/ddr.v
+++ b/ddr/ddr.v
@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
assign Dq = Dq_out;
// Debug message
- wire Debug = 1'b1;
+// wire Debug = 1'b1;
// Timing Check
time MRD_chk;
diff --git a/extras/imu_logger.v b/extras/imu_logger.v
index 68706386b66f2ae9614553be78d72e69a10556f6..2ad65e0b57dd9a5104408550e73441bc9ca42ffa 100644
--- a/extras/imu_logger.v
+++ b/extras/imu_logger.v
@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data
+wire [0:0] debug_state_unused;
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in
@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]),
- .debug(debug_state[15:12]),
+ .debug({debug_state_unused,debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7])
);
diff --git a/compressor/focus_filt.dat b/focus_filt.dat
similarity index 100%
rename from compressor/focus_filt.dat
rename to focus_filt.dat
diff --git a/memctrl353/descrproc353.v b/memctrl353/descrproc353.v
index c85e7adb38e5a5b12a73342624328dac56c26147..5b455d4e0761279ce8994ea3db5c80ef38c5bba2 100644
--- a/memctrl353/descrproc353.v
+++ b/memctrl353/descrproc353.v
@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
reg [15:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input;
-// assign linAddr_input[15:0] = (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}) +{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
+ wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
+//memctrl353/descrproc353.v:504: error: Concatenation operand "((descr_dyn['sd4:'sd0])==(descr_stat['sd13:'sd9]))?((descr_stat['sd8:'sd4])+('sd1)):(5'd0)" has indefinite width.
+// seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
+// ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
- ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
+ ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0];
-// linAddr[15:0] <= (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]})+{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
diff --git a/sensor/lens_flat.v b/sensor/lens_flat.v
index b9abc4715672106b3d982d827b4f7901d9e7b0d1..6bb59793cf60e449b6be4da75bd80887c36edb82 100644
--- a/sensor/lens_flat.v
+++ b/sensor/lens_flat.v
@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
- .BCIN(0), // 18-bit cascade input
+ .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input
- .RSTA(0), // Synchronous reset input for the A port
- .RSTB(0), // Synchronous reset input for the B port
- .RSTP(0) // Synchronous reset input for the P port
+ .RSTA(1'b0), // Synchronous reset input for the A port
+ .RSTB(1'b0), // Synchronous reset input for the B port
+ .RSTP(1'b0) // Synchronous reset input for the P port
);
@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge
.P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
- .BCIN(0), // 18-bit cascade input
+ .BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input
- .RSTA(0), // Synchronous reset input for the A port
- .RSTB(0), // Synchronous reset input for the B port
- .RSTP(0) // Synchronous reset input for the P port
+ .RSTA(1'b0), // Synchronous reset input for the A port
+ .RSTB(1'b0), // Synchronous reset input for the B port
+ .RSTP(1'b0) // Synchronous reset input for the P port
);
@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
- .ERR0(0), /// initial value of the running error (-2.0 start;
- end
- always @start
- begin : timeout
- out = 1;
- # duration out = 0;
- end
+
+module oneshot(trigger,
+ out);
+ input trigger;
+ output out;
+ reg out;
+ event start;
+ parameter duration=4000;
+ initial out= 0;
+ always @ (posedge trigger) begin
+ disable timeout;
+ #0 -> start;
+ end
+ always @start
+ begin : timeout
+ out = 1;
+ # duration out = 0;
+ end
endmodule
-module dly5taps (dly_in,
- dly_out);
- input dly_in;
- output [5:1] dly_out;
- reg [5:1] dly_out;
- parameter dly=6; // delay per tap, ns
-
- always @ (dly_in) # dly dly_out[1] <= dly_in;
- always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1];
- always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2];
- always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3];
- always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4];
+module dly5taps (dly_in,
+ dly_out);
+ input dly_in;
+ output [5:1] dly_out;
+ reg [5:1] dly_out;
+ parameter dly=6; // delay per tap, ns
+
+ always @ (dly_in) # dly dly_out[1] <= dly_in;
+ always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1];
+ always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2];
+ always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3];
+ always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4];
endmodule