Commit fbce217a authored by Andrey Filippov's avatar Andrey Filippov

minor code fixes to make it simulate with iverilog

parent 63198817
......@@ -8,4 +8,11 @@
</buildSpec>
<natures>
</natures>
<linkedResources>
<link>
<name>ise_logs/ISEPartgen.log</name>
<type>1</type>
<location>/home/andrey/git/x353/ise_logs/ISEPartgen-20150725173339957.log</location>
</link>
</linkedResources>
</projectDescription>
......@@ -246,8 +246,8 @@ module camsync (sclk, // @negedge
if (set_period) rep_en <= !high_zero;
end
MSRL16 i_start_pclk16 (.Q(start_pclk16), .A('hf), .CLK(pclk), .D(start_pclk[2]));
MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A('hf), .CLK(pclk), .D(trigger1));
MSRL16 i_start_pclk16 (.Q(start_pclk16), .A(4'hf), .CLK(pclk), .D(start_pclk[2]));
MSRL16 i_strigger1_dly16(.Q(trigger1_dly16), .A(4'hf), .CLK(pclk), .D(trigger1));
//! synchronize start from sclk to pclk
//! Generating repetition (period should be exactly N, not N+/-1) and output pulse
......
......@@ -225,7 +225,7 @@ module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
assign Dq = Dq_out;
// Debug message
wire Debug = 1'b1;
// wire Debug = 1'b1;
// Timing Check
time MRD_chk;
......
......@@ -311,6 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused;
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in
......@@ -322,7 +323,7 @@ rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]),
.debug(debug_state[15:12]),
.debug({debug_state_unused,debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7])
);
......
......@@ -497,16 +497,18 @@ myRAM_WxD_D #( .DATA_WIDTH(22),.DATA_DEPTH(2))
reg [15:0] linAddr;
// wire [15:0] linAddr; //replacing with latches to ease timing
wire [15:0] linAddr_input;
// assign linAddr_input[15:0] = (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}) +{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
wire [4:0] descr_stat_inc=descr_stat[8:4]+1;
assign linAddr_input[15:0] = padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]};
always @ (negedge clk) if (stepsEn[1]) begin // address should be 1
//memctrl353/descrproc353.v:504: error: Concatenation operand "((descr_dyn['sd4:'sd0])==(descr_stat['sd13:'sd9]))?((descr_stat['sd8:'sd4])+('sd1)):(5'd0)" has indefinite width.
// seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
// ({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
seq_par[5:0] <= mode?({1'b0,descr_stat[13:9]}+((descr_stat[8:4]==5'h1f)?2'h2:2'h1)): //fixed bug with pages where number of hor. tiles is multiple of 0x10
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat[8:4]+1):5'b0});
({1'b0,(descr_dyn[4:0]==descr_stat[13:9])?(descr_stat_inc):5'b0});
sa[7:3] <= mode?descr_dyn[4:0]:5'b0;
linAddr[15:0] <= linAddr_input[15:0];
// linAddr[15:0] <= (padlen[4:0]*{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]})+{descr_dyn[19:10],mode?4'b0:descr_dyn[9:6]}; // Result MSB not used
nxtTL <= nxtTLw;
tileX[ 9:0] <= nxtTLw? 10'b0 : (descr_dyn[9:0]+1); // bits [9:5] are garbage if (mode==0)
......
......@@ -174,14 +174,14 @@ module lens_flat (sclk, /// system clock @negedge
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
.BCIN(0), // 18-bit cascade input
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
......@@ -195,14 +195,14 @@ module lens_flat (sclk, /// system clock @negedge
.P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
.BCIN(0), // 18-bit cascade input
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(0), // Synchronous reset input for the A port
.RSTB(0), // Synchronous reset input for the B port
.RSTP(0) // Synchronous reset input for the P port
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
......@@ -216,7 +216,7 @@ lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.ERR0(24'b0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AY[18:0]), /// Ay
.B0(BY[20:0]), /// By, signed
.F(FY[18:0]),
......
......@@ -72,10 +72,11 @@ NET "hact_length*" TIG;
*/
parameter MIN_VACT_PERIOD=130; // 3-130, to increase maximal value (130) - chnge counter width
parameter IS_SIMUL=0;
//synthesis translate_off
`ifdef IVERILOG
parameter IS_SIMUL=1;
`else
parameter IS_SIMUL=0;
`endif
//synthesis translate_on
input cclk; // command clock (posedge, invert on input if needed)
......
......@@ -533,23 +533,23 @@ wire sensor_trigger; // signal to start CMOS sensor in sync mode
wire confirmFrame2Compressor; // pulse to start reading a new frame to buffer for compressor (generated at start of each frame by the compressor)
// mcontr will stop to read to channel FIFO at the end of frame, wait for confirmation
`ifdef debug_compressor
wire [31:0] printk_compressor;
wire [31:0] printk_compressor;
`endif
//ia
`ifdef debug_stuffer
wire [7:0] testwire;
wire [7:0] testwire;
//wire [31:0] printk;
wire [3:0] tst_stuf_etrax;
reg [3:0] tst_cmd_cntr;
reg tst_rdy_after_eot;
wire [3:0] tst_stuf_etrax;
reg [3:0] tst_cmd_cntr;
reg tst_rdy_after_eot;
// ,.test1( test_fifo[3:0])
// ,.test2( test_dma_wcntr[3:0])
wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug
wire dma0_enabled; // just for debug
wire dma1_enabled; // just for debug
`endif
`ifdef debug_dma_count
wire [31:0] printk;
wire [31:0] printk;
`endif
/*
//xfer_over_irq
......
......@@ -4,15 +4,15 @@
//`define PF
//compressor waits for sensor
`define TEST_ABORT
`define SYNC_COMPRESS
//TODO: when TEST_INSUFFICIENT_DATA, i_color_proc does not generate last0, because all_ready==0 when bcntr==0,
// i.e. override ignore/ready from noMoreData until last0
`define SYNC_COMPRESS
//TODO: when TEST_INSUFFICIENT_DATA, i_color_proc does not generate last0, because all_ready==0 when bcntr==0,
// i.e. override ignore/ready from noMoreData until last0
//`define TEST_INSUFFICIENT_DATA
`define TRIGGERED_MODE
`define CONTINUOUS_COMPRESSION
//`define TOO_HIGH_FPS
`define ALL_SLOW_FPS
`define ALL_SLOW_FPS
`define TEST_NO_WAIT_FRAME_SYNC
//`define TRY_SLOW_FPS
/// Enable flushing unfinished frame if there is no data in the memory (end of frame)
......@@ -25,9 +25,9 @@
//`define FORCE_INTERNAL_TIMESTAMP // always use internal TS, ignore incoming
`define TEST_BAD_FRAME //abbreviate one frame
`define TEST_IMU
`define TEST_BAD_FRAME //abbreviate one frame
`define TEST_IMU
module testbench353();
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
......@@ -40,6 +40,13 @@ module testbench353();
parameter CLK1_PER = 10.4; //96MHz
parameter CLK3_PER = 83.33; //12MHz
parameter CPU_PER=10.4;
`ifdef IVERILOG
initial $display("IVERILOG is defined");
`include "IVERILOG_INCLUDE.v"
`else
initial $display("IVERILOG is not defined");
parameter lxtname = "x353_1.lxt";
`endif
`ifdef SYNC_COMPRESS
parameter DEPEND=1'b1;
......@@ -84,12 +91,12 @@ module testbench353();
wire [23:0] TRIG_PERIOD;
assign FRAME_COMPRESS_CYCLES=(WOI_WIDTH &'h3fff0) * (WOI_HEIGHT &'h3fff0) * CYCLES_PER_PIXEL + FPGA_XTRA_CYCLES;
assign FRAME_COMPRESS_CYCLES_INPUT=(FRAME_COMPRESS_CYCLES*CLK0_PER)/CLK1_PER;
`ifdef ALL_SLOW_FPS
`ifdef ALL_SLOW_FPS
assign TRIG_PERIOD = 2* FRAME_COMPRESS_CYCLES_INPUT; /// twice slower than maximal compressor can do
`else
`ifdef TOO_HIGH_FPS
assign TRIG_PERIOD = VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK); /// maximal sensor can do
`else
`else
assign TRIG_PERIOD = FRAME_COMPRESS_CYCLES_INPUT; /// maximal compressor can do
// parameter TRIG_PERIOD= 1.5*(VIRTUAL_WIDTH * (VIRTUAL_HEIGHT + TRIG_LINES + VBLANK)); ///TODO: Improve (calculate)
`endif
......@@ -114,25 +121,25 @@ module testbench353();
parameter X313_WA_IOPINS= 'h70; // bits [31:24] - enable channels (channel 0 -software, enabled at FPGA init)
parameter X313_WA_IOPINS_EN_TRIG_OUT= 'h0c000000;
parameter X313_WA_IOPINS_DIS_TRIG_OUT='h08000000;
parameter X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
parameter X313_WA_IOPINS_DIS_IMU_OUT='h80000000;
parameter X313_WA_IMU_DATA= 'h7e;
parameter X313_WA_IMU_CTRL= 'h7f;
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
parameter X313_RA_IMU_STATUS= 'h7f; // LSB==ready
parameter IMU_PERIOD= 'h800; // normal period
parameter IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready
parameter IMU_PERIOD= 'h800; // normal period
parameter IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready
parameter IMU_BIT_DURATION= 'h3; // actual F(scl) will be F(xclk)/2/(IMU_BIT_DURATION+1)
parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec
parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec
parameter IMU_GPS_BIT_PERIOD='h20; // serial communication duration of a bit (in system clocks)
// use start of trigger as a timestamp (in async mode to prevent timestamp jitter)
// parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE!
......@@ -221,74 +228,74 @@ module testbench353();
reg TEST_CPU_WR_OK;
reg TEST_CPU_RD_OK;
reg SERIAL_BIT = 1'b1;
reg GPS1SEC = 1'b0;
reg ODOMETER_PULSE= 1'b0;
integer SERIAL_DATA_FD;
reg IMU_DATA_READY;
/*
parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec
*/
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
reg SERIAL_BIT = 1'b1;
reg GPS1SEC = 1'b0;
reg ODOMETER_PULSE= 1'b0;
integer SERIAL_DATA_FD;
reg IMU_DATA_READY;
/*
parameter IMU_READY_PERIOD=100000; //100usec
parameter IMU_NREADY_DURATION=10000; //10usec
*/
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
wire IMU_SCL=EXT[0];
wire IMU_SDA=EXT[1];
wire IMU_MOSI=EXT[2];
wire IMU_MISO=EXT[3];
reg IMU_EN;
wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN;
reg IMU_SCLK;
reg IMU_MOSI_REVA;
reg IMU_103695REVA;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
wire IMU_MISO=EXT[3];
reg IMU_EN;
wire IMU_ACTIVE;
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN;
reg IMU_SCLK;
reg IMU_MOSI_REVA;
reg IMU_103695REVA;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
assign IMU_MOSI_OUT=IMU_103695REVA?IMU_MOSI_REVA:IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
assign EXT[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`endif
end
assign EXT[4]=SERIAL_BIT;
assign EXT[5]=GPS1SEC;
assign EXT[6]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA<= IMU_NMOSI;
`endif
// Inputs
wire [11:0] PXD;
......@@ -552,7 +559,8 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
initial begin
$dumpfile("x353.lxt");
// $dumpfile("x353.lxt");
$dumpfile(lxtname);
$dumpvars(0,testbench353);
TTRIG = 1;
CLK3 = 0;
......@@ -577,41 +585,41 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
BUS[7:0] =8'h0;
BUS_EN[7:0] =8'h0;
BUS_RQ[7:0] =8'h0;
FOCUS_MODE = 2'h0;
FOCUS_MODE = 2'h0;
IMU_103695REVA = 1'b0;
`ifdef LATE_DMA
`else
dma_en(0,1);
`endif
// temporary for IMU testing
// #200000;
`endif
// temporary for IMU testing
// #200000;
// $finish;
#250000;
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
dma_en(0,1);
#480000;
//#480000;
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
//#480000;
$finish;
`ifdef TEST_IMU
`ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
......@@ -630,7 +638,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -649,8 +657,8 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -668,7 +676,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -686,7 +694,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -704,7 +712,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -722,7 +730,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -740,7 +748,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -758,39 +766,40 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
$finish;
`endif
$finish;
//#250000;
// dma_en(0,1);
//#480000;
dma_en(0,1);
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA = 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
dma_en(0,1);
#480000;
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h4c0000); // set debug_config to 4'h3
cpu_wr(X313_WA_IMU_CTRL, 1); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_BIT_DURATION | 16'h1000); // set bit counter and stall of 16 sclk half-periods
wait (IMU_CS); // wait IMU inactive
IMU_103695REVA <= 1'b1; // switch to revision "A"
cpu_wr(X313_WA_IMU_CTRL, 3); // select config register
cpu_wr(X313_WA_IMU_DATA, 'h5c0000); // set debug_config to 4'h7
cpu_wr(X313_WA_IMU_CTRL, 0); // select period register
cpu_wr(X313_WA_IMU_DATA, IMU_AUTO_PERIOD); // set period defined by IMU
#480000;
$finish;
`ifdef TEST_IMU
`ifdef TEST_IMU
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
......@@ -809,7 +818,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -828,8 +837,8 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -847,7 +856,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -865,7 +874,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -883,7 +892,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -901,7 +910,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -919,7 +928,7 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_STATUS); $display ("IMU_STATUS =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
......@@ -937,11 +946,11 @@ $finish;
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
cpu_rd_ce1(X313_RA_IMU_DATA); $display ("IMU_DATA =%x",CPU_DI[31:0]);
`endif
`endif
$finish;
//#250000;
......@@ -951,30 +960,30 @@ $finish;
$finish;
end
`ifdef TEST_IMU
initial begin
#10000;
while (!$feof (SERIAL_DATA_FD)) begin
repeat (20*IMU_BIT_DURATION) begin wait (CLK0); wait (~CLK0); end
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b1;
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b0;
send_serial_line;
send_serial_bit('h0a);
send_serial_pause;
send_serial_pause;
ODOMETER_PULSE=1'b1;
send_serial_pause;
ODOMETER_PULSE=1'b0;
`ifdef TEST_IMU
initial begin
#10000;
while (!$feof (SERIAL_DATA_FD)) begin
repeat (20*IMU_BIT_DURATION) begin wait (CLK0); wait (~CLK0); end
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b1;
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b0;
send_serial_line;
send_serial_bit('h0a);
send_serial_pause;
send_serial_pause;
ODOMETER_PULSE=1'b1;
send_serial_pause;
ODOMETER_PULSE=1'b0;
// repeat (20) send_serial_pause;
end
end
`endif